1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
4 *
5 * Common Clock Framework support for Exynos990.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <dt-bindings/clock/samsung,exynos990.h>
14
15 #include "clk.h"
16 #include "clk-exynos-arm64.h"
17 #include "clk-pll.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
21 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
22 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
23
24 /* ---- CMU_TOP ------------------------------------------------------------- */
25
26 /* Register Offset definitions for CMU_TOP (0x1a330000) */
27 #define PLL_LOCKTIME_PLL_G3D 0x0000
28 #define PLL_LOCKTIME_PLL_MMC 0x0004
29 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
30 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
31 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
32 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
33 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
34 #define PLL_CON0_PLL_G3D 0x0100
35 #define PLL_CON3_PLL_G3D 0x010c
36 #define PLL_CON0_PLL_MMC 0x0140
37 #define PLL_CON3_PLL_MMC 0x014c
38 #define PLL_CON0_PLL_SHARED0 0x0180
39 #define PLL_CON3_PLL_SHARED0 0x018c
40 #define PLL_CON0_PLL_SHARED1 0x01c0
41 #define PLL_CON3_PLL_SHARED1 0x01cc
42 #define PLL_CON0_PLL_SHARED2 0x0200
43 #define PLL_CON3_PLL_SHARED2 0x020c
44 #define PLL_CON0_PLL_SHARED3 0x0240
45 #define PLL_CON3_PLL_SHARED3 0x024c
46 #define PLL_CON0_PLL_SHARED4 0x0280
47 #define PLL_CON3_PLL_SHARED4 0x028c
48 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
49 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
50 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
51 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1010
52 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS 0x1014
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1018
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x101c
55 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1020
56 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1024
57 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1028
58 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x102c
59 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
60 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1034
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS 0x1038
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x103c
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1040
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP 0x1044
65 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
66 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
67 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU 0x1050
68 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUS 0x1054
69 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM 0x1058
70 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x105c
71 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1060
72 #define CLK_CON_MUX_MUX_CLKCMU_DPU_ALT 0x1064
73 #define CLK_CON_MUX_MUX_CLKCMU_DSP_BUS 0x1068
74 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x106c
75 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1070
76 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1074
77 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1078
78 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x107c
79 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1080
80 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG 0x1084
81 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1088
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x108c
83 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x1090
84 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD 0x1094
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD 0x1098
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x109c
87 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a0
88 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10a4
89 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10a8
90 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS 0x10ac
91 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC 0x10b0
92 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU 0x10b4
93 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0 0x10b8
94 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD 0x10bc
95 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c0
96 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c4
97 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10c8
98 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10cc
99 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10d0
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10d4
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d8
102 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10dc
103 #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
104 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
105 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
106 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
107 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
108 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
109 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x180c
110 #define CLK_CON_DIV_CLKCMU_BUS1_SSS 0x1810
111 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1814
112 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1818
113 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x181c
114 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1820
115 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1824
116 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1828
117 #define CLK_CON_DIV_CLKCMU_CMU_BOOST 0x182c
118 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
119 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS 0x1834
120 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
121 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
122 #define CLK_CON_DIV_CLKCMU_CPUCL2_BUSP 0x1840
123 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1844
124 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1848
125 #define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU 0x184c
126 #define CLK_CON_DIV_CLKCMU_DNC_BUS 0x1850
127 #define CLK_CON_DIV_CLKCMU_DNC_BUSM 0x1854
128 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x1858
129 #define CLK_CON_DIV_CLKCMU_DSP_BUS 0x185c
130 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1860
131 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1864
132 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
133 #define CLK_CON_DIV_CLKCMU_HPM 0x186c
134 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1870
135 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1874
136 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1878
137 #define CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG 0x187c
138 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1880
139 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x1884
140 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1888
141 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD 0x188c
142 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD 0x1890
143 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1894
144 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x1898
145 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x189c
146 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18a0
147 #define CLK_CON_DIV_CLKCMU_MCSC_BUS 0x18a4
148 #define CLK_CON_DIV_CLKCMU_MCSC_GDC 0x18a8
149 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x18ac
150 #define CLK_CON_DIV_CLKCMU_MFC0_MFC0 0x18b0
151 #define CLK_CON_DIV_CLKCMU_MFC0_WFD 0x18b4
152 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18b8
153 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x18bc
154 #define CLK_CON_DIV_CLKCMU_OTP 0x18c0
155 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18c4
156 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c8
157 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18cc
158 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18d0
159 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18d4
160 #define CLK_CON_DIV_CLKCMU_SSP_BUS 0x18d8
161 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18dc
162 #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
163 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
164 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
165 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
166 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
167 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
168 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1900
169 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1904
170 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1908
171 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x190c
172 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x1910
173 #define CLK_CON_DIV_PLL_SHARED4_DIV3 0x1914
174 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x1918
175 #define CLK_CON_GAT_CLKCMU_G3D_BUS 0x2000
176 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2004
177 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
178 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x200c
179 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2010
180 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x2014
181 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS 0x2018
182 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x201c
183 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2020
184 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2024
185 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2028
186 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x202c
187 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2030
188 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2034
189 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x2038
190 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x203c
191 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2040
192 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP 0x2044
193 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2048
194 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x204c
195 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU 0x2050
196 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUS 0x2054
197 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM 0x2058
198 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x205c
199 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x2060
200 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2064
201 #define CLK_CON_GAT_GATE_CLKCMU_DSP_BUS 0x2068
202 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x206c
203 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2070
204 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2074
205 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x2078
206 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x207c
207 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x2080
208 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x2084
209 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG 0x2088
210 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x208c
211 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD 0x2090
212 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x2094
213 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD 0x2098
214 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD 0x209c
215 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20a0
216 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20a4
217 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20a8
218 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20ac
219 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS 0x20b0
220 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC 0x20b4
221 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0 0x20bc
222 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD 0x20c0
223 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c4
224 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c8
225 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20cc
226 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20d0
227 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d4
228 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d8
229 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20dc
230 #define CLK_CON_GAT_GATE_CLKCMU_SSP_BUS 0x20e0
231 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x20e4
232 #define CLK_CON_GAT_GATE_CLKCMU_VRA_BUS 0x20e8
233
234 static const unsigned long top_clk_regs[] __initconst = {
235 PLL_LOCKTIME_PLL_G3D,
236 PLL_LOCKTIME_PLL_MMC,
237 PLL_LOCKTIME_PLL_SHARED0,
238 PLL_LOCKTIME_PLL_SHARED1,
239 PLL_LOCKTIME_PLL_SHARED2,
240 PLL_LOCKTIME_PLL_SHARED3,
241 PLL_LOCKTIME_PLL_SHARED4,
242 PLL_CON3_PLL_G3D,
243 PLL_CON3_PLL_MMC,
244 PLL_CON3_PLL_SHARED0,
245 PLL_CON3_PLL_SHARED1,
246 PLL_CON3_PLL_SHARED2,
247 PLL_CON3_PLL_SHARED3,
248 PLL_CON3_PLL_SHARED4,
249 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
250 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
251 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
252 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
253 CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS,
254 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
255 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
256 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
257 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
258 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
259 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
260 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
261 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
262 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
263 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
264 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
265 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP,
266 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
267 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
268 CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
269 CLK_CON_MUX_MUX_CLKCMU_DNC_BUS,
270 CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM,
271 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
272 CLK_CON_MUX_MUX_CLKCMU_DPU,
273 CLK_CON_MUX_MUX_CLKCMU_DPU_ALT,
274 CLK_CON_MUX_MUX_CLKCMU_DSP_BUS,
275 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
276 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
277 CLK_CON_MUX_MUX_CLKCMU_HPM,
278 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
279 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
280 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
281 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG,
282 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
283 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
284 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
285 CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD,
286 CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
287 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
288 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
289 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
290 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
291 CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS,
292 CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC,
293 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
294 CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
295 CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
296 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
297 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
298 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
299 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
300 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
301 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
302 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
303 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
304 CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
305 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
306 CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
307 CLK_CON_DIV_CLKCMU_APM_BUS,
308 CLK_CON_DIV_CLKCMU_AUD_CPU,
309 CLK_CON_DIV_CLKCMU_BUS0_BUS,
310 CLK_CON_DIV_CLKCMU_BUS1_BUS,
311 CLK_CON_DIV_CLKCMU_BUS1_SSS,
312 CLK_CON_DIV_CLKCMU_CIS_CLK0,
313 CLK_CON_DIV_CLKCMU_CIS_CLK1,
314 CLK_CON_DIV_CLKCMU_CIS_CLK2,
315 CLK_CON_DIV_CLKCMU_CIS_CLK3,
316 CLK_CON_DIV_CLKCMU_CIS_CLK4,
317 CLK_CON_DIV_CLKCMU_CIS_CLK5,
318 CLK_CON_DIV_CLKCMU_CMU_BOOST,
319 CLK_CON_DIV_CLKCMU_CORE_BUS,
320 CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
321 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
322 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
323 CLK_CON_DIV_CLKCMU_CPUCL2_BUSP,
324 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
325 CLK_CON_DIV_CLKCMU_CSIS_BUS,
326 CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
327 CLK_CON_DIV_CLKCMU_DNC_BUS,
328 CLK_CON_DIV_CLKCMU_DNC_BUSM,
329 CLK_CON_DIV_CLKCMU_DNS_BUS,
330 CLK_CON_DIV_CLKCMU_DSP_BUS,
331 CLK_CON_DIV_CLKCMU_G2D_G2D,
332 CLK_CON_DIV_CLKCMU_G2D_MSCL,
333 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
334 CLK_CON_DIV_CLKCMU_HPM,
335 CLK_CON_DIV_CLKCMU_HSI0_BUS,
336 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
337 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
338 CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
339 CLK_CON_DIV_CLKCMU_HSI1_BUS,
340 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
341 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
342 CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
343 CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
344 CLK_CON_DIV_CLKCMU_HSI2_BUS,
345 CLK_CON_DIV_CLKCMU_HSI2_PCIE,
346 CLK_CON_DIV_CLKCMU_IPP_BUS,
347 CLK_CON_DIV_CLKCMU_ITP_BUS,
348 CLK_CON_DIV_CLKCMU_MCSC_BUS,
349 CLK_CON_DIV_CLKCMU_MCSC_GDC,
350 CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
351 CLK_CON_DIV_CLKCMU_MFC0_MFC0,
352 CLK_CON_DIV_CLKCMU_MFC0_WFD,
353 CLK_CON_DIV_CLKCMU_MIF_BUSP,
354 CLK_CON_DIV_CLKCMU_NPU_BUS,
355 CLK_CON_DIV_CLKCMU_OTP,
356 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
357 CLK_CON_DIV_CLKCMU_PERIC0_IP,
358 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
359 CLK_CON_DIV_CLKCMU_PERIC1_IP,
360 CLK_CON_DIV_CLKCMU_PERIS_BUS,
361 CLK_CON_DIV_CLKCMU_SSP_BUS,
362 CLK_CON_DIV_CLKCMU_TNR_BUS,
363 CLK_CON_DIV_CLKCMU_VRA_BUS,
364 CLK_CON_DIV_DIV_CLKCMU_DPU,
365 CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
366 CLK_CON_DIV_PLL_SHARED0_DIV2,
367 CLK_CON_DIV_PLL_SHARED0_DIV3,
368 CLK_CON_DIV_PLL_SHARED0_DIV4,
369 CLK_CON_DIV_PLL_SHARED1_DIV2,
370 CLK_CON_DIV_PLL_SHARED1_DIV3,
371 CLK_CON_DIV_PLL_SHARED1_DIV4,
372 CLK_CON_DIV_PLL_SHARED2_DIV2,
373 CLK_CON_DIV_PLL_SHARED4_DIV2,
374 CLK_CON_DIV_PLL_SHARED4_DIV3,
375 CLK_CON_DIV_PLL_SHARED4_DIV4,
376 CLK_CON_GAT_CLKCMU_G3D_BUS,
377 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
378 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
379 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
380 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
381 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
382 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS,
383 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
384 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
385 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
386 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
387 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
388 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
389 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
390 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
391 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
392 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
393 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP,
394 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
395 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
396 CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
397 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS,
398 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM,
399 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
400 CLK_CON_GAT_GATE_CLKCMU_DPU,
401 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
402 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS,
403 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
404 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
405 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
406 CLK_CON_GAT_GATE_CLKCMU_HPM,
407 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
408 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
409 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
410 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG,
411 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
412 CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
413 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
414 CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD,
415 CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
416 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
417 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
418 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
419 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
420 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS,
421 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC,
422 CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
423 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
424 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
425 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
426 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
427 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
428 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
429 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
430 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
431 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS,
432 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
433 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS,
434 };
435
436 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
437 PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
438 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
439 PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
440 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
441 PLL(pll_0718x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
442 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
443 PLL(pll_0718x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
444 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
445 PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
446 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
447 PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
448 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
449 PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
450 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
451 };
452
453 /* Parent clock list for CMU_TOP muxes */
454 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
455 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
456 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
457 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
458 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
459 PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
460 PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
461 PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
462 "dout_cmu_shared2_div2" };
463 PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
464 "fout_shared2_pll",
465 "dout_cmu_shared4_div2",
466 "dout_cmu_shared0_div4" };
467 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4",
468 "dout_cmu_shared1_div4",
469 "dout_cmu_shared2_div2",
470 "oscclk" };
471 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div4",
472 "dout_cmu_shared1_div4",
473 "dout_cmu_shared2_div2",
474 "oscclk" };
475 PNAME(mout_cmu_bus1_sss_p) = { "dout_cmu_shared0_div4",
476 "dout_cmu_shared1_div4",
477 "dout_cmu_shared2_div2",
478 "oscclk" };
479 PNAME(mout_cmu_cis_clk0_p) = { "oscclk",
480 "dout_cmu_shared2_div2" };
481 PNAME(mout_cmu_cis_clk1_p) = { "oscclk",
482 "dout_cmu_shared2_div2" };
483 PNAME(mout_cmu_cis_clk2_p) = { "oscclk",
484 "dout_cmu_shared2_div2" };
485 PNAME(mout_cmu_cis_clk3_p) = { "oscclk",
486 "dout_cmu_shared2_div2" };
487 PNAME(mout_cmu_cis_clk4_p) = { "oscclk",
488 "dout_cmu_shared2_div2" };
489 PNAME(mout_cmu_cis_clk5_p) = { "oscclk",
490 "dout_cmu_shared2_div2" };
491 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4",
492 "dout_cmu_shared1_div4",
493 "dout_cmu_shared2_div2",
494 "oscclk" };
495 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2",
496 "dout_cmu_shared1_div2",
497 "fout_shared2_pll",
498 "dout_cmu_shared0_div3",
499 "dout_cmu_shared1_div3",
500 "dout_cmu_shared0_div4",
501 "fout_shared3_pll", "oscclk" };
502 PNAME(mout_cmu_cpucl0_dbg_bus_p) = { "fout_shared2_pll",
503 "dout_cmu_shared0_div3",
504 "dout_cmu_shared0_div4",
505 "oscclk" };
506 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
507 "dout_cmu_shared0_div2",
508 "fout_shared2_pll",
509 "dout_cmu_shared0_div4" };
510 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
511 "dout_cmu_shared0_div2",
512 "fout_shared2_pll",
513 "dout_cmu_shared0_div4" };
514 PNAME(mout_cmu_cpucl2_busp_p) = { "dout_cmu_shared0_div4",
515 "dout_cmu_shared2_div2" };
516 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared4_pll",
517 "dout_cmu_shared0_div2",
518 "fout_shared2_pll",
519 "dout_cmu_shared0_div4" };
520 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3",
521 "dout_cmu_shared4_div2",
522 "dout_cmu_shared0_div4",
523 "dout_cmu_shared4_div3" };
524 PNAME(mout_cmu_csis_ois_mcu_p) = { "dout_cmu_shared0_div4",
525 "dout_cmu_shared2_div2" };
526 PNAME(mout_cmu_dnc_bus_p) = { "dout_cmu_shared1_div2",
527 "fout_shared2_pll",
528 "dout_cmu_shared4_div2",
529 "dout_cmu_shared0_div4" };
530 PNAME(mout_cmu_dnc_busm_p) = { "dout_cmu_shared0_div4",
531 "dout_cmu_shared1_div4",
532 "dout_cmu_shared2_div2",
533 "dout_cmu_shared4_div4" };
534 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3",
535 "dout_cmu_shared4_div2",
536 "dout_cmu_shared0_div4",
537 "dout_cmu_shared1_div4",
538 "dout_cmu_shared4_div3",
539 "dout_cmu_shared2_div2",
540 "oscclk", "oscclk" };
541 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3",
542 "dout_cmu_shared0_div4" };
543 PNAME(mout_cmu_dpu_alt_p) = { "dout_cmu_shared4_div2",
544 "dout_cmu_shared4_div3",
545 "dout_cmu_shared2_div2",
546 "oscclk" };
547 PNAME(mout_cmu_dsp_bus_p) = { "dout_cmu_shared0_div2",
548 "dout_cmu_shared1_div2",
549 "fout_shared2_pll",
550 "dout_cmu_shared4_div2",
551 "fout_shared3_pll", "oscclk",
552 "oscclk", "oscclk" };
553 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3",
554 "dout_cmu_shared4_div2",
555 "dout_cmu_shared0_div4",
556 "dout_cmu_shared2_div2" };
557 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4",
558 "dout_cmu_shared2_div2",
559 "dout_cmu_shared4_div4",
560 "oscclk" };
561 PNAME(mout_cmu_hpm_p) = { "oscclk",
562 "dout_cmu_shared0_div4",
563 "dout_cmu_shared2_div2",
564 "oscclk" };
565 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4",
566 "dout_cmu_shared2_div2" };
567 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
568 "dout_cmu_shared2_div2",
569 "oscclk" };
570 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared0_div4",
571 "dout_cmu_shared2_div2",
572 "oscclk" };
573 PNAME(mout_cmu_hsi0_usbdp_debug_p) = { "oscclk", "fout_shared2_pll" };
574 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
575 "dout_cmu_shared0_div4",
576 "dout_cmu_shared1_div4",
577 "dout_cmu_shared4_div3",
578 "dout_cmu_shared2_div2",
579 "fout_mmc_pll", "oscclk", "oscclk" };
580 PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
581 "fout_mmc_pll",
582 "dout_cmu_shared0_div4" };
583 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
584 PNAME(mout_cmu_hsi1_ufs_card_p) = { "oscclk", "dout_cmu_shared0_div4",
585 "dout_cmu_shared2_div2",
586 "oscclk" };
587 PNAME(mout_cmu_hsi1_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
588 "dout_cmu_shared2_div2",
589 "oscclk" };
590 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div3",
591 "dout_cmu_shared2_div2" };
592 PNAME(mout_cmu_hsi2_pcie_p) = { "oscclk", "fout_shared2_pll" };
593 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3",
594 "dout_cmu_shared4_div2",
595 "dout_cmu_shared0_div4",
596 "dout_cmu_shared1_div4",
597 "dout_cmu_shared4_div3",
598 "oscclk", "oscclk", "oscclk" };
599 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3",
600 "dout_cmu_shared4_div2",
601 "dout_cmu_shared0_div4",
602 "dout_cmu_shared1_div4",
603 "dout_cmu_shared4_div3",
604 "dout_cmu_shared2_div2",
605 "oscclk", "oscclk" };
606 PNAME(mout_cmu_mcsc_bus_p) = { "dout_cmu_shared0_div3",
607 "dout_cmu_shared4_div2",
608 "dout_cmu_shared0_div4",
609 "dout_cmu_shared1_div4",
610 "dout_cmu_shared4_div3",
611 "dout_cmu_shared2_div2",
612 "oscclk", "oscclk" };
613 PNAME(mout_cmu_mcsc_gdc_p) = { "dout_cmu_shared0_div3",
614 "dout_cmu_shared4_div2",
615 "dout_cmu_shared0_div4",
616 "dout_cmu_shared1_div4",
617 "dout_cmu_shared4_div3",
618 "dout_cmu_shared2_div2",
619 "oscclk", "oscclk" };
620 PNAME(mout_cmu_cmu_boost_cpu_p) = { "dout_cmu_shared0_div4",
621 "dout_cmu_shared1_div4",
622 "dout_cmu_shared2_div2",
623 "oscclk" };
624 PNAME(mout_cmu_mfc0_mfc0_p) = { "dout_cmu_shared4_div2",
625 "dout_cmu_shared0_div4",
626 "dout_cmu_shared4_div3",
627 "dout_cmu_shared2_div2" };
628 PNAME(mout_cmu_mfc0_wfd_p) = { "dout_cmu_shared4_div2",
629 "dout_cmu_shared0_div4",
630 "dout_cmu_shared4_div3",
631 "dout_cmu_shared2_div2" };
632 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4",
633 "dout_cmu_shared1_div4",
634 "dout_cmu_shared2_div2",
635 "oscclk" };
636 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll",
637 "fout_shared1_pll",
638 "dout_cmu_shared0_div2",
639 "dout_cmu_shared1_div2",
640 "fout_shared2_pll",
641 "dout_cmu_shared0_div4",
642 "dout_cmu_shared2_div2",
643 "oscclk" };
644 PNAME(mout_cmu_npu_bus_p) = { "dout_cmu_shared0_div2",
645 "dout_cmu_shared1_div2",
646 "fout_shared2_pll",
647 "dout_cmu_shared4_div2",
648 "fout_shared3_pll", "oscclk",
649 "oscclk", "oscclk" };
650 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
651 "dout_cmu_shared2_div2" };
652 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4",
653 "dout_cmu_shared2_div2" };
654 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
655 "dout_cmu_shared2_div2" };
656 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4",
657 "dout_cmu_shared2_div2" };
658 PNAME(mout_cmu_peris_bus_p) = { "dout_cmu_shared0_div4",
659 "dout_cmu_shared2_div2" };
660 PNAME(mout_cmu_ssp_bus_p) = { "dout_cmu_shared4_div2",
661 "dout_cmu_shared0_div4",
662 "dout_cmu_shared4_div3",
663 "dout_cmu_shared2_div2" };
664 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3",
665 "dout_cmu_shared4_div2",
666 "dout_cmu_shared0_div4",
667 "dout_cmu_shared1_div4",
668 "dout_cmu_shared4_div3",
669 "dout_cmu_shared2_div2",
670 "oscclk", "oscclk" };
671 PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
672 "dout_cmu_shared4_div2",
673 "dout_cmu_shared0_div4",
674 "dout_cmu_shared4_div3" };
675
676 /*
677 * Register name to clock name mangling strategy used in this file
678 *
679 * Replace PLL_CON{0,3}_PLL with CLK_MOUT_PLL and mout_pll
680 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
681 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
682 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
683 * Replace CLK_CON_DIV_PLL_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
684 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
685 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
686 *
687 * For gates remove _UID _BLK _IPCLKPORT, _I and _RSTNSYNC
688 */
689
690 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
691 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
692 PLL_CON3_PLL_SHARED0, 4, 1),
693 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
694 PLL_CON3_PLL_SHARED1, 4, 1),
695 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
696 PLL_CON3_PLL_SHARED2, 4, 1),
697 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
698 PLL_CON3_PLL_SHARED3, 4, 1),
699 MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
700 PLL_CON0_PLL_SHARED4, 4, 1),
701 MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
702 PLL_CON0_PLL_MMC, 4, 1),
703 MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
704 PLL_CON0_PLL_G3D, 4, 1),
705 MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
706 mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
707 MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
708 mout_cmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 2),
709 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus",
710 mout_cmu_bus0_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
711 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus",
712 mout_cmu_bus1_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
713 MUX(CLK_MOUT_CMU_BUS1_SSS, "mout_cmu_bus1_sss",
714 mout_cmu_bus1_sss_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS, 0, 2),
715 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0",
716 mout_cmu_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
717 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1",
718 mout_cmu_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
719 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2",
720 mout_cmu_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
721 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3",
722 mout_cmu_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
723 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4",
724 mout_cmu_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1),
725 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5",
726 mout_cmu_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1),
727 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost",
728 mout_cmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
729 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus",
730 mout_cmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
731 MUX(CLK_MOUT_CMU_CPUCL0_DBG_BUS, "mout_cmu_cpucl0_dbg_bus",
732 mout_cmu_cpucl0_dbg_bus_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
733 0, 2),
734 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
735 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
736 0, 2),
737 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
738 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
739 0, 2),
740 MUX(CLK_MOUT_CMU_CPUCL2_BUSP, "mout_cmu_cpucl2_busp",
741 mout_cmu_cpucl2_busp_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP,
742 0, 1),
743 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
744 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
745 0, 2),
746 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus",
747 mout_cmu_csis_bus_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
748 MUX(CLK_MOUT_CMU_CSIS_OIS_MCU, "mout_cmu_csis_ois_mcu",
749 mout_cmu_csis_ois_mcu_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
750 0, 1),
751 MUX(CLK_MOUT_CMU_DNC_BUS, "mout_cmu_dnc_bus",
752 mout_cmu_dnc_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUS, 0, 2),
753 MUX(CLK_MOUT_CMU_DNC_BUSM, "mout_cmu_dnc_busm",
754 mout_cmu_dnc_busm_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM, 0, 2),
755 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus",
756 mout_cmu_dns_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
757 MUX(CLK_MOUT_CMU_DPU, "mout_cmu_dpu",
758 mout_cmu_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 1),
759 MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt",
760 mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
761 MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus",
762 mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
763 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d",
764 mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
765 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl",
766 mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1),
767 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm",
768 mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
769 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus",
770 mout_cmu_hsi0_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 1),
771 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",
772 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
773 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",
774 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
775 0, 2),
776 MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug",
777 mout_cmu_hsi0_usbdp_debug_p,
778 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2),
779 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus",
780 mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
781 MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card",
782 mout_cmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
783 0, 2),
784 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie",
785 mout_cmu_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
786 MUX(CLK_MOUT_CMU_HSI1_UFS_CARD, "mout_cmu_hsi1_ufs_card",
787 mout_cmu_hsi1_ufs_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD,
788 0, 2),
789 MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd",
790 mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
791 0, 1),
792 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus",
793 mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
794 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie",
795 mout_cmu_hsi2_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
796 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus",
797 mout_cmu_ipp_bus_p, CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
798 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus",
799 mout_cmu_itp_bus_p, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
800 MUX(CLK_MOUT_CMU_MCSC_BUS, "mout_cmu_mcsc_bus",
801 mout_cmu_mcsc_bus_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, 0, 3),
802 MUX(CLK_MOUT_CMU_MCSC_GDC, "mout_cmu_mcsc_gdc",
803 mout_cmu_mcsc_gdc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, 0, 3),
804 MUX(CLK_MOUT_CMU_CMU_BOOST_CPU, "mout_cmu_cmu_boost_cpu",
805 mout_cmu_cmu_boost_cpu_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
806 0, 2),
807 MUX(CLK_MOUT_CMU_MFC0_MFC0, "mout_cmu_mfc0_mfc0",
808 mout_cmu_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 2),
809 MUX(CLK_MOUT_CMU_MFC0_WFD, "mout_cmu_mfc0_wfd",
810 mout_cmu_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 2),
811 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp",
812 mout_cmu_mif_busp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
813 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
814 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
815 MUX(CLK_MOUT_CMU_NPU_BUS, "mout_cmu_npu_bus",
816 mout_cmu_npu_bus_p, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
817 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
818 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
819 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip",
820 mout_cmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
821 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
822 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
823 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip",
824 mout_cmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
825 MUX(CLK_MOUT_CMU_PERIS_BUS, "mout_cmu_peris_bus",
826 mout_cmu_peris_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
827 MUX(CLK_MOUT_CMU_SSP_BUS, "mout_cmu_ssp_bus",
828 mout_cmu_ssp_bus_p, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, 0, 2),
829 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus",
830 mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
831 MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
832 mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
833 };
834
835 static const struct samsung_div_clock top_div_clks[] __initconst = {
836 /* SHARED0 region*/
837 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
838 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
839 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
840 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
841 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
842 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
843
844 /* SHARED1 region*/
845 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
846 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
847 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
848 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
849 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
850 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
851
852 /* SHARED2 region */
853 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
854 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
855
856 /* SHARED4 region*/
857 DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
858 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
859 DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
860 CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
861 DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
862 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
863
864 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
865 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
866 DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
867 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
868 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
869 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
870 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
871 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
872 DIV(CLK_DOUT_CMU_BUS1_SSS, "dout_cmu_bus1_sss", "gout_cmu_bus1_sss",
873 CLK_CON_DIV_CLKCMU_BUS1_SSS, 0, 4),
874 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
875 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
876 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
877 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
878 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
879 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
880 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
881 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
882 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",
883 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
884 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",
885 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
886 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "mout_cmu_cmu_boost",
887 CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
888 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
889 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
890 DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug",
891 "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
892 0, 3),
893 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
894 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
895 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
896 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
897 DIV(CLK_DOUT_CMU_CPUCL2_BUSP, "dout_cmu_cpucl2_busp",
898 "gout_cmu_cpucl2_busp", CLK_CON_DIV_CLKCMU_CPUCL2_BUSP, 0, 4),
899 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
900 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
901 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
902 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
903 DIV(CLK_DOUT_CMU_CSIS_OIS_MCU, "dout_cmu_csis_ois_mcu",
904 "gout_cmu_csis_ois_mcu", CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, 0, 4),
905 DIV(CLK_DOUT_CMU_DNC_BUS, "dout_cmu_dnc_bus", "gout_cmu_dnc_bus",
906 CLK_CON_DIV_CLKCMU_DNC_BUS, 0, 4),
907 DIV(CLK_DOUT_CMU_DNC_BUSM, "dout_cmu_dnc_busm", "gout_cmu_dnc_busm",
908 CLK_CON_DIV_CLKCMU_DNC_BUSM, 0, 4),
909 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
910 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
911 DIV(CLK_DOUT_CMU_DSP_BUS, "dout_cmu_dsp_bus", "gout_cmu_dsp_bus",
912 CLK_CON_DIV_CLKCMU_DSP_BUS, 0, 4),
913 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
914 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
915 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
916 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
917 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
918 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
919 DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
920 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
921 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
922 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
923 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
924 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
925 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
926 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
927 DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
928 "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
929 0, 4),
930 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
931 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
932 DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card",
933 "gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
934 0, 9),
935 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
936 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7),
937 DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card",
938 "gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
939 0, 3),
940 DIV(CLK_DOUT_CMU_HSI1_UFS_EMBD, "dout_cmu_hsi1_ufs_embd",
941 "gout_cmu_hsi1_ufs_embd", CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
942 0, 3),
943 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
944 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
945 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
946 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7),
947 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
948 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
949 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
950 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
951 DIV(CLK_DOUT_CMU_MCSC_BUS, "dout_cmu_mcsc_bus", "gout_cmu_mcsc_bus",
952 CLK_CON_DIV_CLKCMU_MCSC_BUS, 0, 4),
953 DIV(CLK_DOUT_CMU_MCSC_GDC, "dout_cmu_mcsc_gdc", "gout_cmu_mcsc_gdc",
954 CLK_CON_DIV_CLKCMU_MCSC_GDC, 0, 4),
955 DIV(CLK_DOUT_CMU_CMU_BOOST_CPU, "dout_cmu_cmu_boost_cpu",
956 "mout_cmu_cmu_boost_cpu", CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
957 0, 2),
958 DIV(CLK_DOUT_CMU_MFC0_MFC0, "dout_cmu_mfc0_mfc0", "gout_cmu_mfc0_mfc0",
959 CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0, 4),
960 DIV(CLK_DOUT_CMU_MFC0_WFD, "dout_cmu_mfc0_wfd", "gout_cmu_mfc0_wfd",
961 CLK_CON_DIV_CLKCMU_MFC0_WFD, 0, 4),
962 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
963 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
964 DIV(CLK_DOUT_CMU_NPU_BUS, "dout_cmu_npu_bus", "gout_cmu_npu_bus",
965 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
966 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
967 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
968 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
969 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
970 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
971 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
972 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
973 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
974 DIV(CLK_DOUT_CMU_PERIS_BUS, "dout_cmu_peris_bus", "gout_cmu_peris_bus",
975 CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
976 DIV(CLK_DOUT_CMU_SSP_BUS, "dout_cmu_ssp_bus", "gout_cmu_ssp_bus",
977 CLK_CON_DIV_CLKCMU_SSP_BUS, 0, 4),
978 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
979 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
980 DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
981 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
982 DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu",
983 CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4),
984 };
985
986 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
987 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
988 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
989 GATE(CLK_GOUT_CMU_AUD_CPU, "gout_cmu_aud_cpu", "mout_cmu_aud_cpu",
990 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
991 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
992 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, CLK_IGNORE_UNUSED, 0),
993 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
994 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, CLK_IGNORE_UNUSED, 0),
995 GATE(CLK_GOUT_CMU_BUS1_SSS, "gout_cmu_bus1_sss", "mout_cmu_bus1_sss",
996 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS, 21, CLK_IGNORE_UNUSED, 0),
997 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
998 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
999 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1000 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1001 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1002 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1003 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1004 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1005 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1006 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1007 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1008 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1009 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1010 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IGNORE_UNUSED, 0),
1011 GATE(CLK_GOUT_CMU_CPUCL0_DBG_BUS, "gout_cmu_cpucl0_dbg_bus",
1012 "mout_cmu_cpucl0_dbg_bus", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1013 21, 0, 0),
1014 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1015 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1016 21, CLK_IGNORE_UNUSED, 0),
1017 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1018 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1019 21, CLK_IGNORE_UNUSED, 0),
1020 GATE(CLK_GOUT_CMU_CPUCL2_BUSP, "gout_cmu_cpucl2_busp",
1021 "mout_cmu_cpucl2_busp", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP,
1022 21, CLK_IGNORE_UNUSED, 0),
1023 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1024 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
1025 21, CLK_IGNORE_UNUSED, 0),
1026 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1027 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1028 GATE(CLK_GOUT_CMU_CSIS_OIS_MCU, "gout_cmu_csis_ois_mcu",
1029 "mout_cmu_csis_ois_mcu", CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
1030 21, 0, 0),
1031 GATE(CLK_GOUT_CMU_DNC_BUS, "gout_cmu_dnc_bus", "mout_cmu_dnc_bus",
1032 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS, 21, 0, 0),
1033 GATE(CLK_GOUT_CMU_DNC_BUSM, "gout_cmu_dnc_busm", "mout_cmu_dnc_busm",
1034 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM, 21, 0, 0),
1035 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1036 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1037 GATE(CLK_GOUT_CMU_DPU, "gout_cmu_dpu", "mout_cmu_dpu",
1038 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
1039 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_alt",
1040 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, CLK_IGNORE_UNUSED, 0),
1041 GATE(CLK_GOUT_CMU_DSP_BUS, "gout_cmu_dsp_bus", "mout_cmu_dsp_bus",
1042 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 21, 0, 0),
1043 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1044 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1045 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1046 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1047 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1048 "fout_shared2_pll", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1049 21, 0, 0),
1050 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1051 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1052 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus",
1053 "mout_cmu_hsi0_bus", CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1054 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1055 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1056 21, 0, 0),
1057 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1058 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
1059 21, 0, 0),
1060 GATE(CLK_GOUT_CMU_HSI0_USBDP_DEBUG, "gout_cmu_hsi0_usbdp_debug",
1061 "mout_cmu_hsi0_usbdp_debug", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG,
1062 21, 0, 0),
1063 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1064 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1065 GATE(CLK_GOUT_CMU_HSI1_MMC_CARD, "gout_cmu_hsi1_mmc_card",
1066 "mout_cmu_hsi1_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
1067 21, 0, 0),
1068 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie",
1069 "mout_cmu_hsi1_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
1070 21, 0, 0),
1071 GATE(CLK_GOUT_CMU_HSI1_UFS_CARD, "gout_cmu_hsi1_ufs_card",
1072 "mout_cmu_hsi1_ufs_card", CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD,
1073 21, 0, 0),
1074 GATE(CLK_GOUT_CMU_HSI1_UFS_EMBD, "gout_cmu_hsi1_ufs_embd",
1075 "mout_cmu_hsi1_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
1076 21, 0, 0),
1077 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1078 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1079 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie",
1080 "mout_cmu_hsi2_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
1081 21, 0, 0),
1082 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1083 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1084 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1085 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1086 GATE(CLK_GOUT_CMU_MCSC_BUS, "gout_cmu_mcsc_bus", "mout_cmu_mcsc_bus",
1087 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, 21, 0, 0),
1088 GATE(CLK_GOUT_CMU_MCSC_GDC, "gout_cmu_mcsc_gdc", "mout_cmu_mcsc_gdc",
1089 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, 21, 0, 0),
1090 GATE(CLK_GOUT_CMU_MFC0_MFC0, "gout_cmu_mfc0_mfc0",
1091 "mout_cmu_mfc0_mfc0", CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
1092 21, 0, 0),
1093 GATE(CLK_GOUT_CMU_MFC0_WFD, "gout_cmu_mfc0_wfd", "mout_cmu_mfc0_wfd",
1094 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, 21, 0, 0),
1095 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1096 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1097 GATE(CLK_GOUT_CMU_NPU_BUS, "gout_cmu_npu_bus", "mout_cmu_npu_bus",
1098 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
1099 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1100 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1101 21, 0, 0),
1102 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip",
1103 "mout_cmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
1104 21, 0, 0),
1105 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1106 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1107 21, 0, 0),
1108 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip",
1109 "mout_cmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
1110 21, 0, 0),
1111 GATE(CLK_GOUT_CMU_PERIS_BUS, "gout_cmu_peris_bus",
1112 "mout_cmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
1113 21, CLK_IGNORE_UNUSED, 0),
1114 GATE(CLK_GOUT_CMU_SSP_BUS, "gout_cmu_ssp_bus", "mout_cmu_ssp_bus",
1115 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS, 21, 0, 0),
1116 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1117 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1118 GATE(CLK_GOUT_CMU_VRA_BUS, "gout_cmu_vra_bus", "mout_cmu_vra_bus",
1119 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS, 21, 0, 0),
1120 };
1121
1122 static const struct samsung_cmu_info top_cmu_info __initconst = {
1123 .pll_clks = top_pll_clks,
1124 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1125 .mux_clks = top_mux_clks,
1126 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1127 .div_clks = top_div_clks,
1128 .nr_div_clks = ARRAY_SIZE(top_div_clks),
1129 .gate_clks = top_gate_clks,
1130 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1131 .nr_clk_ids = CLKS_NR_TOP,
1132 .clk_regs = top_clk_regs,
1133 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1134 };
1135
exynos990_cmu_top_init(struct device_node * np)1136 static void __init exynos990_cmu_top_init(struct device_node *np)
1137 {
1138 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1139 }
1140
1141 /* Register CMU_TOP early, as it's a dependency for other early domains */
1142 CLK_OF_DECLARE(exynos990_cmu_top, "samsung,exynos990-cmu-top",
1143 exynos990_cmu_top_init);
1144
1145 /* ---- CMU_HSI0 ------------------------------------------------------------ */
1146
1147 /* Register Offset definitions for CMU_HSI0 (0x10a00000) */
1148 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0600
1149 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0620
1150 #define PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER 0x0630
1151 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0610
1152 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x2004
1153 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK 0x2018
1154 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2014
1155 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2020
1156 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK 0x2044
1157 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2008
1158 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x200c
1159 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x2010
1160 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK 0x201c
1161 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2024
1162 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2028
1163 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x202c
1164 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2034
1165 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x203c
1166 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2040
1167 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2030
1168 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1169 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK 0x2048
1170 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x2038
1171
1172 static const unsigned long hsi0_clk_regs[] __initconst = {
1173 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
1174 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
1175 PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
1176 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
1177 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
1178 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1179 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
1180 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
1181 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
1182 CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
1183 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
1184 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
1185 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
1186 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1187 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1188 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1189 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1190 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1191 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
1192 CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
1193 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1194 };
1195
1196 /* Parent clock list for CMU_HSI0 muxes */
1197 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
1198 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", "dout_cmu_hsi0_usb31drd" };
1199 PNAME(mout_hsi0_usbdp_debug_user_p) = { "oscclk",
1200 "dout_cmu_hsi0_usbdp_debug" };
1201 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
1202
1203 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1204 MUX(CLK_MOUT_HSI0_BUS_USER, "mout_hsi0_bus_user",
1205 mout_hsi0_bus_user_p, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
1206 4, 1),
1207 MUX(CLK_MOUT_HSI0_USB31DRD_USER, "mout_hsi0_usb31drd_user",
1208 mout_hsi0_usb31drd_user_p, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
1209 4, 1),
1210 MUX(CLK_MOUT_HSI0_USBDP_DEBUG_USER, "mout_hsi0_usbdp_debug_user",
1211 mout_hsi0_usbdp_debug_user_p,
1212 PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
1213 4, 1),
1214 MUX(CLK_MOUT_HSI0_DPGTC_USER, "mout_hsi0_dpgtc_user",
1215 mout_hsi0_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
1216 4, 1),
1217 };
1218
1219 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
1220 GATE(CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK,
1221 "gout_hsi0_dp_link_dp_gtc_clk", "mout_hsi0_dpgtc_user",
1222 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
1223 21, 0, 0),
1224 GATE(CLK_GOUT_HSI0_DP_LINK_PCLK,
1225 "gout_hsi0_dp_link_pclk", "mout_hsi0_bus_user",
1226 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1227 21, 0, 0),
1228 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
1229 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus_user",
1230 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
1231 21, 0, 0),
1232 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK,
1233 "gout_hsi0_lhm_axi_p_hsi0_clk", "mout_hsi0_bus_user",
1234 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
1235 21, CLK_IS_CRITICAL, 0),
1236 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK,
1237 "gout_hsi0_ppmu_hsi0_bus1_aclk", "mout_hsi0_bus_user",
1238 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
1239 21, 0, 0),
1240 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK,
1241 "gout_hsi0_ppmu_hsi0_bus1_pclk", "mout_hsi0_bus_user",
1242 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
1243 21, 0, 0),
1244 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
1245 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus_user",
1246 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
1247 21, 0, 0),
1248 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
1249 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus_user",
1250 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1251 21, CLK_IGNORE_UNUSED, 0),
1252 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
1253 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus_user",
1254 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1255 21, 0, 0),
1256 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
1257 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus_user",
1258 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1259 21, 0, 0),
1260 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
1261 "gout_hsi0_usb31drd_bus_clk_early",
1262 "mout_hsi0_bus_user",
1263 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
1264 21, 0, 0),
1265 GATE(CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40,
1266 "gout_hsi0_usb31drd_usb31drd_ref_clk_40",
1267 "mout_hsi0_usb31drd_user",
1268 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
1269 21, 0, 0),
1270 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL,
1271 "gout_hsi0_usb31drd_usbdpphy_ref_soc_pll",
1272 "mout_hsi0_usbdp_debug_user",
1273 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
1274 21, 0, 0),
1275 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB,
1276 "gout_hsi0_usb31drd_ipclkport_i_usbdpphy_scl_apb_pclk",
1277 "mout_hsi0_bus_user",
1278 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1279 21, 0, 0),
1280 GATE(CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK,
1281 "gout_hsi0_usb31drd_usbpcs_apb_clk",
1282 "mout_hsi0_bus_user",
1283 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1284 21, 0, 0),
1285 GATE(CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK,
1286 "gout_hsi0_vgen_lite_ipclkport_clk", "mout_hsi0_bus_user",
1287 CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
1288 21, 0, 0),
1289 GATE(CLK_GOUT_HSI0_CMU_HSI0_PCLK,
1290 "gout_hsi0_cmu_hsi0_pclk", "mout_hsi0_bus_user",
1291 CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
1292 21, CLK_IGNORE_UNUSED, 0),
1293 GATE(CLK_GOUT_HSI0_XIU_D_HSI0_ACLK,
1294 "gout_hsi0_xiu_d_hsi0_aclk", "mout_hsi0_bus_user",
1295 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1296 21, CLK_IGNORE_UNUSED, 0),
1297 };
1298
1299 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1300 .mux_clks = hsi0_mux_clks,
1301 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1302 .gate_clks = hsi0_gate_clks,
1303 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
1304 .nr_clk_ids = CLKS_NR_HSI0,
1305 .clk_regs = hsi0_clk_regs,
1306 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1307 .clk_name = "bus",
1308 };
1309
1310 /* ---- CMU_PERIS ----------------------------------------------------------- */
1311
1312 /* Register Offset definitions for CMU_PERIS (0x10020000) */
1313 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
1314 #define PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER 0x0604
1315 #define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
1316 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x203c
1317 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK 0x204c
1318 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2048
1319 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x200c
1320 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x2034
1321 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK 0x2010
1322 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2038
1323 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2014
1324 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2028
1325 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x201c
1326 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2020
1327 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x2024
1328 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2030
1329 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x2018
1330 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2040
1331 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2044
1332 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2000
1333 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
1334 #define QCH_CON_D_TZPC_PERIS_QCH 0x3004
1335 #define QCH_CON_GIC_QCH 0x3008
1336 #define QCH_CON_LHM_AXI_P_PERIS_QCH 0x300c
1337 #define QCH_CON_MCT_QCH 0x3010
1338 #define QCH_CON_OTP_CON_BIRA_QCH 0x3014
1339 #define QCH_CON_OTP_CON_TOP_QCH 0x301c
1340 #define QCH_CON_PERIS_CMU_PERIS_QCH 0x3020
1341 #define QCH_CON_SYSREG_PERIS_QCH 0x3024
1342 #define QCH_CON_TMU_SUB_QCH 0x3028
1343 #define QCH_CON_TMU_TOP_QCH 0x302c
1344 #define QCH_CON_WDT_CLUSTER0_QCH 0x3030
1345 #define QCH_CON_WDT_CLUSTER2_QCH 0x3034
1346
1347 static const unsigned long peris_clk_regs[] __initconst = {
1348 PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1349 PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER,
1350 CLK_CON_MUX_MUX_CLK_PERIS_GIC,
1351 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1352 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
1353 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1354 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
1355 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
1356 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
1357 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
1358 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
1359 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
1360 CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
1361 CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
1362 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
1363 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1364 CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
1365 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
1366 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
1367 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
1368 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
1369 QCH_CON_D_TZPC_PERIS_QCH,
1370 QCH_CON_GIC_QCH,
1371 QCH_CON_LHM_AXI_P_PERIS_QCH,
1372 QCH_CON_MCT_QCH,
1373 QCH_CON_OTP_CON_BIRA_QCH,
1374 QCH_CON_OTP_CON_TOP_QCH,
1375 QCH_CON_PERIS_CMU_PERIS_QCH,
1376 QCH_CON_SYSREG_PERIS_QCH,
1377 QCH_CON_TMU_SUB_QCH,
1378 QCH_CON_TMU_TOP_QCH,
1379 QCH_CON_WDT_CLUSTER0_QCH,
1380 QCH_CON_WDT_CLUSTER2_QCH,
1381 };
1382
1383 /* Parent clock list for CMU_PERIS muxes */
1384 PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" };
1385 PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" };
1386
1387 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
1388 MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
1389 mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1390 4, 1),
1391 MUX(CLK_MOUT_PERIS_CLK_PERIS_GIC, "mout_peris_clk_peris_gic",
1392 mout_peris_clk_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC,
1393 4, 1),
1394 };
1395
1396 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1397 GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK,
1398 "gout_peris_sysreg_peris_pclk", "mout_peris_bus_user",
1399 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1400 21, 0, 0),
1401 GATE(CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK,
1402 "gout_peris_wdt_cluster2_pclk", "mout_peris_bus_user",
1403 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
1404 21, 0, 0),
1405 GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK,
1406 "gout_peris_wdt_cluster0_pclk", "mout_peris_bus_user",
1407 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1408 21, 0, 0),
1409 GATE(CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK,
1410 "clk_peris_peris_cmu_peris_pclk", "mout_peris_bus_user",
1411 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
1412 21, CLK_IGNORE_UNUSED, 0),
1413 GATE(CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK,
1414 "gout_peris_clk_peris_busp_clk", "mout_peris_bus_user",
1415 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
1416 21, 0, 0),
1417 GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK,
1418 "gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user",
1419 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
1420 21, 0, 0),
1421 GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK,
1422 "gout_peris_clk_peris_gic_clk", "mout_peris_bus_user",
1423 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
1424 21, 0, 0),
1425 GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
1426 "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user",
1427 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
1428 21, CLK_IGNORE_UNUSED, 0),
1429 GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK,
1430 "gout_peris_otp_con_bira_pclk", "mout_peris_bus_user",
1431 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
1432 21, 0, 0),
1433 GATE(CLK_GOUT_PERIS_GIC_CLK,
1434 "gout_peris_gic_clk", "mout_peris_bus_user",
1435 CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
1436 21, CLK_IS_CRITICAL, 0),
1437 GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK,
1438 "gout_peris_lhm_axi_p_peris_clk", "oscclk",
1439 CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
1440 21, CLK_IGNORE_UNUSED, 0),
1441 GATE(CLK_GOUT_PERIS_MCT_PCLK,
1442 "gout_peris_mct_pclk", "mout_peris_clk_peris_gic",
1443 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
1444 21, 0, 0),
1445 GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK,
1446 "gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic",
1447 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1448 21, 0, 0),
1449 GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK,
1450 "gout_peris_d_tzpc_peris_pclk", "mout_peris_bus_user",
1451 CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
1452 21, 0, 0),
1453 GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK,
1454 "gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic",
1455 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
1456 21, 0, 0),
1457 GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK,
1458 "gout_peris_otp_con_bira_oscclk", "oscclk",
1459 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
1460 21, 0, 0),
1461 GATE(CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK,
1462 "gout_peris_otp_con_top_oscclk", "oscclk",
1463 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
1464 21, 0, 0),
1465 };
1466
1467 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1468 .mux_clks = peris_mux_clks,
1469 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
1470 .gate_clks = peris_gate_clks,
1471 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1472 .nr_clk_ids = CLKS_NR_PERIS,
1473 .clk_regs = peris_clk_regs,
1474 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1475 };
1476
exynos990_cmu_peris_init(struct device_node * np)1477 static void __init exynos990_cmu_peris_init(struct device_node *np)
1478 {
1479 exynos_arm64_register_cmu(NULL, np, &peris_cmu_info);
1480 }
1481
1482 /* Register CMU_PERIS early, as it's a dependency for the MCT. */
1483 CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris",
1484 exynos990_cmu_peris_init);
1485
1486 /* ----- platform_driver ----- */
1487
exynos990_cmu_probe(struct platform_device * pdev)1488 static int __init exynos990_cmu_probe(struct platform_device *pdev)
1489 {
1490 const struct samsung_cmu_info *info;
1491 struct device *dev = &pdev->dev;
1492
1493 info = of_device_get_match_data(dev);
1494 exynos_arm64_register_cmu(dev, dev->of_node, info);
1495
1496 return 0;
1497 }
1498
1499 static const struct of_device_id exynos990_cmu_of_match[] = {
1500 {
1501 .compatible = "samsung,exynos990-cmu-hsi0",
1502 .data = &hsi0_cmu_info,
1503 },
1504 { },
1505 };
1506
1507 static struct platform_driver exynos990_cmu_driver __refdata = {
1508 .driver = {
1509 .name = "exynos990-cmu",
1510 .of_match_table = exynos990_cmu_of_match,
1511 .suppress_bind_attrs = true,
1512 },
1513 .probe = exynos990_cmu_probe,
1514 };
1515
exynos990_cmu_init(void)1516 static int __init exynos990_cmu_init(void)
1517 {
1518 return platform_driver_register(&exynos990_cmu_driver);
1519 }
1520
1521 core_initcall(exynos990_cmu_init);
1522