1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Samsung Electronics Co., Ltd.
4 * Author: Kaustabh Chakraborty <kauschluss@disroot.org>
5 *
6 * Common Clock Framework support for Exynos7870.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynos7870-cmu.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /*
20 * Register offsets for CMU_MIF (0x10460000)
21 */
22 #define PLL_LOCKTIME_MIF_MEM_PLL 0x0000
23 #define PLL_LOCKTIME_MIF_MEDIA_PLL 0x0020
24 #define PLL_LOCKTIME_MIF_BUS_PLL 0x0040
25 #define PLL_CON0_MIF_MEM_PLL 0x0100
26 #define PLL_CON0_MIF_MEDIA_PLL 0x0120
27 #define PLL_CON0_MIF_BUS_PLL 0x0140
28 #define CLK_CON_GAT_MIF_MUX_MEM_PLL 0x0200
29 #define CLK_CON_GAT_MIF_MUX_MEM_PLL_CON 0x0200
30 #define CLK_CON_GAT_MIF_MUX_MEDIA_PLL 0x0204
31 #define CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON 0x0204
32 #define CLK_CON_GAT_MIF_MUX_BUS_PLL 0x0208
33 #define CLK_CON_GAT_MIF_MUX_BUS_PLL_CON 0x0208
34 #define CLK_CON_GAT_MIF_MUX_BUSD 0x0220
35 #define CLK_CON_MUX_MIF_BUSD 0x0220
36 #define CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA 0x0264
37 #define CLK_CON_MUX_MIF_CMU_ISP_VRA 0x0264
38 #define CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM 0x0268
39 #define CLK_CON_MUX_MIF_CMU_ISP_CAM 0x0268
40 #define CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP 0x026c
41 #define CLK_CON_MUX_MIF_CMU_ISP_ISP 0x026c
42 #define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS 0x0270
43 #define CLK_CON_MUX_MIF_CMU_DISPAUD_BUS 0x0270
44 #define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 0x0274
45 #define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK 0x0274
46 #define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 0x0278
47 #define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK 0x0278
48 #define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL 0x027c
49 #define CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL 0x027c
50 #define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC 0x0280
51 #define CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC 0x0280
52 #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS 0x0284
53 #define CLK_CON_MUX_MIF_CMU_FSYS_BUS 0x0284
54 #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0 0x0288
55 #define CLK_CON_MUX_MIF_CMU_FSYS_MMC0 0x0288
56 #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1 0x028c
57 #define CLK_CON_MUX_MIF_CMU_FSYS_MMC1 0x028c
58 #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2 0x0290
59 #define CLK_CON_MUX_MIF_CMU_FSYS_MMC2 0x0290
60 #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 0x029c
61 #define CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK 0x029c
62 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS 0x02a0
63 #define CLK_CON_MUX_MIF_CMU_PERI_BUS 0x02a0
64 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1 0x02a4
65 #define CLK_CON_MUX_MIF_CMU_PERI_UART1 0x02a4
66 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2 0x02a8
67 #define CLK_CON_MUX_MIF_CMU_PERI_UART2 0x02a8
68 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0 0x02ac
69 #define CLK_CON_MUX_MIF_CMU_PERI_UART0 0x02ac
70 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2 0x02b0
71 #define CLK_CON_MUX_MIF_CMU_PERI_SPI2 0x02b0
72 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1 0x02b4
73 #define CLK_CON_MUX_MIF_CMU_PERI_SPI1 0x02b4
74 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0 0x02b8
75 #define CLK_CON_MUX_MIF_CMU_PERI_SPI0 0x02b8
76 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3 0x02bc
77 #define CLK_CON_MUX_MIF_CMU_PERI_SPI3 0x02bc
78 #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4 0x02c0
79 #define CLK_CON_MUX_MIF_CMU_PERI_SPI4 0x02c0
80 #define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0 0x02c4
81 #define CLK_CON_MUX_MIF_CMU_ISP_SENSOR0 0x02c4
82 #define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1 0x02c8
83 #define CLK_CON_MUX_MIF_CMU_ISP_SENSOR1 0x02c8
84 #define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2 0x02cc
85 #define CLK_CON_MUX_MIF_CMU_ISP_SENSOR2 0x02cc
86 #define CLK_CON_DIV_MIF_BUSD 0x0420
87 #define CLK_CON_DIV_MIF_APB 0x0424
88 #define CLK_CON_DIV_MIF_HSI2C 0x0430
89 #define CLK_CON_DIV_MIF_CMU_G3D_SWITCH 0x0460
90 #define CLK_CON_DIV_MIF_CMU_ISP_VRA 0x0464
91 #define CLK_CON_DIV_MIF_CMU_ISP_CAM 0x0468
92 #define CLK_CON_DIV_MIF_CMU_ISP_ISP 0x046c
93 #define CLK_CON_DIV_MIF_CMU_DISPAUD_BUS 0x0470
94 #define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK 0x0474
95 #define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK 0x0478
96 #define CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL 0x047c
97 #define CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC 0x0480
98 #define CLK_CON_DIV_MIF_CMU_FSYS_BUS 0x0484
99 #define CLK_CON_DIV_MIF_CMU_FSYS_MMC0 0x0488
100 #define CLK_CON_DIV_MIF_CMU_FSYS_MMC1 0x048c
101 #define CLK_CON_DIV_MIF_CMU_FSYS_MMC2 0x0490
102 #define CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK 0x049c
103 #define CLK_CON_DIV_MIF_CMU_PERI_BUS 0x04a0
104 #define CLK_CON_DIV_MIF_CMU_PERI_UART1 0x04a4
105 #define CLK_CON_DIV_MIF_CMU_PERI_UART2 0x04a8
106 #define CLK_CON_DIV_MIF_CMU_PERI_UART0 0x04ac
107 #define CLK_CON_DIV_MIF_CMU_PERI_SPI2 0x04b0
108 #define CLK_CON_DIV_MIF_CMU_PERI_SPI1 0x04b4
109 #define CLK_CON_DIV_MIF_CMU_PERI_SPI0 0x04b8
110 #define CLK_CON_DIV_MIF_CMU_PERI_SPI3 0x04bc
111 #define CLK_CON_DIV_MIF_CMU_PERI_SPI4 0x04c0
112 #define CLK_CON_DIV_MIF_CMU_ISP_SENSOR0 0x04c4
113 #define CLK_CON_DIV_MIF_CMU_ISP_SENSOR1 0x04c8
114 #define CLK_CON_DIV_MIF_CMU_ISP_SENSOR2 0x04cc
115 #define CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS 0x080c
116 #define CLK_CON_GAT_MIF_HSI2C_AP_PCLKS 0x0828
117 #define CLK_CON_GAT_MIF_HSI2C_CP_PCLKS 0x0828
118 #define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0 0x0828
119 #define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1 0x0828
120 #define CLK_CON_GAT_MIF_HSI2C_AP_PCLKM 0x0840
121 #define CLK_CON_GAT_MIF_HSI2C_CP_PCLKM 0x0840
122 #define CLK_CON_GAT_MIF_HSI2C_IPCLK 0x0840
123 #define CLK_CON_GAT_MIF_HSI2C_ITCLK 0x0840
124 #define CLK_CON_GAT_MIF_CP_PCLK_HSI2C 0x0840
125 #define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0 0x0840
126 #define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1 0x0840
127 #define CLK_CON_GAT_MIF_CMU_G3D_SWITCH 0x0860
128 #define CLK_CON_GAT_MIF_CMU_ISP_VRA 0x0864
129 #define CLK_CON_GAT_MIF_CMU_ISP_CAM 0x0868
130 #define CLK_CON_GAT_MIF_CMU_ISP_ISP 0x086c
131 #define CLK_CON_GAT_MIF_CMU_DISPAUD_BUS 0x0870
132 #define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK 0x0874
133 #define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK 0x0878
134 #define CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL 0x087c
135 #define CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC 0x0880
136 #define CLK_CON_GAT_MIF_CMU_FSYS_BUS 0x0884
137 #define CLK_CON_GAT_MIF_CMU_FSYS_MMC0 0x0888
138 #define CLK_CON_GAT_MIF_CMU_FSYS_MMC1 0x088c
139 #define CLK_CON_GAT_MIF_CMU_FSYS_MMC2 0x0890
140 #define CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK 0x089c
141 #define CLK_CON_GAT_MIF_CMU_PERI_BUS 0x08a0
142 #define CLK_CON_GAT_MIF_CMU_PERI_UART1 0x08a4
143 #define CLK_CON_GAT_MIF_CMU_PERI_UART2 0x08a8
144 #define CLK_CON_GAT_MIF_CMU_PERI_UART0 0x08ac
145 #define CLK_CON_GAT_MIF_CMU_PERI_SPI2 0x08b0
146 #define CLK_CON_GAT_MIF_CMU_PERI_SPI1 0x08b4
147 #define CLK_CON_GAT_MIF_CMU_PERI_SPI0 0x08b8
148 #define CLK_CON_GAT_MIF_CMU_PERI_SPI3 0x08bc
149 #define CLK_CON_GAT_MIF_CMU_PERI_SPI4 0x08c0
150 #define CLK_CON_GAT_MIF_CMU_ISP_SENSOR0 0x08c4
151 #define CLK_CON_GAT_MIF_CMU_ISP_SENSOR1 0x08c8
152 #define CLK_CON_GAT_MIF_CMU_ISP_SENSOR2 0x08cc
153
154 static const unsigned long mif_clk_regs[] __initconst = {
155 PLL_LOCKTIME_MIF_MEM_PLL,
156 PLL_LOCKTIME_MIF_MEDIA_PLL,
157 PLL_LOCKTIME_MIF_BUS_PLL,
158 PLL_CON0_MIF_MEM_PLL,
159 PLL_CON0_MIF_MEDIA_PLL,
160 PLL_CON0_MIF_BUS_PLL,
161 CLK_CON_GAT_MIF_MUX_MEM_PLL,
162 CLK_CON_GAT_MIF_MUX_MEM_PLL_CON,
163 CLK_CON_GAT_MIF_MUX_MEDIA_PLL,
164 CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON,
165 CLK_CON_GAT_MIF_MUX_BUS_PLL,
166 CLK_CON_GAT_MIF_MUX_BUS_PLL_CON,
167 CLK_CON_GAT_MIF_MUX_BUSD,
168 CLK_CON_MUX_MIF_BUSD,
169 CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA,
170 CLK_CON_MUX_MIF_CMU_ISP_VRA,
171 CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM,
172 CLK_CON_MUX_MIF_CMU_ISP_CAM,
173 CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP,
174 CLK_CON_MUX_MIF_CMU_ISP_ISP,
175 CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS,
176 CLK_CON_MUX_MIF_CMU_DISPAUD_BUS,
177 CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK,
178 CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK,
179 CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK,
180 CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK,
181 CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL,
182 CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL,
183 CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC,
184 CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC,
185 CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS,
186 CLK_CON_MUX_MIF_CMU_FSYS_BUS,
187 CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0,
188 CLK_CON_MUX_MIF_CMU_FSYS_MMC0,
189 CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1,
190 CLK_CON_MUX_MIF_CMU_FSYS_MMC1,
191 CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2,
192 CLK_CON_MUX_MIF_CMU_FSYS_MMC2,
193 CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK,
194 CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK,
195 CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS,
196 CLK_CON_MUX_MIF_CMU_PERI_BUS,
197 CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1,
198 CLK_CON_MUX_MIF_CMU_PERI_UART1,
199 CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2,
200 CLK_CON_MUX_MIF_CMU_PERI_UART2,
201 CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0,
202 CLK_CON_MUX_MIF_CMU_PERI_UART0,
203 CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2,
204 CLK_CON_MUX_MIF_CMU_PERI_SPI2,
205 CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1,
206 CLK_CON_MUX_MIF_CMU_PERI_SPI1,
207 CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0,
208 CLK_CON_MUX_MIF_CMU_PERI_SPI0,
209 CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3,
210 CLK_CON_MUX_MIF_CMU_PERI_SPI3,
211 CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4,
212 CLK_CON_MUX_MIF_CMU_PERI_SPI4,
213 CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0,
214 CLK_CON_MUX_MIF_CMU_ISP_SENSOR0,
215 CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1,
216 CLK_CON_MUX_MIF_CMU_ISP_SENSOR1,
217 CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2,
218 CLK_CON_MUX_MIF_CMU_ISP_SENSOR2,
219 CLK_CON_DIV_MIF_BUSD,
220 CLK_CON_DIV_MIF_APB,
221 CLK_CON_DIV_MIF_HSI2C,
222 CLK_CON_DIV_MIF_CMU_G3D_SWITCH,
223 CLK_CON_DIV_MIF_CMU_ISP_VRA,
224 CLK_CON_DIV_MIF_CMU_ISP_CAM,
225 CLK_CON_DIV_MIF_CMU_ISP_ISP,
226 CLK_CON_DIV_MIF_CMU_DISPAUD_BUS,
227 CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK,
228 CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK,
229 CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL,
230 CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC,
231 CLK_CON_DIV_MIF_CMU_FSYS_BUS,
232 CLK_CON_DIV_MIF_CMU_FSYS_MMC0,
233 CLK_CON_DIV_MIF_CMU_FSYS_MMC1,
234 CLK_CON_DIV_MIF_CMU_FSYS_MMC2,
235 CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK,
236 CLK_CON_DIV_MIF_CMU_PERI_BUS,
237 CLK_CON_DIV_MIF_CMU_PERI_UART1,
238 CLK_CON_DIV_MIF_CMU_PERI_UART2,
239 CLK_CON_DIV_MIF_CMU_PERI_UART0,
240 CLK_CON_DIV_MIF_CMU_PERI_SPI2,
241 CLK_CON_DIV_MIF_CMU_PERI_SPI1,
242 CLK_CON_DIV_MIF_CMU_PERI_SPI0,
243 CLK_CON_DIV_MIF_CMU_PERI_SPI3,
244 CLK_CON_DIV_MIF_CMU_PERI_SPI4,
245 CLK_CON_DIV_MIF_CMU_ISP_SENSOR0,
246 CLK_CON_DIV_MIF_CMU_ISP_SENSOR1,
247 CLK_CON_DIV_MIF_CMU_ISP_SENSOR2,
248 CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS,
249 CLK_CON_GAT_MIF_HSI2C_AP_PCLKS,
250 CLK_CON_GAT_MIF_HSI2C_CP_PCLKS,
251 CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0,
252 CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1,
253 CLK_CON_GAT_MIF_HSI2C_AP_PCLKM,
254 CLK_CON_GAT_MIF_HSI2C_CP_PCLKM,
255 CLK_CON_GAT_MIF_HSI2C_IPCLK,
256 CLK_CON_GAT_MIF_HSI2C_ITCLK,
257 CLK_CON_GAT_MIF_CP_PCLK_HSI2C,
258 CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0,
259 CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1,
260 CLK_CON_GAT_MIF_CMU_G3D_SWITCH,
261 CLK_CON_GAT_MIF_CMU_ISP_VRA,
262 CLK_CON_GAT_MIF_CMU_ISP_CAM,
263 CLK_CON_GAT_MIF_CMU_ISP_ISP,
264 CLK_CON_GAT_MIF_CMU_DISPAUD_BUS,
265 CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK,
266 CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK,
267 CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL,
268 CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC,
269 CLK_CON_GAT_MIF_CMU_FSYS_BUS,
270 CLK_CON_GAT_MIF_CMU_FSYS_MMC0,
271 CLK_CON_GAT_MIF_CMU_FSYS_MMC1,
272 CLK_CON_GAT_MIF_CMU_FSYS_MMC2,
273 CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK,
274 CLK_CON_GAT_MIF_CMU_PERI_BUS,
275 CLK_CON_GAT_MIF_CMU_PERI_UART1,
276 CLK_CON_GAT_MIF_CMU_PERI_UART2,
277 CLK_CON_GAT_MIF_CMU_PERI_UART0,
278 CLK_CON_GAT_MIF_CMU_PERI_SPI2,
279 CLK_CON_GAT_MIF_CMU_PERI_SPI1,
280 CLK_CON_GAT_MIF_CMU_PERI_SPI0,
281 CLK_CON_GAT_MIF_CMU_PERI_SPI3,
282 CLK_CON_GAT_MIF_CMU_PERI_SPI4,
283 CLK_CON_GAT_MIF_CMU_ISP_SENSOR0,
284 CLK_CON_GAT_MIF_CMU_ISP_SENSOR1,
285 CLK_CON_GAT_MIF_CMU_ISP_SENSOR2,
286 };
287
288 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
289 FFACTOR(0, "ffac_mif_mux_bus_pll_div2", "gout_mif_mux_bus_pll_con", 1, 2,
290 0),
291 FFACTOR(0, "ffac_mif_mux_media_pll_div2", "gout_mif_mux_media_pll_con",
292 1, 2, 0),
293 FFACTOR(0, "ffac_mif_mux_mem_pll_div2", "gout_mif_mux_mem_pll_con", 1, 2,
294 0),
295 };
296
297 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
298 PLL(pll_1417x, CLK_FOUT_MIF_BUS_PLL, "fout_mif_bus_pll", "oscclk",
299 PLL_LOCKTIME_MIF_BUS_PLL, PLL_CON0_MIF_BUS_PLL, NULL),
300 PLL(pll_1417x, CLK_FOUT_MIF_MEDIA_PLL, "fout_mif_media_pll", "oscclk",
301 PLL_LOCKTIME_MIF_MEDIA_PLL, PLL_CON0_MIF_MEDIA_PLL, NULL),
302 PLL(pll_1417x, CLK_FOUT_MIF_MEM_PLL, "fout_mif_mem_pll", "oscclk",
303 PLL_LOCKTIME_MIF_MEM_PLL, PLL_CON0_MIF_MEM_PLL, NULL),
304 };
305
306 /* List of parent clocks for muxes in CMU_MIF */
307 PNAME(mout_mif_cmu_dispaud_bus_p) = { "ffac_mif_mux_bus_pll_div2",
308 "ffac_mif_mux_media_pll_div2" };
309 PNAME(mout_mif_cmu_dispaud_decon_eclk_p) = { "ffac_mif_mux_bus_pll_div2",
310 "ffac_mif_mux_media_pll_div2" };
311 PNAME(mout_mif_cmu_dispaud_decon_vclk_p) = { "ffac_mif_mux_bus_pll_div2",
312 "ffac_mif_mux_media_pll_div2" };
313 PNAME(mout_mif_cmu_fsys_bus_p) = { "ffac_mif_mux_bus_pll_div2",
314 "ffac_mif_mux_media_pll_div2" };
315 PNAME(mout_mif_cmu_fsys_mmc0_p) = { "ffac_mif_mux_bus_pll_div2",
316 "ffac_mif_mux_media_pll_div2" };
317 PNAME(mout_mif_cmu_fsys_mmc1_p) = { "ffac_mif_mux_bus_pll_div2",
318 "ffac_mif_mux_media_pll_div2" };
319 PNAME(mout_mif_cmu_fsys_mmc2_p) = { "ffac_mif_mux_bus_pll_div2",
320 "ffac_mif_mux_media_pll_div2" };
321 PNAME(mout_mif_cmu_fsys_usb20drd_refclk_p) = { "ffac_mif_mux_bus_pll_div2",
322 "ffac_mif_mux_media_pll_div2" };
323 PNAME(mout_mif_cmu_isp_cam_p) = { "ffac_mif_mux_bus_pll_div2",
324 "ffac_mif_mux_media_pll_div2" };
325 PNAME(mout_mif_cmu_isp_isp_p) = { "ffac_mif_mux_bus_pll_div2",
326 "ffac_mif_mux_media_pll_div2" };
327 PNAME(mout_mif_cmu_isp_sensor0_p) = { "ffac_mif_mux_bus_pll_div2",
328 "oscclk" };
329 PNAME(mout_mif_cmu_isp_sensor1_p) = { "ffac_mif_mux_bus_pll_div2",
330 "oscclk" };
331 PNAME(mout_mif_cmu_isp_sensor2_p) = { "ffac_mif_mux_bus_pll_div2",
332 "oscclk" };
333 PNAME(mout_mif_cmu_isp_vra_p) = { "ffac_mif_mux_bus_pll_div2",
334 "ffac_mif_mux_media_pll_div2",
335 "gout_mif_mux_bus_pll_con" };
336 PNAME(mout_mif_cmu_mfcmscl_mfc_p) = { "ffac_mif_mux_bus_pll_div2",
337 "ffac_mif_mux_media_pll_div2",
338 "gout_mif_mux_bus_pll_con" };
339 PNAME(mout_mif_cmu_mfcmscl_mscl_p) = { "ffac_mif_mux_bus_pll_div2",
340 "ffac_mif_mux_media_pll_div2",
341 "gout_mif_mux_bus_pll_con" };
342 PNAME(mout_mif_cmu_peri_bus_p) = { "ffac_mif_mux_bus_pll_div2",
343 "ffac_mif_mux_media_pll_div2" };
344 PNAME(mout_mif_cmu_peri_spi0_p) = { "ffac_mif_mux_bus_pll_div2",
345 "oscclk" };
346 PNAME(mout_mif_cmu_peri_spi2_p) = { "ffac_mif_mux_bus_pll_div2",
347 "oscclk" };
348 PNAME(mout_mif_cmu_peri_spi1_p) = { "ffac_mif_mux_bus_pll_div2",
349 "oscclk" };
350 PNAME(mout_mif_cmu_peri_spi4_p) = { "ffac_mif_mux_bus_pll_div2",
351 "oscclk" };
352 PNAME(mout_mif_cmu_peri_spi3_p) = { "ffac_mif_mux_bus_pll_div2",
353 "oscclk" };
354 PNAME(mout_mif_cmu_peri_uart1_p) = { "ffac_mif_mux_bus_pll_div2",
355 "ffac_mif_mux_media_pll_div2" };
356 PNAME(mout_mif_cmu_peri_uart2_p) = { "ffac_mif_mux_bus_pll_div2",
357 "ffac_mif_mux_media_pll_div2" };
358 PNAME(mout_mif_cmu_peri_uart0_p) = { "ffac_mif_mux_bus_pll_div2",
359 "ffac_mif_mux_media_pll_div2" };
360 PNAME(mout_mif_busd_p) = { "ffac_mif_mux_bus_pll_div2",
361 "ffac_mif_mux_media_pll_div2",
362 "ffac_mif_mux_mem_pll_div2" };
363
364 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
365 MUX(CLK_MOUT_MIF_CMU_DISPAUD_BUS, "mout_mif_cmu_dispaud_bus",
366 mout_mif_cmu_dispaud_bus_p, CLK_CON_MUX_MIF_CMU_DISPAUD_BUS, 12, 1),
367 MUX(CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK,
368 "mout_mif_cmu_dispaud_decon_eclk",
369 mout_mif_cmu_dispaud_decon_eclk_p,
370 CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK, 12, 1),
371 MUX(CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK,
372 "mout_mif_cmu_dispaud_decon_vclk",
373 mout_mif_cmu_dispaud_decon_vclk_p,
374 CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK, 12, 1),
375 MUX(CLK_MOUT_MIF_CMU_FSYS_BUS, "mout_mif_cmu_fsys_bus",
376 mout_mif_cmu_fsys_bus_p, CLK_CON_MUX_MIF_CMU_FSYS_BUS, 12, 1),
377 MUX(CLK_MOUT_MIF_CMU_FSYS_MMC0, "mout_mif_cmu_fsys_mmc0",
378 mout_mif_cmu_fsys_mmc0_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC0, 12, 1),
379 MUX(CLK_MOUT_MIF_CMU_FSYS_MMC1, "mout_mif_cmu_fsys_mmc1",
380 mout_mif_cmu_fsys_mmc1_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC1, 12, 1),
381 MUX(CLK_MOUT_MIF_CMU_FSYS_MMC2, "mout_mif_cmu_fsys_mmc2",
382 mout_mif_cmu_fsys_mmc2_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC2, 12, 1),
383 MUX(CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
384 "mout_mif_cmu_fsys_usb20drd_refclk",
385 mout_mif_cmu_fsys_usb20drd_refclk_p,
386 CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK, 12, 1),
387 MUX(CLK_MOUT_MIF_CMU_ISP_CAM, "mout_mif_cmu_isp_cam",
388 mout_mif_cmu_isp_cam_p, CLK_CON_MUX_MIF_CMU_ISP_CAM, 12, 1),
389 MUX(CLK_MOUT_MIF_CMU_ISP_ISP, "mout_mif_cmu_isp_isp",
390 mout_mif_cmu_isp_isp_p, CLK_CON_MUX_MIF_CMU_ISP_ISP, 12, 1),
391 MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR0, "mout_mif_cmu_isp_sensor0",
392 mout_mif_cmu_isp_sensor0_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR0, 12, 1),
393 MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR1, "mout_mif_cmu_isp_sensor1",
394 mout_mif_cmu_isp_sensor1_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR1, 12, 1),
395 MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR2, "mout_mif_cmu_isp_sensor2",
396 mout_mif_cmu_isp_sensor2_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR2, 12, 1),
397 MUX(CLK_MOUT_MIF_CMU_ISP_VRA, "mout_mif_cmu_isp_vra",
398 mout_mif_cmu_isp_vra_p, CLK_CON_MUX_MIF_CMU_ISP_VRA, 12, 2),
399 MUX(CLK_MOUT_MIF_CMU_MFCMSCL_MFC, "mout_mif_cmu_mfcmscl_mfc",
400 mout_mif_cmu_mfcmscl_mfc_p, CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC, 12, 2),
401 MUX(CLK_MOUT_MIF_CMU_MFCMSCL_MSCL, "mout_mif_cmu_mfcmscl_mscl",
402 mout_mif_cmu_mfcmscl_mscl_p, CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL, 12,
403 2),
404 MUX(CLK_MOUT_MIF_CMU_PERI_BUS, "mout_mif_cmu_peri_bus",
405 mout_mif_cmu_peri_bus_p, CLK_CON_MUX_MIF_CMU_PERI_BUS, 12, 1),
406 MUX(CLK_MOUT_MIF_CMU_PERI_SPI0, "mout_mif_cmu_peri_spi0",
407 mout_mif_cmu_peri_spi0_p, CLK_CON_MUX_MIF_CMU_PERI_SPI0, 12, 1),
408 MUX(CLK_MOUT_MIF_CMU_PERI_SPI2, "mout_mif_cmu_peri_spi2",
409 mout_mif_cmu_peri_spi2_p, CLK_CON_MUX_MIF_CMU_PERI_SPI2, 12, 1),
410 MUX(CLK_MOUT_MIF_CMU_PERI_SPI1, "mout_mif_cmu_peri_spi1",
411 mout_mif_cmu_peri_spi1_p, CLK_CON_MUX_MIF_CMU_PERI_SPI1, 12, 1),
412 MUX(CLK_MOUT_MIF_CMU_PERI_SPI4, "mout_mif_cmu_peri_spi4",
413 mout_mif_cmu_peri_spi4_p, CLK_CON_MUX_MIF_CMU_PERI_SPI4, 12, 1),
414 MUX(CLK_MOUT_MIF_CMU_PERI_SPI3, "mout_mif_cmu_peri_spi3",
415 mout_mif_cmu_peri_spi3_p, CLK_CON_MUX_MIF_CMU_PERI_SPI3, 12, 1),
416 MUX(CLK_MOUT_MIF_CMU_PERI_UART1, "mout_mif_cmu_peri_uart1",
417 mout_mif_cmu_peri_uart1_p, CLK_CON_MUX_MIF_CMU_PERI_UART1, 12, 1),
418 MUX(CLK_MOUT_MIF_CMU_PERI_UART2, "mout_mif_cmu_peri_uart2",
419 mout_mif_cmu_peri_uart2_p, CLK_CON_MUX_MIF_CMU_PERI_UART2, 12, 1),
420 MUX(CLK_MOUT_MIF_CMU_PERI_UART0, "mout_mif_cmu_peri_uart0",
421 mout_mif_cmu_peri_uart0_p, CLK_CON_MUX_MIF_CMU_PERI_UART0, 12, 1),
422 MUX(CLK_MOUT_MIF_BUSD, "mout_mif_busd", mout_mif_busd_p,
423 CLK_CON_MUX_MIF_BUSD, 12, 2),
424 };
425
426 static const struct samsung_div_clock mif_div_clks[] __initconst = {
427 DIV(CLK_DOUT_MIF_CMU_DISPAUD_BUS, "dout_mif_cmu_dispaud_bus",
428 "gout_mif_mux_cmu_dispaud_bus", CLK_CON_DIV_MIF_CMU_DISPAUD_BUS, 0,
429 4),
430 DIV(CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK,
431 "dout_mif_cmu_dispaud_decon_eclk",
432 "gout_mif_mux_cmu_dispaud_decon_eclk",
433 CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK, 0, 4),
434 DIV(CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK,
435 "dout_mif_cmu_dispaud_decon_vclk",
436 "gout_mif_mux_cmu_dispaud_decon_vclk",
437 CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK, 0, 4),
438 DIV(CLK_DOUT_MIF_CMU_FSYS_BUS, "dout_mif_cmu_fsys_bus",
439 "gout_mif_mux_cmu_fsys_bus", CLK_CON_DIV_MIF_CMU_FSYS_BUS, 0, 4),
440 DIV(CLK_DOUT_MIF_CMU_FSYS_MMC0, "dout_mif_cmu_fsys_mmc0",
441 "gout_mif_mux_cmu_fsys_mmc0", CLK_CON_DIV_MIF_CMU_FSYS_MMC0, 0, 10),
442 DIV(CLK_DOUT_MIF_CMU_FSYS_MMC1, "dout_mif_cmu_fsys_mmc1",
443 "gout_mif_mux_cmu_fsys_mmc1", CLK_CON_DIV_MIF_CMU_FSYS_MMC1, 0, 10),
444 DIV(CLK_DOUT_MIF_CMU_FSYS_MMC2, "dout_mif_cmu_fsys_mmc2",
445 "gout_mif_mux_cmu_fsys_mmc2", CLK_CON_DIV_MIF_CMU_FSYS_MMC2, 0, 10),
446 DIV(CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
447 "dout_mif_cmu_fsys_usb20drd_refclk",
448 "gout_mif_mux_cmu_fsys_usb20drd_refclk",
449 CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, 4),
450 DIV(CLK_DOUT_MIF_CMU_G3D_SWITCH, "dout_mif_cmu_g3d_switch",
451 "ffac_mif_mux_bus_pll_div2", CLK_CON_DIV_MIF_CMU_G3D_SWITCH, 0, 2),
452 DIV(CLK_DOUT_MIF_CMU_ISP_CAM, "dout_mif_cmu_isp_cam",
453 "gout_mif_mux_cmu_isp_cam", CLK_CON_DIV_MIF_CMU_ISP_CAM, 0, 4),
454 DIV(CLK_DOUT_MIF_CMU_ISP_ISP, "dout_mif_cmu_isp_isp",
455 "gout_mif_mux_cmu_isp_isp", CLK_CON_DIV_MIF_CMU_ISP_ISP, 0, 4),
456 DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR0, "dout_mif_cmu_isp_sensor0",
457 "gout_mif_mux_cmu_isp_sensor0", CLK_CON_DIV_MIF_CMU_ISP_SENSOR0, 0,
458 6),
459 DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR1, "dout_mif_cmu_isp_sensor1",
460 "gout_mif_mux_cmu_isp_sensor1", CLK_CON_DIV_MIF_CMU_ISP_SENSOR1, 0,
461 6),
462 DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR2, "dout_mif_cmu_isp_sensor2",
463 "gout_mif_mux_cmu_isp_sensor2", CLK_CON_DIV_MIF_CMU_ISP_SENSOR2, 0,
464 6),
465 DIV(CLK_DOUT_MIF_CMU_ISP_VRA, "dout_mif_cmu_isp_vra",
466 "gout_mif_mux_cmu_isp_vra", CLK_CON_DIV_MIF_CMU_ISP_VRA, 0, 4),
467 DIV(CLK_DOUT_MIF_CMU_MFCMSCL_MFC, "dout_mif_cmu_mfcmscl_mfc",
468 "gout_mif_mux_cmu_mfcmscl_mfc", CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC, 0,
469 4),
470 DIV(CLK_DOUT_MIF_CMU_MFCMSCL_MSCL, "dout_mif_cmu_mfcmscl_mscl",
471 "gout_mif_mux_cmu_mfcmscl_mscl", CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL,
472 0, 4),
473 DIV(CLK_DOUT_MIF_CMU_PERI_BUS, "dout_mif_cmu_peri_bus",
474 "gout_mif_mux_cmu_peri_bus", CLK_CON_DIV_MIF_CMU_PERI_BUS, 0, 4),
475 DIV(CLK_DOUT_MIF_CMU_PERI_SPI0, "dout_mif_cmu_peri_spi0",
476 "gout_mif_mux_cmu_peri_spi0", CLK_CON_DIV_MIF_CMU_PERI_SPI0, 0, 6),
477 DIV(CLK_DOUT_MIF_CMU_PERI_SPI2, "dout_mif_cmu_peri_spi2",
478 "gout_mif_mux_cmu_peri_spi2", CLK_CON_DIV_MIF_CMU_PERI_SPI2, 0, 6),
479 DIV(CLK_DOUT_MIF_CMU_PERI_SPI1, "dout_mif_cmu_peri_spi1",
480 "gout_mif_mux_cmu_peri_spi1", CLK_CON_DIV_MIF_CMU_PERI_SPI1, 0, 6),
481 DIV(CLK_DOUT_MIF_CMU_PERI_SPI4, "dout_mif_cmu_peri_spi4",
482 "gout_mif_mux_cmu_peri_spi4", CLK_CON_DIV_MIF_CMU_PERI_SPI4, 0, 6),
483 DIV(CLK_DOUT_MIF_CMU_PERI_SPI3, "dout_mif_cmu_peri_spi3",
484 "gout_mif_mux_cmu_peri_spi3", CLK_CON_DIV_MIF_CMU_PERI_SPI3, 0, 6),
485 DIV(CLK_DOUT_MIF_CMU_PERI_UART1, "dout_mif_cmu_peri_uart1",
486 "gout_mif_mux_cmu_peri_uart1", CLK_CON_DIV_MIF_CMU_PERI_UART1, 0, 4),
487 DIV(CLK_DOUT_MIF_CMU_PERI_UART2, "dout_mif_cmu_peri_uart2",
488 "gout_mif_mux_cmu_peri_uart2", CLK_CON_DIV_MIF_CMU_PERI_UART2, 0, 4),
489 DIV(CLK_DOUT_MIF_CMU_PERI_UART0, "dout_mif_cmu_peri_uart0",
490 "gout_mif_mux_cmu_peri_uart0", CLK_CON_DIV_MIF_CMU_PERI_UART0, 0, 4),
491 DIV(CLK_DOUT_MIF_APB, "dout_mif_apb", "dout_mif_busd",
492 CLK_CON_DIV_MIF_APB, 0, 2),
493 DIV(CLK_DOUT_MIF_BUSD, "dout_mif_busd", "gout_mif_mux_busd",
494 CLK_CON_DIV_MIF_BUSD, 0, 4),
495 DIV(CLK_DOUT_MIF_HSI2C, "dout_mif_hsi2c", "ffac_mif_mux_media_pll_div2",
496 CLK_CON_DIV_MIF_HSI2C, 0, 4),
497 };
498
499 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
500 GATE(CLK_GOUT_MIF_CMU_DISPAUD_BUS, "gout_mif_cmu_dispaud_bus",
501 "dout_mif_cmu_dispaud_bus", CLK_CON_GAT_MIF_CMU_DISPAUD_BUS, 0,
502 CLK_SET_RATE_PARENT, 0),
503 GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK,
504 "gout_mif_cmu_dispaud_decon_eclk",
505 "dout_mif_cmu_dispaud_decon_eclk",
506 CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK, 0, CLK_SET_RATE_PARENT, 0),
507 GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK,
508 "gout_mif_cmu_dispaud_decon_vclk",
509 "dout_mif_cmu_dispaud_decon_vclk",
510 CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK, 0, CLK_SET_RATE_PARENT, 0),
511 GATE(CLK_GOUT_MIF_CMU_FSYS_BUS, "gout_mif_cmu_fsys_bus",
512 "dout_mif_cmu_fsys_bus", CLK_CON_GAT_MIF_CMU_FSYS_BUS, 0,
513 CLK_SET_RATE_PARENT, 0),
514 GATE(CLK_GOUT_MIF_CMU_FSYS_MMC0, "gout_mif_cmu_fsys_mmc0",
515 "dout_mif_cmu_fsys_mmc0", CLK_CON_GAT_MIF_CMU_FSYS_MMC0, 0,
516 CLK_SET_RATE_PARENT, 0),
517 GATE(CLK_GOUT_MIF_CMU_FSYS_MMC1, "gout_mif_cmu_fsys_mmc1",
518 "dout_mif_cmu_fsys_mmc1", CLK_CON_GAT_MIF_CMU_FSYS_MMC1, 0,
519 CLK_SET_RATE_PARENT, 0),
520 GATE(CLK_GOUT_MIF_CMU_FSYS_MMC2, "gout_mif_cmu_fsys_mmc2",
521 "dout_mif_cmu_fsys_mmc2", CLK_CON_GAT_MIF_CMU_FSYS_MMC2, 0,
522 CLK_SET_RATE_PARENT, 0),
523 GATE(CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
524 "gout_mif_cmu_fsys_usb20drd_refclk",
525 "dout_mif_cmu_fsys_usb20drd_refclk",
526 CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, CLK_SET_RATE_PARENT,
527 0),
528 GATE(CLK_GOUT_MIF_CMU_G3D_SWITCH, "gout_mif_cmu_g3d_switch",
529 "dout_mif_cmu_g3d_switch", CLK_CON_GAT_MIF_CMU_G3D_SWITCH, 0,
530 CLK_SET_RATE_PARENT, 0),
531 GATE(CLK_GOUT_MIF_CMU_ISP_CAM, "gout_mif_cmu_isp_cam",
532 "dout_mif_cmu_isp_cam", CLK_CON_GAT_MIF_CMU_ISP_CAM, 0,
533 CLK_SET_RATE_PARENT, 0),
534 GATE(CLK_GOUT_MIF_CMU_ISP_ISP, "gout_mif_cmu_isp_isp",
535 "dout_mif_cmu_isp_isp", CLK_CON_GAT_MIF_CMU_ISP_ISP, 0,
536 CLK_SET_RATE_PARENT, 0),
537 GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR0, "gout_mif_cmu_isp_sensor0",
538 "dout_mif_cmu_isp_sensor0", CLK_CON_GAT_MIF_CMU_ISP_SENSOR0, 0,
539 CLK_SET_RATE_PARENT, 0),
540 GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR1, "gout_mif_cmu_isp_sensor1",
541 "dout_mif_cmu_isp_sensor1", CLK_CON_GAT_MIF_CMU_ISP_SENSOR1, 0,
542 CLK_SET_RATE_PARENT, 0),
543 GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR2, "gout_mif_cmu_isp_sensor2",
544 "dout_mif_cmu_isp_sensor2", CLK_CON_GAT_MIF_CMU_ISP_SENSOR2, 0,
545 CLK_SET_RATE_PARENT, 0),
546 GATE(CLK_GOUT_MIF_CMU_ISP_VRA, "gout_mif_cmu_isp_vra",
547 "dout_mif_cmu_isp_vra", CLK_CON_GAT_MIF_CMU_ISP_VRA, 0,
548 CLK_SET_RATE_PARENT, 0),
549 GATE(CLK_GOUT_MIF_CMU_MFCMSCL_MFC, "gout_mif_cmu_mfcmscl_mfc",
550 "dout_mif_cmu_mfcmscl_mfc", CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC, 0,
551 CLK_SET_RATE_PARENT, 0),
552 GATE(CLK_GOUT_MIF_CMU_MFCMSCL_MSCL, "gout_mif_cmu_mfcmscl_mscl",
553 "dout_mif_cmu_mfcmscl_mscl", CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL, 0,
554 CLK_SET_RATE_PARENT, 0),
555 GATE(CLK_GOUT_MIF_CMU_PERI_BUS, "gout_mif_cmu_peri_bus",
556 "dout_mif_cmu_peri_bus", CLK_CON_GAT_MIF_CMU_PERI_BUS, 0,
557 CLK_SET_RATE_PARENT, 0),
558 GATE(CLK_GOUT_MIF_CMU_PERI_SPI0, "gout_mif_cmu_peri_spi0",
559 "dout_mif_cmu_peri_spi0", CLK_CON_GAT_MIF_CMU_PERI_SPI0, 0,
560 CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_GOUT_MIF_CMU_PERI_SPI2, "gout_mif_cmu_peri_spi2",
562 "dout_mif_cmu_peri_spi2", CLK_CON_GAT_MIF_CMU_PERI_SPI2, 0,
563 CLK_SET_RATE_PARENT, 0),
564 GATE(CLK_GOUT_MIF_CMU_PERI_SPI1, "gout_mif_cmu_peri_spi1",
565 "dout_mif_cmu_peri_spi1", CLK_CON_GAT_MIF_CMU_PERI_SPI1, 0,
566 CLK_SET_RATE_PARENT, 0),
567 GATE(CLK_GOUT_MIF_CMU_PERI_SPI4, "gout_mif_cmu_peri_spi4",
568 "dout_mif_cmu_peri_spi4", CLK_CON_GAT_MIF_CMU_PERI_SPI4, 0,
569 CLK_SET_RATE_PARENT, 0),
570 GATE(CLK_GOUT_MIF_CMU_PERI_SPI3, "gout_mif_cmu_peri_spi3",
571 "dout_mif_cmu_peri_spi3", CLK_CON_GAT_MIF_CMU_PERI_SPI3, 0,
572 CLK_SET_RATE_PARENT, 0),
573 GATE(CLK_GOUT_MIF_CMU_PERI_UART1, "gout_mif_cmu_peri_uart1",
574 "dout_mif_cmu_peri_uart1", CLK_CON_GAT_MIF_CMU_PERI_UART1, 0,
575 CLK_SET_RATE_PARENT, 0),
576 GATE(CLK_GOUT_MIF_CMU_PERI_UART2, "gout_mif_cmu_peri_uart2",
577 "dout_mif_cmu_peri_uart2", CLK_CON_GAT_MIF_CMU_PERI_UART2, 0,
578 CLK_SET_RATE_PARENT, 0),
579 GATE(CLK_GOUT_MIF_CMU_PERI_UART0, "gout_mif_cmu_peri_uart0",
580 "dout_mif_cmu_peri_uart0", CLK_CON_GAT_MIF_CMU_PERI_UART0, 0,
581 CLK_SET_RATE_PARENT, 0),
582 GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKM, "gout_mif_hsi2c_ap_pclkm",
583 "dout_mif_hsi2c", CLK_CON_GAT_MIF_HSI2C_AP_PCLKM, 0,
584 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
585 GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKS, "gout_mif_hsi2c_ap_pclks",
586 "dout_mif_apb", CLK_CON_GAT_MIF_HSI2C_AP_PCLKS, 14, CLK_IS_CRITICAL
587 | CLK_SET_RATE_PARENT, 0),
588 GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKM, "gout_mif_hsi2c_cp_pclkm",
589 "dout_mif_hsi2c", CLK_CON_GAT_MIF_HSI2C_CP_PCLKM, 1,
590 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
591 GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKS, "gout_mif_hsi2c_cp_pclks",
592 "dout_mif_apb", CLK_CON_GAT_MIF_HSI2C_CP_PCLKS, 15, CLK_IS_CRITICAL
593 | CLK_SET_RATE_PARENT, 0),
594 GATE(CLK_GOUT_MIF_HSI2C_IPCLK, "gout_mif_hsi2c_ipclk", "dout_mif_hsi2c",
595 CLK_CON_GAT_MIF_HSI2C_IPCLK, 2, CLK_IS_CRITICAL |
596 CLK_SET_RATE_PARENT, 0),
597 GATE(CLK_GOUT_MIF_HSI2C_ITCLK, "gout_mif_hsi2c_itclk", "dout_mif_hsi2c",
598 CLK_CON_GAT_MIF_HSI2C_ITCLK, 3, CLK_IS_CRITICAL |
599 CLK_SET_RATE_PARENT, 0),
600 GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C, "gout_mif_cp_pclk_hsi2c",
601 "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C, 6, CLK_IS_CRITICAL
602 | CLK_SET_RATE_PARENT, 0),
603 GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0, "gout_mif_cp_pclk_hsi2c_bat_0",
604 "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0, 4,
605 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
606 GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1, "gout_mif_cp_pclk_hsi2c_bat_1",
607 "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1, 5,
608 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
609 GATE(CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS, "gout_mif_wrap_adc_if_osc_sys",
610 "oscclk", CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS, 3,
611 CLK_SET_RATE_PARENT, 0),
612 GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0, "gout_mif_wrap_adc_if_pclk_s0",
613 "dout_mif_apb", CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0, 20,
614 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
615 GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1, "gout_mif_wrap_adc_if_pclk_s1",
616 "dout_mif_apb", CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1, 21,
617 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
618 GATE(CLK_GOUT_MIF_MUX_BUS_PLL, "gout_mif_mux_bus_pll",
619 "gout_mif_mux_bus_pll_con", CLK_CON_GAT_MIF_MUX_BUS_PLL, 21,
620 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
621 GATE(CLK_GOUT_MIF_MUX_BUS_PLL_CON, "gout_mif_mux_bus_pll_con",
622 "fout_mif_bus_pll", CLK_CON_GAT_MIF_MUX_BUS_PLL_CON, 12,
623 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
624 GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS, "gout_mif_mux_cmu_dispaud_bus",
625 "mout_mif_cmu_dispaud_bus", CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS,
626 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
627 GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK,
628 "gout_mif_mux_cmu_dispaud_decon_eclk",
629 "mout_mif_cmu_dispaud_decon_eclk",
630 CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK, 21, CLK_IS_CRITICAL |
631 CLK_SET_RATE_PARENT, 0),
632 GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK,
633 "gout_mif_mux_cmu_dispaud_decon_vclk",
634 "mout_mif_cmu_dispaud_decon_vclk",
635 CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK, 21, CLK_IS_CRITICAL |
636 CLK_SET_RATE_PARENT, 0),
637 GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_BUS, "gout_mif_mux_cmu_fsys_bus",
638 "mout_mif_cmu_fsys_bus", CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS, 21,
639 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
640 GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0, "gout_mif_mux_cmu_fsys_mmc0",
641 "mout_mif_cmu_fsys_mmc0", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0, 21,
642 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
643 GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1, "gout_mif_mux_cmu_fsys_mmc1",
644 "mout_mif_cmu_fsys_mmc1", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1, 21,
645 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
646 GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2, "gout_mif_mux_cmu_fsys_mmc2",
647 "mout_mif_cmu_fsys_mmc2", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2, 21,
648 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
649 GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK,
650 "gout_mif_mux_cmu_fsys_usb20drd_refclk",
651 "mout_mif_cmu_fsys_usb20drd_refclk",
652 CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, 21, CLK_IS_CRITICAL |
653 CLK_SET_RATE_PARENT, 0),
654 GATE(CLK_GOUT_MIF_MUX_CMU_ISP_CAM, "gout_mif_mux_cmu_isp_cam",
655 "mout_mif_cmu_isp_cam", CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM, 21,
656 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
657 GATE(CLK_GOUT_MIF_MUX_CMU_ISP_ISP, "gout_mif_mux_cmu_isp_isp",
658 "mout_mif_cmu_isp_isp", CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP, 21,
659 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
660 GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0, "gout_mif_mux_cmu_isp_sensor0",
661 "mout_mif_cmu_isp_sensor0", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0,
662 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
663 GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1, "gout_mif_mux_cmu_isp_sensor1",
664 "mout_mif_cmu_isp_sensor1", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1,
665 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
666 GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2, "gout_mif_mux_cmu_isp_sensor2",
667 "mout_mif_cmu_isp_sensor2", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2,
668 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
669 GATE(CLK_GOUT_MIF_MUX_CMU_ISP_VRA, "gout_mif_mux_cmu_isp_vra",
670 "mout_mif_cmu_isp_vra", CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA, 21,
671 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
672 GATE(CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC, "gout_mif_mux_cmu_mfcmscl_mfc",
673 "mout_mif_cmu_mfcmscl_mfc", CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC,
674 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
675 GATE(CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL, "gout_mif_mux_cmu_mfcmscl_mscl",
676 "mout_mif_cmu_mfcmscl_mscl", CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL,
677 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
678 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_BUS, "gout_mif_mux_cmu_peri_bus",
679 "mout_mif_cmu_peri_bus", CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS, 21,
680 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
681 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI0, "gout_mif_mux_cmu_peri_spi0",
682 "mout_mif_cmu_peri_spi0", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0, 21,
683 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
684 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI2, "gout_mif_mux_cmu_peri_spi2",
685 "mout_mif_cmu_peri_spi2", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2, 21,
686 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
687 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI1, "gout_mif_mux_cmu_peri_spi1",
688 "mout_mif_cmu_peri_spi1", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1, 21,
689 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
690 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI4, "gout_mif_mux_cmu_peri_spi4",
691 "mout_mif_cmu_peri_spi4", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4, 21,
692 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
693 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI3, "gout_mif_mux_cmu_peri_spi3",
694 "mout_mif_cmu_peri_spi3", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3, 21,
695 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
696 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART1, "gout_mif_mux_cmu_peri_uart1",
697 "mout_mif_cmu_peri_uart1", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1, 21,
698 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
699 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART2, "gout_mif_mux_cmu_peri_uart2",
700 "mout_mif_cmu_peri_uart2", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2, 21,
701 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
702 GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART0, "gout_mif_mux_cmu_peri_uart0",
703 "mout_mif_cmu_peri_uart0", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0, 21,
704 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
705 GATE(CLK_GOUT_MIF_MUX_BUSD, "gout_mif_mux_busd", "mout_mif_busd",
706 CLK_CON_GAT_MIF_MUX_BUSD, 21, CLK_IS_CRITICAL |
707 CLK_SET_RATE_PARENT, 0),
708 GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL, "gout_mif_mux_media_pll",
709 "gout_mif_mux_media_pll_con", CLK_CON_GAT_MIF_MUX_MEDIA_PLL, 21,
710 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
711 GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL_CON, "gout_mif_mux_media_pll_con",
712 "fout_mif_media_pll", CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON, 12,
713 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
714 GATE(CLK_GOUT_MIF_MUX_MEM_PLL, "gout_mif_mux_mem_pll",
715 "gout_mif_mux_mem_pll_con", CLK_CON_GAT_MIF_MUX_MEM_PLL, 21,
716 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
717 GATE(CLK_GOUT_MIF_MUX_MEM_PLL_CON, "gout_mif_mux_mem_pll_con",
718 "fout_mif_mem_pll", CLK_CON_GAT_MIF_MUX_MEM_PLL_CON, 12,
719 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
720 };
721
722 static const struct samsung_cmu_info mif_cmu_info __initconst = {
723 .fixed_factor_clks = mif_fixed_factor_clks,
724 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
725 .pll_clks = mif_pll_clks,
726 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
727 .mux_clks = mif_mux_clks,
728 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
729 .div_clks = mif_div_clks,
730 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
731 .gate_clks = mif_gate_clks,
732 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
733 .clk_regs = mif_clk_regs,
734 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
735 .nr_clk_ids = MIF_NR_CLK,
736 };
737
738 /*
739 * Register offsets for CMU_DISPAUD (0x148d0000)
740 */
741 #define PLL_LOCKTIME_DISPAUD_PLL 0x0000
742 #define PLL_LOCKTIME_DISPAUD_AUD_PLL 0x00c0
743 #define PLL_CON0_DISPAUD_PLL 0x0100
744 #define PLL_CON0_DISPAUD_AUD_PLL 0x01c0
745 #define CLK_CON_GAT_DISPAUD_MUX_PLL 0x0200
746 #define CLK_CON_GAT_DISPAUD_MUX_PLL_CON 0x0200
747 #define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL 0x0204
748 #define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON 0x0204
749 #define CLK_CON_GAT_DISPAUD_MUX_BUS_USER 0x0210
750 #define CLK_CON_MUX_DISPAUD_BUS_USER 0x0210
751 #define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER 0x0214
752 #define CLK_CON_MUX_DISPAUD_DECON_VCLK_USER 0x0214
753 #define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER 0x0218
754 #define CLK_CON_MUX_DISPAUD_DECON_ECLK_USER 0x0218
755 #define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK 0x021c
756 #define CLK_CON_MUX_DISPAUD_DECON_VCLK 0x021c
757 #define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK 0x0220
758 #define CLK_CON_MUX_DISPAUD_DECON_ECLK 0x0220
759 #define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 0x0224
760 #define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 0x0224
761 #define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 0x0228
762 #define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 0x0228
763 #define CLK_CON_GAT_DISPAUD_MUX_MI2S 0x022c
764 #define CLK_CON_MUX_DISPAUD_MI2S 0x022c
765 #define CLK_CON_DIV_DISPAUD_APB 0x0400
766 #define CLK_CON_DIV_DISPAUD_DECON_VCLK 0x0404
767 #define CLK_CON_DIV_DISPAUD_DECON_ECLK 0x0408
768 #define CLK_CON_DIV_DISPAUD_MI2S 0x040c
769 #define CLK_CON_DIV_DISPAUD_MIXER 0x0410
770 #define CLK_CON_GAT_DISPAUD_BUS 0x0810
771 #define CLK_CON_GAT_DISPAUD_BUS_DISP 0x0810
772 #define CLK_CON_GAT_DISPAUD_BUS_PPMU 0x0810
773 #define CLK_CON_GAT_DISPAUD_APB_AUD 0x0814
774 #define CLK_CON_GAT_DISPAUD_APB_AUD_AMP 0x0814
775 #define CLK_CON_GAT_DISPAUD_APB_DISP 0x0814
776 #define CLK_CON_GAT_DISPAUD_DECON_VCLK 0x081c
777 #define CLK_CON_GAT_DISPAUD_DECON_ECLK 0x0820
778 #define CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI 0x082c
779 #define CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI 0x082c
780 #define CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK 0x0830
781 #define CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 0x0834
782 #define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 0x0838
783 #define CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK 0x083c
784 #define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 0x0840
785
786 static const unsigned long dispaud_clk_regs[] __initconst = {
787 PLL_LOCKTIME_DISPAUD_PLL,
788 PLL_LOCKTIME_DISPAUD_AUD_PLL,
789 PLL_CON0_DISPAUD_PLL,
790 PLL_CON0_DISPAUD_AUD_PLL,
791 CLK_CON_GAT_DISPAUD_MUX_PLL,
792 CLK_CON_GAT_DISPAUD_MUX_PLL_CON,
793 CLK_CON_GAT_DISPAUD_MUX_AUD_PLL,
794 CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON,
795 CLK_CON_GAT_DISPAUD_MUX_BUS_USER,
796 CLK_CON_MUX_DISPAUD_BUS_USER,
797 CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER,
798 CLK_CON_MUX_DISPAUD_DECON_VCLK_USER,
799 CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER,
800 CLK_CON_MUX_DISPAUD_DECON_ECLK_USER,
801 CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK,
802 CLK_CON_MUX_DISPAUD_DECON_VCLK,
803 CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK,
804 CLK_CON_MUX_DISPAUD_DECON_ECLK,
805 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER,
806 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON,
807 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER,
808 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON,
809 CLK_CON_GAT_DISPAUD_MUX_MI2S,
810 CLK_CON_MUX_DISPAUD_MI2S,
811 CLK_CON_DIV_DISPAUD_APB,
812 CLK_CON_DIV_DISPAUD_DECON_VCLK,
813 CLK_CON_DIV_DISPAUD_DECON_ECLK,
814 CLK_CON_DIV_DISPAUD_MI2S,
815 CLK_CON_DIV_DISPAUD_MIXER,
816 CLK_CON_GAT_DISPAUD_BUS,
817 CLK_CON_GAT_DISPAUD_BUS_DISP,
818 CLK_CON_GAT_DISPAUD_BUS_PPMU,
819 CLK_CON_GAT_DISPAUD_APB_AUD,
820 CLK_CON_GAT_DISPAUD_APB_AUD_AMP,
821 CLK_CON_GAT_DISPAUD_APB_DISP,
822 CLK_CON_GAT_DISPAUD_DECON_VCLK,
823 CLK_CON_GAT_DISPAUD_DECON_ECLK,
824 CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI,
825 CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI,
826 CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK,
827 CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S,
828 CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN,
829 CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK,
830 CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN,
831 };
832
833 static const struct samsung_fixed_rate_clock dispaud_fixed_clks[] __initconst = {
834 FRATE(0, "frat_dispaud_audiocdclk0", NULL, 0, 100000000),
835 FRATE(0, "frat_dispaud_mixer_bclk_bt", NULL, 0, 12500000),
836 FRATE(0, "frat_dispaud_mixer_bclk_cp", NULL, 0, 12500000),
837 FRATE(0, "frat_dispaud_mixer_bclk_fm", NULL, 0, 12500000),
838 FRATE(0, "frat_dispaud_mixer_sclk_ap", NULL, 0, 12500000),
839 FRATE(0, "frat_dispaud_mipiphy_rxclkesc0", NULL, 0, 188000000),
840 FRATE(0, "frat_dispaud_mipiphy_txbyteclkhs", NULL, 0, 188000000),
841 };
842
843 static const struct samsung_pll_clock dispaud_pll_clks[] __initconst = {
844 PLL(pll_1417x, CLK_FOUT_DISPAUD_AUD_PLL, "fout_dispaud_aud_pll",
845 "oscclk", PLL_LOCKTIME_DISPAUD_AUD_PLL, PLL_CON0_DISPAUD_AUD_PLL,
846 NULL),
847 PLL(pll_1417x, CLK_FOUT_DISPAUD_PLL, "fout_dispaud_pll", "oscclk",
848 PLL_LOCKTIME_DISPAUD_PLL, PLL_CON0_DISPAUD_PLL, NULL),
849 };
850
851 /* List of parent clocks for muxes in CMU_DISPAUD */
852 PNAME(mout_dispaud_bus_user_p) = { "oscclk", "gout_mif_cmu_dispaud_bus" };
853 PNAME(mout_dispaud_decon_eclk_user_p) = { "oscclk",
854 "gout_mif_cmu_dispaud_decon_eclk" };
855 PNAME(mout_dispaud_decon_vclk_user_p) = { "oscclk",
856 "gout_mif_cmu_dispaud_decon_vclk" };
857 PNAME(mout_dispaud_decon_eclk_p) = { "gout_dispaud_mux_decon_eclk_user",
858 "gout_dispaud_mux_pll_con" };
859 PNAME(mout_dispaud_decon_vclk_p) = { "gout_dispaud_mux_decon_vclk_user",
860 "gout_dispaud_mux_pll_con" };
861 PNAME(mout_dispaud_mi2s_p) = { "gout_dispaud_mux_aud_pll_con",
862 "frat_dispaud_audiocdclk0" };
863
864 static const struct samsung_mux_clock dispaud_mux_clks[] __initconst = {
865 MUX(CLK_MOUT_DISPAUD_BUS_USER, "mout_dispaud_bus_user",
866 mout_dispaud_bus_user_p, CLK_CON_MUX_DISPAUD_BUS_USER, 12, 1),
867 MUX(CLK_MOUT_DISPAUD_DECON_ECLK_USER, "mout_dispaud_decon_eclk_user",
868 mout_dispaud_decon_eclk_user_p, CLK_CON_MUX_DISPAUD_DECON_ECLK_USER,
869 12, 1),
870 MUX(CLK_MOUT_DISPAUD_DECON_VCLK_USER, "mout_dispaud_decon_vclk_user",
871 mout_dispaud_decon_vclk_user_p, CLK_CON_MUX_DISPAUD_DECON_VCLK_USER,
872 12, 1),
873 MUX(CLK_MOUT_DISPAUD_DECON_ECLK, "mout_dispaud_decon_eclk",
874 mout_dispaud_decon_eclk_p, CLK_CON_MUX_DISPAUD_DECON_ECLK, 12, 1),
875 MUX(CLK_MOUT_DISPAUD_DECON_VCLK, "mout_dispaud_decon_vclk",
876 mout_dispaud_decon_vclk_p, CLK_CON_MUX_DISPAUD_DECON_VCLK, 12, 1),
877 MUX(CLK_MOUT_DISPAUD_MI2S, "mout_dispaud_mi2s", mout_dispaud_mi2s_p,
878 CLK_CON_MUX_DISPAUD_MI2S, 12, 1),
879 };
880
881 static const struct samsung_div_clock dispaud_div_clks[] __initconst = {
882 DIV(CLK_DOUT_DISPAUD_APB, "dout_dispaud_apb",
883 "gout_dispaud_mux_bus_user", CLK_CON_DIV_DISPAUD_APB, 0, 2),
884 DIV(CLK_DOUT_DISPAUD_DECON_ECLK, "dout_dispaud_decon_eclk",
885 "gout_dispaud_mux_decon_eclk", CLK_CON_DIV_DISPAUD_DECON_ECLK, 0, 3),
886 DIV(CLK_DOUT_DISPAUD_DECON_VCLK, "dout_dispaud_decon_vclk",
887 "gout_dispaud_mux_decon_vclk", CLK_CON_DIV_DISPAUD_DECON_VCLK, 0, 3),
888 DIV(CLK_DOUT_DISPAUD_MI2S, "dout_dispaud_mi2s", "gout_dispaud_mux_mi2s",
889 CLK_CON_DIV_DISPAUD_MI2S, 0, 4),
890 DIV(CLK_DOUT_DISPAUD_MIXER, "dout_dispaud_mixer",
891 "gout_dispaud_mux_aud_pll_con", CLK_CON_DIV_DISPAUD_MIXER, 0, 4),
892 };
893
894 static const struct samsung_gate_clock dispaud_gate_clks[] __initconst = {
895 GATE(CLK_GOUT_DISPAUD_BUS, "gout_dispaud_bus",
896 "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS, 0,
897 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
898 GATE(CLK_GOUT_DISPAUD_BUS_DISP, "gout_dispaud_bus_disp",
899 "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS_DISP, 2,
900 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
901 GATE(CLK_GOUT_DISPAUD_BUS_PPMU, "gout_dispaud_bus_ppmu",
902 "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS_PPMU, 3,
903 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
904 GATE(CLK_GOUT_DISPAUD_APB_AUD, "gout_dispaud_apb_aud",
905 "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_AUD, 2,
906 CLK_SET_RATE_PARENT, 0),
907 GATE(CLK_GOUT_DISPAUD_APB_AUD_AMP, "gout_dispaud_apb_aud_amp",
908 "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_AUD_AMP, 3,
909 CLK_SET_RATE_PARENT, 0),
910 GATE(CLK_GOUT_DISPAUD_APB_DISP, "gout_dispaud_apb_disp",
911 "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_DISP, 1,
912 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
913 GATE(CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN,
914 "gout_dispaud_con_aud_i2s_bclk_bt_in",
915 "frat_dispaud_mixer_bclk_bt",
916 CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN, 0, CLK_SET_RATE_PARENT,
917 0),
918 GATE(CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN,
919 "gout_dispaud_con_aud_i2s_bclk_fm_in",
920 "frat_dispaud_mixer_bclk_fm",
921 CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN, 0, CLK_SET_RATE_PARENT,
922 0),
923 GATE(CLK_GOUT_DISPAUD_CON_CP2AUD_BCK, "gout_dispaud_con_cp2aud_bck",
924 "frat_dispaud_mixer_bclk_cp", CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK,
925 0, CLK_SET_RATE_PARENT, 0),
926 GATE(CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S,
927 "gout_dispaud_con_ext2aud_bck_gpio_i2s",
928 "frat_dispaud_mixer_sclk_ap",
929 CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S, 0,
930 CLK_SET_RATE_PARENT, 0),
931 GATE(CLK_GOUT_DISPAUD_DECON_ECLK, "gout_dispaud_decon_eclk",
932 "dout_dispaud_decon_eclk", CLK_CON_GAT_DISPAUD_DECON_ECLK, 0,
933 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
934 GATE(CLK_GOUT_DISPAUD_DECON_VCLK, "gout_dispaud_decon_vclk",
935 "dout_dispaud_decon_vclk", CLK_CON_GAT_DISPAUD_DECON_VCLK, 0,
936 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
937 GATE(CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI,
938 "gout_dispaud_mi2s_amp_i2scodclki", "dout_dispaud_mi2s",
939 CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI, 1, CLK_SET_RATE_PARENT, 0),
940 GATE(CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI,
941 "gout_dispaud_mi2s_aud_i2scodclki", "dout_dispaud_mi2s",
942 CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI, 0, CLK_SET_RATE_PARENT, 0),
943 GATE(CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK, "gout_dispaud_mixer_aud_sysclk",
944 "dout_dispaud_mixer", CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK, 0,
945 CLK_SET_RATE_PARENT, 0),
946 GATE(CLK_GOUT_DISPAUD_MUX_AUD_PLL, "gout_dispaud_mux_aud_pll",
947 "gout_dispaud_mux_aud_pll_con", CLK_CON_GAT_DISPAUD_MUX_AUD_PLL,
948 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
949 GATE(CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON, "gout_dispaud_mux_aud_pll_con",
950 "fout_dispaud_aud_pll", CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON, 12,
951 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
952 GATE(CLK_GOUT_DISPAUD_MUX_BUS_USER, "gout_dispaud_mux_bus_user",
953 "mout_dispaud_bus_user", CLK_CON_GAT_DISPAUD_MUX_BUS_USER, 21,
954 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
955 GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER,
956 "gout_dispaud_mux_decon_eclk_user", "mout_dispaud_decon_eclk_user",
957 CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER, 21, CLK_IS_CRITICAL |
958 CLK_SET_RATE_PARENT, 0),
959 GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER,
960 "gout_dispaud_mux_decon_vclk_user", "mout_dispaud_decon_vclk_user",
961 CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER, 21, CLK_IS_CRITICAL |
962 CLK_SET_RATE_PARENT, 0),
963 GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER,
964 "gout_dispaud_mux_mipiphy_rxclkesc0_user",
965 "gout_dispaud_mux_mipiphy_rxclkesc0_user_con",
966 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER, 21, CLK_IS_CRITICAL
967 | CLK_SET_RATE_PARENT, 0),
968 GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON,
969 "gout_dispaud_mux_mipiphy_rxclkesc0_user_con",
970 "frat_dispaud_mipiphy_rxclkesc0",
971 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON, 12,
972 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
973 GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER,
974 "gout_dispaud_mux_mipiphy_txbyteclkhs_user",
975 "gout_dispaud_mux_mipiphy_txbyteclkhs_user_con",
976 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER, 21,
977 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
978 GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON,
979 "gout_dispaud_mux_mipiphy_txbyteclkhs_user_con",
980 "frat_dispaud_mipiphy_txbyteclkhs",
981 CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON, 12,
982 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
983 GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK, "gout_dispaud_mux_decon_eclk",
984 "mout_dispaud_decon_eclk", CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK, 21,
985 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
986 GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK, "gout_dispaud_mux_decon_vclk",
987 "mout_dispaud_decon_vclk", CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK, 21,
988 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
989 GATE(CLK_GOUT_DISPAUD_MUX_MI2S, "gout_dispaud_mux_mi2s",
990 "mout_dispaud_mi2s", CLK_CON_GAT_DISPAUD_MUX_MI2S, 21,
991 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
992 GATE(CLK_GOUT_DISPAUD_MUX_PLL, "gout_dispaud_mux_pll",
993 "gout_dispaud_mux_pll_con", CLK_CON_GAT_DISPAUD_MUX_PLL, 21,
994 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
995 GATE(CLK_GOUT_DISPAUD_MUX_PLL_CON, "gout_dispaud_mux_pll_con",
996 "fout_dispaud_pll", CLK_CON_GAT_DISPAUD_MUX_PLL_CON, 12,
997 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
998 };
999
1000 static const struct samsung_cmu_info dispaud_cmu_info __initconst = {
1001 .fixed_clks = dispaud_fixed_clks,
1002 .nr_fixed_clks = ARRAY_SIZE(dispaud_fixed_clks),
1003 .pll_clks = dispaud_pll_clks,
1004 .nr_pll_clks = ARRAY_SIZE(dispaud_pll_clks),
1005 .mux_clks = dispaud_mux_clks,
1006 .nr_mux_clks = ARRAY_SIZE(dispaud_mux_clks),
1007 .div_clks = dispaud_div_clks,
1008 .nr_div_clks = ARRAY_SIZE(dispaud_div_clks),
1009 .gate_clks = dispaud_gate_clks,
1010 .nr_gate_clks = ARRAY_SIZE(dispaud_gate_clks),
1011 .clk_regs = dispaud_clk_regs,
1012 .nr_clk_regs = ARRAY_SIZE(dispaud_clk_regs),
1013 .nr_clk_ids = DISPAUD_NR_CLK,
1014 };
1015
1016 /*
1017 * Register offsets for CMU_FSYS (0x13730000)
1018 */
1019 #define PLL_LOCKTIME_FSYS_USB_PLL 0x0000
1020 #define PLL_CON0_FSYS_USB_PLL 0x0100
1021 #define CLK_CON_GAT_FSYS_MUX_USB_PLL 0x0200
1022 #define CLK_CON_GAT_FSYS_MUX_USB_PLL_CON 0x0200
1023 #define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 0x0230
1024 #define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 0x0230
1025 #define CLK_CON_GAT_FSYS_BUSP3_HCLK 0x0804
1026 #define CLK_CON_GAT_FSYS_MMC0_ACLK 0x0804
1027 #define CLK_CON_GAT_FSYS_MMC1_ACLK 0x0804
1028 #define CLK_CON_GAT_FSYS_MMC2_ACLK 0x0804
1029 #define CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0 0x0804
1030 #define CLK_CON_GAT_FSYS_PPMU_ACLK 0x0804
1031 #define CLK_CON_GAT_FSYS_PPMU_PCLK 0x0804
1032 #define CLK_CON_GAT_FSYS_SROMC_HCLK 0x0804
1033 #define CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK 0x0804
1034 #define CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD 0x0804
1035 #define CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL 0x0804
1036 #define CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK 0x0828
1037
1038 static const unsigned long fsys_clk_regs[] __initconst = {
1039 PLL_LOCKTIME_FSYS_USB_PLL,
1040 PLL_CON0_FSYS_USB_PLL,
1041 CLK_CON_GAT_FSYS_MUX_USB_PLL,
1042 CLK_CON_GAT_FSYS_MUX_USB_PLL_CON,
1043 CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER,
1044 CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON,
1045 CLK_CON_GAT_FSYS_BUSP3_HCLK,
1046 CLK_CON_GAT_FSYS_MMC0_ACLK,
1047 CLK_CON_GAT_FSYS_MMC1_ACLK,
1048 CLK_CON_GAT_FSYS_MMC2_ACLK,
1049 CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0,
1050 CLK_CON_GAT_FSYS_PPMU_ACLK,
1051 CLK_CON_GAT_FSYS_PPMU_PCLK,
1052 CLK_CON_GAT_FSYS_SROMC_HCLK,
1053 CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK,
1054 CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD,
1055 CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL,
1056 CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK,
1057 };
1058
1059 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
1060 FRATE(0, "frat_fsys_usb20drd_phyclock", NULL, 0, 60000000),
1061 };
1062
1063 static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
1064 PLL(pll_1417x, CLK_FOUT_FSYS_USB_PLL, "fout_fsys_usb_pll", "oscclk",
1065 PLL_LOCKTIME_FSYS_USB_PLL, PLL_CON0_FSYS_USB_PLL, NULL),
1066 };
1067
1068 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
1069 GATE(CLK_GOUT_FSYS_BUSP3_HCLK, "gout_fsys_busp3_hclk",
1070 "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_BUSP3_HCLK, 2,
1071 CLK_SET_RATE_PARENT, 0),
1072 GATE(CLK_GOUT_FSYS_MMC0_ACLK, "gout_fsys_mmc0_aclk",
1073 "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC0_ACLK, 8,
1074 CLK_SET_RATE_PARENT, 0),
1075 GATE(CLK_GOUT_FSYS_MMC1_ACLK, "gout_fsys_mmc1_aclk",
1076 "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC1_ACLK, 9,
1077 CLK_SET_RATE_PARENT, 0),
1078 GATE(CLK_GOUT_FSYS_MMC2_ACLK, "gout_fsys_mmc2_aclk",
1079 "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC2_ACLK, 10,
1080 CLK_SET_RATE_PARENT, 0),
1081 GATE(CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0, "gout_fsys_pdma0_aclk_pdma0",
1082 "gout_fsys_upsizer_bus1_aclk", CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0,
1083 7, CLK_SET_RATE_PARENT, 0),
1084 GATE(CLK_GOUT_FSYS_PPMU_ACLK, "gout_fsys_ppmu_aclk",
1085 "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_PPMU_ACLK, 17,
1086 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1087 GATE(CLK_GOUT_FSYS_PPMU_PCLK, "gout_fsys_ppmu_pclk",
1088 "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_PPMU_PCLK, 18,
1089 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1090 GATE(CLK_GOUT_FSYS_SROMC_HCLK, "gout_fsys_sromc_hclk",
1091 "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_SROMC_HCLK, 6,
1092 CLK_SET_RATE_PARENT, 0),
1093 GATE(CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK, "gout_fsys_upsizer_bus1_aclk",
1094 "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK, 12,
1095 CLK_SET_RATE_PARENT, 0),
1096 GATE(CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD, "gout_fsys_usb20drd_aclk_hsdrd",
1097 "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD, 20,
1098 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1099 GATE(CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL,
1100 "gout_fsys_usb20drd_hclk_usb20_ctrl", "gout_fsys_busp3_hclk",
1101 CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL, 21, CLK_IS_CRITICAL |
1102 CLK_SET_RATE_PARENT, 0),
1103 GATE(CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK,
1104 "gout_fsys_usb20drd_hsdrd_ref_clk",
1105 "gout_mif_cmu_fsys_usb20drd_refclk",
1106 CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK, 0, CLK_SET_RATE_PARENT, 0),
1107 GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER,
1108 "gout_fsys_mux_usb20drd_phyclock_user",
1109 "gout_fsys_mux_usb20drd_phyclock_user_con",
1110 CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, 21, CLK_IS_CRITICAL |
1111 CLK_SET_RATE_PARENT, 0),
1112 GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON,
1113 "gout_fsys_mux_usb20drd_phyclock_user_con",
1114 "frat_fsys_usb20drd_phyclock",
1115 CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, 12,
1116 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1117 GATE(CLK_GOUT_FSYS_MUX_USB_PLL, "gout_fsys_mux_usb_pll",
1118 "gout_fsys_mux_usb_pll_con", CLK_CON_GAT_FSYS_MUX_USB_PLL, 21,
1119 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1120 GATE(CLK_GOUT_FSYS_MUX_USB_PLL_CON, "gout_fsys_mux_usb_pll_con",
1121 "fout_fsys_usb_pll", CLK_CON_GAT_FSYS_MUX_USB_PLL_CON, 12,
1122 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1123 };
1124
1125 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
1126 .fixed_clks = fsys_fixed_clks,
1127 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
1128 .pll_clks = fsys_pll_clks,
1129 .nr_pll_clks = ARRAY_SIZE(fsys_pll_clks),
1130 .gate_clks = fsys_gate_clks,
1131 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
1132 .clk_regs = fsys_clk_regs,
1133 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
1134 .nr_clk_ids = FSYS_NR_CLK,
1135 };
1136
1137 /*
1138 * Register offsets for CMU_G3D (0x11460000)
1139 */
1140 #define PLL_LOCKTIME_G3D_PLL 0x0000
1141 #define PLL_CON0_G3D_PLL 0x0100
1142 #define CLK_CON_GAT_G3D_MUX_PLL 0x0200
1143 #define CLK_CON_GAT_G3D_MUX_PLL_CON 0x0200
1144 #define CLK_CON_GAT_G3D_MUX_SWITCH_USER 0x0204
1145 #define CLK_CON_MUX_G3D_SWITCH_USER 0x0204
1146 #define CLK_CON_GAT_G3D_MUX 0x0208
1147 #define CLK_CON_MUX_G3D 0x0208
1148 #define CLK_CON_DIV_G3D_BUS 0x0400
1149 #define CLK_CON_DIV_G3D_APB 0x0404
1150 #define CLK_CON_GAT_G3D_ASYNCS_D0_CLK 0x0804
1151 #define CLK_CON_GAT_G3D_ASYNC_PCLKM 0x0804
1152 #define CLK_CON_GAT_G3D_CLK 0x0804
1153 #define CLK_CON_GAT_G3D_PPMU_ACLK 0x0804
1154 #define CLK_CON_GAT_G3D_QE_ACLK 0x0804
1155 #define CLK_CON_GAT_G3D_PPMU_PCLK 0x0808
1156 #define CLK_CON_GAT_G3D_QE_PCLK 0x0808
1157 #define CLK_CON_GAT_G3D_SYSREG_PCLK 0x0808
1158
1159 static const unsigned long g3d_clk_regs[] __initconst = {
1160 PLL_LOCKTIME_G3D_PLL,
1161 PLL_CON0_G3D_PLL,
1162 CLK_CON_GAT_G3D_MUX_PLL,
1163 CLK_CON_GAT_G3D_MUX_PLL_CON,
1164 CLK_CON_GAT_G3D_MUX_SWITCH_USER,
1165 CLK_CON_MUX_G3D_SWITCH_USER,
1166 CLK_CON_GAT_G3D_MUX,
1167 CLK_CON_MUX_G3D,
1168 CLK_CON_DIV_G3D_BUS,
1169 CLK_CON_DIV_G3D_APB,
1170 CLK_CON_GAT_G3D_ASYNCS_D0_CLK,
1171 CLK_CON_GAT_G3D_ASYNC_PCLKM,
1172 CLK_CON_GAT_G3D_CLK,
1173 CLK_CON_GAT_G3D_PPMU_ACLK,
1174 CLK_CON_GAT_G3D_QE_ACLK,
1175 CLK_CON_GAT_G3D_PPMU_PCLK,
1176 CLK_CON_GAT_G3D_QE_PCLK,
1177 CLK_CON_GAT_G3D_SYSREG_PCLK,
1178 };
1179
1180 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
1181 PLL(pll_1417x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
1182 PLL_LOCKTIME_G3D_PLL, PLL_CON0_G3D_PLL, NULL),
1183 };
1184
1185 /* List of parent clocks for muxes in CMU_G3D */
1186 PNAME(mout_g3d_switch_user_p) = { "oscclk", "gout_mif_cmu_g3d_switch" };
1187 PNAME(mout_g3d_p) = { "gout_g3d_mux_pll_con",
1188 "gout_g3d_mux_switch_user" };
1189
1190 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
1191 MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
1192 mout_g3d_switch_user_p, CLK_CON_MUX_G3D_SWITCH_USER, 12, 1),
1193 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, CLK_CON_MUX_G3D, 12, 1),
1194 };
1195
1196 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
1197 DIV(CLK_DOUT_G3D_APB, "dout_g3d_apb", "dout_g3d_bus",
1198 CLK_CON_DIV_G3D_APB, 0, 3),
1199 DIV(CLK_DOUT_G3D_BUS, "dout_g3d_bus", "gout_g3d_mux",
1200 CLK_CON_DIV_G3D_BUS, 0, 3),
1201 };
1202
1203 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
1204 GATE(CLK_GOUT_G3D_ASYNCS_D0_CLK, "gout_g3d_asyncs_d0_clk",
1205 "dout_g3d_bus", CLK_CON_GAT_G3D_ASYNCS_D0_CLK, 1, CLK_IS_CRITICAL |
1206 CLK_SET_RATE_PARENT, 0),
1207 GATE(CLK_GOUT_G3D_ASYNC_PCLKM, "gout_g3d_async_pclkm", "dout_g3d_bus",
1208 CLK_CON_GAT_G3D_ASYNC_PCLKM, 0, CLK_IS_CRITICAL |
1209 CLK_SET_RATE_PARENT, 0),
1210 GATE(CLK_GOUT_G3D_CLK, "gout_g3d_clk", "dout_g3d_bus",
1211 CLK_CON_GAT_G3D_CLK, 6, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1212 GATE(CLK_GOUT_G3D_PPMU_ACLK, "gout_g3d_ppmu_aclk", "dout_g3d_bus",
1213 CLK_CON_GAT_G3D_PPMU_ACLK, 7, CLK_IS_CRITICAL |
1214 CLK_SET_RATE_PARENT, 0),
1215 GATE(CLK_GOUT_G3D_PPMU_PCLK, "gout_g3d_ppmu_pclk", "dout_g3d_apb",
1216 CLK_CON_GAT_G3D_PPMU_PCLK, 4, CLK_IS_CRITICAL |
1217 CLK_SET_RATE_PARENT, 0),
1218 GATE(CLK_GOUT_G3D_QE_ACLK, "gout_g3d_qe_aclk", "dout_g3d_bus",
1219 CLK_CON_GAT_G3D_QE_ACLK, 8, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1220 0),
1221 GATE(CLK_GOUT_G3D_QE_PCLK, "gout_g3d_qe_pclk", "dout_g3d_apb",
1222 CLK_CON_GAT_G3D_QE_PCLK, 5, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1223 0),
1224 GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_apb",
1225 CLK_CON_GAT_G3D_SYSREG_PCLK, 6, CLK_SET_RATE_PARENT, 0),
1226 GATE(CLK_GOUT_G3D_MUX_SWITCH_USER, "gout_g3d_mux_switch_user",
1227 "mout_g3d_switch_user", CLK_CON_GAT_G3D_MUX_SWITCH_USER, 21,
1228 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1229 GATE(CLK_GOUT_G3D_MUX, "gout_g3d_mux", "mout_g3d", CLK_CON_GAT_G3D_MUX,
1230 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1231 GATE(CLK_GOUT_G3D_MUX_PLL, "gout_g3d_mux_pll", "gout_g3d_mux_pll_con",
1232 CLK_CON_GAT_G3D_MUX_PLL, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1233 0),
1234 GATE(CLK_GOUT_G3D_MUX_PLL_CON, "gout_g3d_mux_pll_con", "fout_g3d_pll",
1235 CLK_CON_GAT_G3D_MUX_PLL_CON, 12, CLK_IS_CRITICAL |
1236 CLK_SET_RATE_PARENT, 0),
1237 };
1238
1239 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
1240 .pll_clks = g3d_pll_clks,
1241 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
1242 .mux_clks = g3d_mux_clks,
1243 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
1244 .div_clks = g3d_div_clks,
1245 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
1246 .gate_clks = g3d_gate_clks,
1247 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1248 .clk_regs = g3d_clk_regs,
1249 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
1250 .nr_clk_ids = G3D_NR_CLK,
1251 };
1252
1253 /*
1254 * Register offsets for CMU_ISP (0x144d0000)
1255 */
1256 #define PLL_LOCKTIME_ISP_PLL 0x0000
1257 #define PLL_CON0_ISP_PLL 0x0100
1258 #define CLK_CON_GAT_ISP_MUX_PLL 0x0200
1259 #define CLK_CON_GAT_ISP_MUX_PLL_CON 0x0200
1260 #define CLK_CON_GAT_ISP_MUX_VRA_USER 0x0210
1261 #define CLK_CON_MUX_ISP_VRA_USER 0x0210
1262 #define CLK_CON_GAT_ISP_MUX_CAM_USER 0x0214
1263 #define CLK_CON_MUX_ISP_CAM_USER 0x0214
1264 #define CLK_CON_GAT_ISP_MUX_USER 0x0218
1265 #define CLK_CON_MUX_ISP_USER 0x0218
1266 #define CLK_CON_GAT_ISP_MUX_VRA 0x0220
1267 #define CLK_CON_MUX_ISP_VRA 0x0220
1268 #define CLK_CON_GAT_ISP_MUX_CAM 0x0224
1269 #define CLK_CON_MUX_ISP_CAM 0x0224
1270 #define CLK_CON_GAT_ISP_MUX_ISP 0x0228
1271 #define CLK_CON_MUX_ISP_ISP 0x0228
1272 #define CLK_CON_GAT_ISP_MUX_ISPD 0x022c
1273 #define CLK_CON_MUX_ISP_ISPD 0x022c
1274 #define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 0x0230
1275 #define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 0x0230
1276 #define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 0x0234
1277 #define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 0x0234
1278 #define CLK_CON_DIV_ISP_APB 0x0400
1279 #define CLK_CON_DIV_ISP_CAM_HALF 0x0404
1280 #define CLK_CON_GAT_ISP_VRA 0x0810
1281 #define CLK_CON_GAT_ISP_ISPD 0x0818
1282 #define CLK_CON_GAT_ISP_ISPD_PPMU 0x0818
1283 #define CLK_CON_GAT_ISP_CAM 0x081c
1284 #define CLK_CON_GAT_ISP_CAM_HALF 0x0820
1285
1286 static const unsigned long isp_clk_regs[] __initconst = {
1287 PLL_LOCKTIME_ISP_PLL,
1288 PLL_CON0_ISP_PLL,
1289 CLK_CON_GAT_ISP_MUX_PLL,
1290 CLK_CON_GAT_ISP_MUX_PLL_CON,
1291 CLK_CON_GAT_ISP_MUX_VRA_USER,
1292 CLK_CON_MUX_ISP_VRA_USER,
1293 CLK_CON_GAT_ISP_MUX_CAM_USER,
1294 CLK_CON_MUX_ISP_CAM_USER,
1295 CLK_CON_GAT_ISP_MUX_USER,
1296 CLK_CON_MUX_ISP_USER,
1297 CLK_CON_GAT_ISP_MUX_VRA,
1298 CLK_CON_MUX_ISP_VRA,
1299 CLK_CON_GAT_ISP_MUX_CAM,
1300 CLK_CON_MUX_ISP_CAM,
1301 CLK_CON_GAT_ISP_MUX_ISP,
1302 CLK_CON_MUX_ISP_ISP,
1303 CLK_CON_GAT_ISP_MUX_ISPD,
1304 CLK_CON_MUX_ISP_ISPD,
1305 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER,
1306 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON,
1307 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER,
1308 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON,
1309 CLK_CON_DIV_ISP_APB,
1310 CLK_CON_DIV_ISP_CAM_HALF,
1311 CLK_CON_GAT_ISP_VRA,
1312 CLK_CON_GAT_ISP_ISPD,
1313 CLK_CON_GAT_ISP_ISPD_PPMU,
1314 CLK_CON_GAT_ISP_CAM,
1315 CLK_CON_GAT_ISP_CAM_HALF,
1316 };
1317
1318 static const struct samsung_fixed_rate_clock isp_fixed_clks[] __initconst = {
1319 FRATE(0, "frat_isp_rxbyteclkhs0_sensor0", NULL, 0, 188000000),
1320 FRATE(0, "frat_isp_rxbyteclkhs0_sensor1", NULL, 0, 188000000),
1321 };
1322
1323 static const struct samsung_pll_clock isp_pll_clks[] __initconst = {
1324 PLL(pll_1417x, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
1325 PLL_LOCKTIME_ISP_PLL, PLL_CON0_ISP_PLL, NULL),
1326 };
1327
1328 /* List of parent clocks for muxes in CMU_ISP */
1329 PNAME(mout_isp_cam_user_p) = { "oscclk", "gout_mif_cmu_isp_cam" };
1330 PNAME(mout_isp_user_p) = { "oscclk", "gout_mif_cmu_isp_isp" };
1331 PNAME(mout_isp_vra_user_p) = { "oscclk", "gout_mif_cmu_isp_vra" };
1332 PNAME(mout_isp_cam_p) = { "gout_isp_mux_cam_user",
1333 "gout_isp_mux_pll_con" };
1334 PNAME(mout_isp_isp_p) = { "gout_isp_mux_user", "gout_isp_mux_pll_con" };
1335 PNAME(mout_isp_ispd_p) = { "gout_isp_mux_vra", "gout_isp_mux_cam" };
1336 PNAME(mout_isp_vra_p) = { "gout_isp_mux_vra_user",
1337 "gout_isp_mux_pll_con" };
1338
1339 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
1340 MUX(CLK_MOUT_ISP_CAM_USER, "mout_isp_cam_user", mout_isp_cam_user_p,
1341 CLK_CON_MUX_ISP_CAM_USER, 12, 1),
1342 MUX(CLK_MOUT_ISP_USER, "mout_isp_user", mout_isp_user_p,
1343 CLK_CON_MUX_ISP_USER, 12, 1),
1344 MUX(CLK_MOUT_ISP_VRA_USER, "mout_isp_vra_user", mout_isp_vra_user_p,
1345 CLK_CON_MUX_ISP_VRA_USER, 12, 1),
1346 MUX(CLK_MOUT_ISP_CAM, "mout_isp_cam", mout_isp_cam_p,
1347 CLK_CON_MUX_ISP_CAM, 12, 1),
1348 MUX(CLK_MOUT_ISP_ISP, "mout_isp_isp", mout_isp_isp_p,
1349 CLK_CON_MUX_ISP_ISP, 12, 1),
1350 MUX(CLK_MOUT_ISP_ISPD, "mout_isp_ispd", mout_isp_ispd_p,
1351 CLK_CON_MUX_ISP_ISPD, 12, 1),
1352 MUX(CLK_MOUT_ISP_VRA, "mout_isp_vra", mout_isp_vra_p,
1353 CLK_CON_MUX_ISP_VRA, 12, 1),
1354 };
1355
1356 static const struct samsung_div_clock isp_div_clks[] __initconst = {
1357 DIV(CLK_DOUT_ISP_APB, "dout_isp_apb", "gout_isp_mux_vra",
1358 CLK_CON_DIV_ISP_APB, 0, 2),
1359 DIV(CLK_DOUT_ISP_CAM_HALF, "dout_isp_cam_half", "gout_isp_mux_cam",
1360 CLK_CON_DIV_ISP_CAM_HALF, 0, 2),
1361 };
1362
1363 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
1364 GATE(CLK_GOUT_ISP_CAM, "gout_isp_cam", "gout_isp_mux_cam",
1365 CLK_CON_GAT_ISP_CAM, 0, CLK_SET_RATE_PARENT, 0),
1366 GATE(CLK_GOUT_ISP_CAM_HALF, "gout_isp_cam_half", "dout_isp_cam_half",
1367 CLK_CON_GAT_ISP_CAM_HALF, 0, CLK_SET_RATE_PARENT, 0),
1368 GATE(CLK_GOUT_ISP_ISPD, "gout_isp_ispd", "gout_isp_mux_ispd",
1369 CLK_CON_GAT_ISP_ISPD, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1370 GATE(CLK_GOUT_ISP_ISPD_PPMU, "gout_isp_ispd_ppmu", "gout_isp_mux_ispd",
1371 CLK_CON_GAT_ISP_ISPD_PPMU, 1, CLK_IS_CRITICAL |
1372 CLK_SET_RATE_PARENT, 0),
1373 GATE(CLK_GOUT_ISP_VRA, "gout_isp_vra", "gout_isp_mux_vra",
1374 CLK_CON_GAT_ISP_VRA, 0, CLK_SET_RATE_PARENT, 0),
1375 GATE(CLK_GOUT_ISP_MUX_CAM_USER, "gout_isp_mux_cam_user",
1376 "mout_isp_cam_user", CLK_CON_GAT_ISP_MUX_CAM_USER, 21,
1377 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1378 GATE(CLK_GOUT_ISP_MUX_USER, "gout_isp_mux_user", "mout_isp_user",
1379 CLK_CON_GAT_ISP_MUX_USER, 21, CLK_IS_CRITICAL |
1380 CLK_SET_RATE_PARENT, 0),
1381 GATE(CLK_GOUT_ISP_MUX_VRA_USER, "gout_isp_mux_vra_user",
1382 "mout_isp_vra_user", CLK_CON_GAT_ISP_MUX_VRA_USER, 21,
1383 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1384 GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER,
1385 "gout_isp_mux_rxbyteclkhs0_sensor1_user",
1386 "gout_isp_mux_rxbyteclkhs0_sensor1_user_con",
1387 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER, 21, CLK_IS_CRITICAL
1388 | CLK_SET_RATE_PARENT, 0),
1389 GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON,
1390 "gout_isp_mux_rxbyteclkhs0_sensor1_user_con",
1391 "frat_isp_rxbyteclkhs0_sensor1",
1392 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON, 12,
1393 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1394 GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER,
1395 "gout_isp_mux_rxbyteclkhs0_sensor0_user",
1396 "gout_isp_mux_rxbyteclkhs0_sensor0_user_con",
1397 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER, 21, CLK_IS_CRITICAL
1398 | CLK_SET_RATE_PARENT, 0),
1399 GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON,
1400 "gout_isp_mux_rxbyteclkhs0_sensor0_user_con",
1401 "frat_isp_rxbyteclkhs0_sensor0",
1402 CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON, 12,
1403 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1404 GATE(CLK_GOUT_ISP_MUX_CAM, "gout_isp_mux_cam", "mout_isp_cam",
1405 CLK_CON_GAT_ISP_MUX_CAM, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1406 0),
1407 GATE(CLK_GOUT_ISP_MUX_ISP, "gout_isp_mux_isp", "mout_isp_isp",
1408 CLK_CON_GAT_ISP_MUX_ISP, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1409 0),
1410 GATE(CLK_GOUT_ISP_MUX_ISPD, "gout_isp_mux_ispd", "mout_isp_ispd",
1411 CLK_CON_GAT_ISP_MUX_ISPD, 21, CLK_IS_CRITICAL |
1412 CLK_SET_RATE_PARENT, 0),
1413 GATE(CLK_GOUT_ISP_MUX_VRA, "gout_isp_mux_vra", "mout_isp_vra",
1414 CLK_CON_GAT_ISP_MUX_VRA, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1415 0),
1416 GATE(CLK_GOUT_ISP_MUX_PLL, "gout_isp_mux_pll", "gout_isp_mux_pll_con",
1417 CLK_CON_GAT_ISP_MUX_PLL, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1418 0),
1419 GATE(CLK_GOUT_ISP_MUX_PLL_CON, "gout_isp_mux_pll_con", "fout_isp_pll",
1420 CLK_CON_GAT_ISP_MUX_PLL_CON, 12, CLK_IS_CRITICAL |
1421 CLK_SET_RATE_PARENT, 0),
1422 };
1423
1424 static const struct samsung_cmu_info isp_cmu_info __initconst = {
1425 .fixed_clks = isp_fixed_clks,
1426 .nr_fixed_clks = ARRAY_SIZE(isp_fixed_clks),
1427 .pll_clks = isp_pll_clks,
1428 .nr_pll_clks = ARRAY_SIZE(isp_pll_clks),
1429 .mux_clks = isp_mux_clks,
1430 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
1431 .div_clks = isp_div_clks,
1432 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
1433 .gate_clks = isp_gate_clks,
1434 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
1435 .clk_regs = isp_clk_regs,
1436 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
1437 .nr_clk_ids = ISP_NR_CLK,
1438 };
1439
1440 /*
1441 * Register offsets for CMU_MFCMSCL (0x12cb0000)
1442 */
1443 #define CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER 0x0200
1444 #define CLK_CON_MUX_MFCMSCL_MSCL_USER 0x0200
1445 #define CLK_CON_GAT_MFCMSCL_MUX_MFC_USER 0x0204
1446 #define CLK_CON_MUX_MFCMSCL_MFC_USER 0x0204
1447 #define CLK_CON_DIV_MFCMSCL_APB 0x0400
1448 #define CLK_CON_GAT_MFCMSCL_MSCL 0x0804
1449 #define CLK_CON_GAT_MFCMSCL_MSCL_BI 0x0804
1450 #define CLK_CON_GAT_MFCMSCL_MSCL_D 0x0804
1451 #define CLK_CON_GAT_MFCMSCL_MSCL_JPEG 0x0804
1452 #define CLK_CON_GAT_MFCMSCL_MSCL_POLY 0x0804
1453 #define CLK_CON_GAT_MFCMSCL_MSCL_PPMU 0x0804
1454 #define CLK_CON_GAT_MFCMSCL_MFC 0x0808
1455
1456 static const unsigned long mfcmscl_clk_regs[] __initconst = {
1457 CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER,
1458 CLK_CON_MUX_MFCMSCL_MSCL_USER,
1459 CLK_CON_GAT_MFCMSCL_MUX_MFC_USER,
1460 CLK_CON_MUX_MFCMSCL_MFC_USER,
1461 CLK_CON_DIV_MFCMSCL_APB,
1462 CLK_CON_GAT_MFCMSCL_MSCL,
1463 CLK_CON_GAT_MFCMSCL_MSCL_BI,
1464 CLK_CON_GAT_MFCMSCL_MSCL_D,
1465 CLK_CON_GAT_MFCMSCL_MSCL_JPEG,
1466 CLK_CON_GAT_MFCMSCL_MSCL_POLY,
1467 CLK_CON_GAT_MFCMSCL_MSCL_PPMU,
1468 CLK_CON_GAT_MFCMSCL_MFC,
1469 };
1470
1471 /* List of parent clocks for muxes in CMU_MFCMSCL */
1472 PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "gout_mif_cmu_mfcmscl_mfc" };
1473 PNAME(mout_mfcmscl_mscl_user_p) = { "oscclk", "gout_mif_cmu_mfcmscl_mscl" };
1474
1475 static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
1476 MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
1477 mout_mfcmscl_mfc_user_p, CLK_CON_MUX_MFCMSCL_MFC_USER, 12, 1),
1478 MUX(CLK_MOUT_MFCMSCL_MSCL_USER, "mout_mfcmscl_mscl_user",
1479 mout_mfcmscl_mscl_user_p, CLK_CON_MUX_MFCMSCL_MSCL_USER, 12, 1),
1480 };
1481
1482 static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
1483 DIV(CLK_DOUT_MFCMSCL_APB, "dout_mfcmscl_apb",
1484 "gout_mfcmscl_mux_mscl_user", CLK_CON_DIV_MFCMSCL_APB, 0, 2),
1485 };
1486
1487 static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
1488 GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc",
1489 "gout_mfcmscl_mux_mfc_user", CLK_CON_GAT_MFCMSCL_MFC, 0,
1490 CLK_SET_RATE_PARENT, 0),
1491 GATE(CLK_GOUT_MFCMSCL_MSCL, "gout_mfcmscl_mscl",
1492 "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL, 0,
1493 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1494 GATE(CLK_GOUT_MFCMSCL_MSCL_BI, "gout_mfcmscl_mscl_bi",
1495 "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_BI, 4,
1496 CLK_SET_RATE_PARENT, 0),
1497 GATE(CLK_GOUT_MFCMSCL_MSCL_D, "gout_mfcmscl_mscl_d",
1498 "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL_D, 1,
1499 CLK_SET_RATE_PARENT, 0),
1500 GATE(CLK_GOUT_MFCMSCL_MSCL_JPEG, "gout_mfcmscl_mscl_jpeg",
1501 "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_JPEG, 2,
1502 CLK_SET_RATE_PARENT, 0),
1503 GATE(CLK_GOUT_MFCMSCL_MSCL_POLY, "gout_mfcmscl_mscl_poly",
1504 "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_POLY, 3,
1505 CLK_SET_RATE_PARENT, 0),
1506 GATE(CLK_GOUT_MFCMSCL_MSCL_PPMU, "gout_mfcmscl_mscl_ppmu",
1507 "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL_PPMU, 5,
1508 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1509 GATE(CLK_GOUT_MFCMSCL_MUX_MFC_USER, "gout_mfcmscl_mux_mfc_user",
1510 "mout_mfcmscl_mfc_user", CLK_CON_GAT_MFCMSCL_MUX_MFC_USER, 21,
1511 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1512 GATE(CLK_GOUT_MFCMSCL_MUX_MSCL_USER, "gout_mfcmscl_mux_mscl_user",
1513 "mout_mfcmscl_mscl_user", CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER, 21,
1514 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1515 };
1516
1517 static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
1518 .mux_clks = mfcmscl_mux_clks,
1519 .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
1520 .div_clks = mfcmscl_div_clks,
1521 .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
1522 .gate_clks = mfcmscl_gate_clks,
1523 .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1524 .clk_regs = mfcmscl_clk_regs,
1525 .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
1526 .nr_clk_ids = MFCMSCL_NR_CLK,
1527 };
1528
1529 /*
1530 * Register offsets for CMU_PERI (0x101f0000)
1531 */
1532 #define CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK 0x0800
1533 #define CLK_CON_GAT_PERI_TMU_CPUCL0_CLK 0x0800
1534 #define CLK_CON_GAT_PERI_TMU_CPUCL1_CLK 0x0800
1535 #define CLK_CON_GAT_PERI_TMU_CLK 0x0800
1536 #define CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK 0x0810
1537 #define CLK_CON_GAT_PERI_GPIO2_PCLK 0x0810
1538 #define CLK_CON_GAT_PERI_GPIO5_PCLK 0x0810
1539 #define CLK_CON_GAT_PERI_GPIO6_PCLK 0x0810
1540 #define CLK_CON_GAT_PERI_GPIO7_PCLK 0x0810
1541 #define CLK_CON_GAT_PERI_HSI2C4_IPCLK 0x0810
1542 #define CLK_CON_GAT_PERI_HSI2C6_IPCLK 0x0810
1543 #define CLK_CON_GAT_PERI_HSI2C3_IPCLK 0x0810
1544 #define CLK_CON_GAT_PERI_HSI2C5_IPCLK 0x0810
1545 #define CLK_CON_GAT_PERI_HSI2C2_IPCLK 0x0810
1546 #define CLK_CON_GAT_PERI_HSI2C1_IPCLK 0x0810
1547 #define CLK_CON_GAT_PERI_I2C0_PCLK 0x0810
1548 #define CLK_CON_GAT_PERI_I2C4_PCLK 0x0810
1549 #define CLK_CON_GAT_PERI_I2C5_PCLK 0x0810
1550 #define CLK_CON_GAT_PERI_I2C6_PCLK 0x0810
1551 #define CLK_CON_GAT_PERI_I2C7_PCLK 0x0810
1552 #define CLK_CON_GAT_PERI_I2C8_PCLK 0x0810
1553 #define CLK_CON_GAT_PERI_I2C3_PCLK 0x0810
1554 #define CLK_CON_GAT_PERI_I2C2_PCLK 0x0810
1555 #define CLK_CON_GAT_PERI_I2C1_PCLK 0x0810
1556 #define CLK_CON_GAT_PERI_MCT_PCLK 0x0810
1557 #define CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0 0x0810
1558 #define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK 0x0814
1559 #define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK 0x0814
1560 #define CLK_CON_GAT_PERI_SFRIF_TMU_PCLK 0x0814
1561 #define CLK_CON_GAT_PERI_SPI0_PCLK 0x0814
1562 #define CLK_CON_GAT_PERI_SPI2_PCLK 0x0814
1563 #define CLK_CON_GAT_PERI_SPI1_PCLK 0x0814
1564 #define CLK_CON_GAT_PERI_SPI4_PCLK 0x0814
1565 #define CLK_CON_GAT_PERI_SPI3_PCLK 0x0814
1566 #define CLK_CON_GAT_PERI_UART1_PCLK 0x0814
1567 #define CLK_CON_GAT_PERI_UART2_PCLK 0x0814
1568 #define CLK_CON_GAT_PERI_UART0_PCLK 0x0814
1569 #define CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK 0x0814
1570 #define CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK 0x0814
1571 #define CLK_CON_GAT_PERI_UART1_EXT_UCLK 0x0830
1572 #define CLK_CON_GAT_PERI_UART2_EXT_UCLK 0x0834
1573 #define CLK_CON_GAT_PERI_UART0_EXT_UCLK 0x0838
1574 #define CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK 0x083c
1575 #define CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK 0x0840
1576 #define CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK 0x0844
1577 #define CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK 0x0848
1578 #define CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK 0x084c
1579
1580 static const unsigned long peri_clk_regs[] __initconst = {
1581 CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK,
1582 CLK_CON_GAT_PERI_TMU_CPUCL0_CLK,
1583 CLK_CON_GAT_PERI_TMU_CPUCL1_CLK,
1584 CLK_CON_GAT_PERI_TMU_CLK,
1585 CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK,
1586 CLK_CON_GAT_PERI_GPIO2_PCLK,
1587 CLK_CON_GAT_PERI_GPIO5_PCLK,
1588 CLK_CON_GAT_PERI_GPIO6_PCLK,
1589 CLK_CON_GAT_PERI_GPIO7_PCLK,
1590 CLK_CON_GAT_PERI_HSI2C4_IPCLK,
1591 CLK_CON_GAT_PERI_HSI2C6_IPCLK,
1592 CLK_CON_GAT_PERI_HSI2C3_IPCLK,
1593 CLK_CON_GAT_PERI_HSI2C5_IPCLK,
1594 CLK_CON_GAT_PERI_HSI2C2_IPCLK,
1595 CLK_CON_GAT_PERI_HSI2C1_IPCLK,
1596 CLK_CON_GAT_PERI_I2C0_PCLK,
1597 CLK_CON_GAT_PERI_I2C4_PCLK,
1598 CLK_CON_GAT_PERI_I2C5_PCLK,
1599 CLK_CON_GAT_PERI_I2C6_PCLK,
1600 CLK_CON_GAT_PERI_I2C7_PCLK,
1601 CLK_CON_GAT_PERI_I2C8_PCLK,
1602 CLK_CON_GAT_PERI_I2C3_PCLK,
1603 CLK_CON_GAT_PERI_I2C2_PCLK,
1604 CLK_CON_GAT_PERI_I2C1_PCLK,
1605 CLK_CON_GAT_PERI_MCT_PCLK,
1606 CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0,
1607 CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK,
1608 CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK,
1609 CLK_CON_GAT_PERI_SFRIF_TMU_PCLK,
1610 CLK_CON_GAT_PERI_SPI0_PCLK,
1611 CLK_CON_GAT_PERI_SPI2_PCLK,
1612 CLK_CON_GAT_PERI_SPI1_PCLK,
1613 CLK_CON_GAT_PERI_SPI4_PCLK,
1614 CLK_CON_GAT_PERI_SPI3_PCLK,
1615 CLK_CON_GAT_PERI_UART1_PCLK,
1616 CLK_CON_GAT_PERI_UART2_PCLK,
1617 CLK_CON_GAT_PERI_UART0_PCLK,
1618 CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK,
1619 CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK,
1620 CLK_CON_GAT_PERI_UART1_EXT_UCLK,
1621 CLK_CON_GAT_PERI_UART2_EXT_UCLK,
1622 CLK_CON_GAT_PERI_UART0_EXT_UCLK,
1623 CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK,
1624 CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK,
1625 CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK,
1626 CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK,
1627 CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK,
1628 };
1629
1630 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
1631 GATE(CLK_GOUT_PERI_BUSP1_PERIC0_HCLK, "gout_peri_busp1_peric0_hclk",
1632 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK, 3,
1633 CLK_SET_RATE_PARENT, 0),
1634 GATE(CLK_GOUT_PERI_GPIO2_PCLK, "gout_peri_gpio2_pclk",
1635 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO2_PCLK, 7,
1636 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1637 GATE(CLK_GOUT_PERI_GPIO5_PCLK, "gout_peri_gpio5_pclk",
1638 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO5_PCLK, 8,
1639 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1640 GATE(CLK_GOUT_PERI_GPIO6_PCLK, "gout_peri_gpio6_pclk",
1641 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO6_PCLK, 9,
1642 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1643 GATE(CLK_GOUT_PERI_GPIO7_PCLK, "gout_peri_gpio7_pclk",
1644 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO7_PCLK, 10,
1645 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1646 GATE(CLK_GOUT_PERI_HSI2C4_IPCLK, "gout_peri_hsi2c4_ipclk",
1647 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C4_IPCLK, 14,
1648 CLK_SET_RATE_PARENT, 0),
1649 GATE(CLK_GOUT_PERI_HSI2C6_IPCLK, "gout_peri_hsi2c6_ipclk",
1650 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_HSI2C6_IPCLK, 16,
1651 CLK_SET_RATE_PARENT, 0),
1652 GATE(CLK_GOUT_PERI_HSI2C3_IPCLK, "gout_peri_hsi2c3_ipclk",
1653 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C3_IPCLK, 13,
1654 CLK_SET_RATE_PARENT, 0),
1655 GATE(CLK_GOUT_PERI_HSI2C5_IPCLK, "gout_peri_hsi2c5_ipclk",
1656 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_HSI2C5_IPCLK, 15,
1657 CLK_SET_RATE_PARENT, 0),
1658 GATE(CLK_GOUT_PERI_HSI2C2_IPCLK, "gout_peri_hsi2c2_ipclk",
1659 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C2_IPCLK, 12,
1660 CLK_SET_RATE_PARENT, 0),
1661 GATE(CLK_GOUT_PERI_HSI2C1_IPCLK, "gout_peri_hsi2c1_ipclk",
1662 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C1_IPCLK, 11,
1663 CLK_SET_RATE_PARENT, 0),
1664 GATE(CLK_GOUT_PERI_I2C0_PCLK, "gout_peri_i2c0_pclk",
1665 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C0_PCLK, 21,
1666 CLK_SET_RATE_PARENT, 0),
1667 GATE(CLK_GOUT_PERI_I2C4_PCLK, "gout_peri_i2c4_pclk",
1668 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C4_PCLK, 17,
1669 CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_GOUT_PERI_I2C5_PCLK, "gout_peri_i2c5_pclk",
1671 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C5_PCLK, 18,
1672 CLK_SET_RATE_PARENT, 0),
1673 GATE(CLK_GOUT_PERI_I2C6_PCLK, "gout_peri_i2c6_pclk",
1674 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C6_PCLK, 19,
1675 CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_GOUT_PERI_I2C7_PCLK, "gout_peri_i2c7_pclk",
1677 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C7_PCLK, 24,
1678 CLK_SET_RATE_PARENT, 0),
1679 GATE(CLK_GOUT_PERI_I2C8_PCLK, "gout_peri_i2c8_pclk",
1680 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C8_PCLK, 25,
1681 CLK_SET_RATE_PARENT, 0),
1682 GATE(CLK_GOUT_PERI_I2C3_PCLK, "gout_peri_i2c3_pclk",
1683 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C3_PCLK, 20,
1684 CLK_SET_RATE_PARENT, 0),
1685 GATE(CLK_GOUT_PERI_I2C2_PCLK, "gout_peri_i2c2_pclk",
1686 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C2_PCLK, 22,
1687 CLK_SET_RATE_PARENT, 0),
1688 GATE(CLK_GOUT_PERI_I2C1_PCLK, "gout_peri_i2c1_pclk",
1689 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C1_PCLK, 23,
1690 CLK_SET_RATE_PARENT, 0),
1691 GATE(CLK_GOUT_PERI_MCT_PCLK, "gout_peri_mct_pclk",
1692 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_MCT_PCLK, 26,
1693 CLK_SET_RATE_PARENT, 0),
1694 GATE(CLK_GOUT_PERI_PWM_MOTOR_OSCCLK, "gout_peri_pwm_motor_oscclk",
1695 "oscclk", CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK, 2,
1696 CLK_SET_RATE_PARENT, 0),
1697 GATE(CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0, "gout_peri_pwm_motor_pclk_s0",
1698 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0, 29,
1699 CLK_SET_RATE_PARENT, 0),
1700 GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK,
1701 "gout_peri_sfrif_tmu_cpucl0_pclk", "gout_mif_cmu_peri_bus",
1702 CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK, 1, CLK_SET_RATE_PARENT, 0),
1703 GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK,
1704 "gout_peri_sfrif_tmu_cpucl1_pclk", "gout_mif_cmu_peri_bus",
1705 CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK, 2, CLK_SET_RATE_PARENT, 0),
1706 GATE(CLK_GOUT_PERI_SFRIF_TMU_PCLK, "gout_peri_sfrif_tmu_pclk",
1707 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SFRIF_TMU_PCLK, 3,
1708 CLK_SET_RATE_PARENT, 0),
1709 GATE(CLK_GOUT_PERI_SPI0_PCLK, "gout_peri_spi0_pclk",
1710 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI0_PCLK, 6,
1711 CLK_SET_RATE_PARENT, 0),
1712 GATE(CLK_GOUT_PERI_SPI0_SPI_EXT_CLK, "gout_peri_spi0_spi_ext_clk",
1713 "gout_mif_cmu_peri_spi0", CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK, 0,
1714 CLK_SET_RATE_PARENT, 0),
1715 GATE(CLK_GOUT_PERI_SPI2_PCLK, "gout_peri_spi2_pclk",
1716 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI2_PCLK, 4,
1717 CLK_SET_RATE_PARENT, 0),
1718 GATE(CLK_GOUT_PERI_SPI2_SPI_EXT_CLK, "gout_peri_spi2_spi_ext_clk",
1719 "gout_mif_cmu_peri_spi2", CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK, 0,
1720 CLK_SET_RATE_PARENT, 0),
1721 GATE(CLK_GOUT_PERI_SPI1_PCLK, "gout_peri_spi1_pclk",
1722 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI1_PCLK, 5,
1723 CLK_SET_RATE_PARENT, 0),
1724 GATE(CLK_GOUT_PERI_SPI1_SPI_EXT_CLK, "gout_peri_spi1_spi_ext_clk",
1725 "gout_mif_cmu_peri_spi1", CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK, 0,
1726 CLK_SET_RATE_PARENT, 0),
1727 GATE(CLK_GOUT_PERI_SPI4_PCLK, "gout_peri_spi4_pclk",
1728 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI4_PCLK, 8,
1729 CLK_SET_RATE_PARENT, 0),
1730 GATE(CLK_GOUT_PERI_SPI4_SPI_EXT_CLK, "gout_peri_spi4_spi_ext_clk",
1731 "gout_mif_cmu_peri_spi4", CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK, 0,
1732 CLK_SET_RATE_PARENT, 0),
1733 GATE(CLK_GOUT_PERI_SPI3_PCLK, "gout_peri_spi3_pclk",
1734 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI3_PCLK, 7,
1735 CLK_SET_RATE_PARENT, 0),
1736 GATE(CLK_GOUT_PERI_SPI3_SPI_EXT_CLK, "gout_peri_spi3_spi_ext_clk",
1737 "gout_mif_cmu_peri_spi3", CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK, 0,
1738 CLK_SET_RATE_PARENT, 0),
1739 GATE(CLK_GOUT_PERI_TMU_CPUCL0_CLK, "gout_peri_tmu_cpucl0_clk", "oscclk",
1740 CLK_CON_GAT_PERI_TMU_CPUCL0_CLK, 4, CLK_SET_RATE_PARENT, 0),
1741 GATE(CLK_GOUT_PERI_TMU_CPUCL1_CLK, "gout_peri_tmu_cpucl1_clk", "oscclk",
1742 CLK_CON_GAT_PERI_TMU_CPUCL1_CLK, 5, CLK_SET_RATE_PARENT, 0),
1743 GATE(CLK_GOUT_PERI_TMU_CLK, "gout_peri_tmu_clk", "oscclk",
1744 CLK_CON_GAT_PERI_TMU_CLK, 6, CLK_SET_RATE_PARENT, 0),
1745 GATE(CLK_GOUT_PERI_UART1_EXT_UCLK, "gout_peri_uart1_ext_uclk",
1746 "gout_mif_cmu_peri_uart1", CLK_CON_GAT_PERI_UART1_EXT_UCLK, 0,
1747 CLK_SET_RATE_PARENT, 0),
1748 GATE(CLK_GOUT_PERI_UART1_PCLK, "gout_peri_uart1_pclk",
1749 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART1_PCLK, 11,
1750 CLK_SET_RATE_PARENT, 0),
1751 GATE(CLK_GOUT_PERI_UART2_EXT_UCLK, "gout_peri_uart2_ext_uclk",
1752 "gout_mif_cmu_peri_uart2", CLK_CON_GAT_PERI_UART2_EXT_UCLK, 0,
1753 CLK_SET_RATE_PARENT, 0),
1754 GATE(CLK_GOUT_PERI_UART2_PCLK, "gout_peri_uart2_pclk",
1755 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART2_PCLK, 12,
1756 CLK_SET_RATE_PARENT, 0),
1757 GATE(CLK_GOUT_PERI_UART0_EXT_UCLK, "gout_peri_uart0_ext_uclk",
1758 "gout_mif_cmu_peri_uart0", CLK_CON_GAT_PERI_UART0_EXT_UCLK, 0,
1759 CLK_SET_RATE_PARENT, 0),
1760 GATE(CLK_GOUT_PERI_UART0_PCLK, "gout_peri_uart0_pclk",
1761 "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART0_PCLK, 10,
1762 CLK_SET_RATE_PARENT, 0),
1763 GATE(CLK_GOUT_PERI_WDT_CPUCL0_PCLK, "gout_peri_wdt_cpucl0_pclk",
1764 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK, 13,
1765 CLK_SET_RATE_PARENT, 0),
1766 GATE(CLK_GOUT_PERI_WDT_CPUCL1_PCLK, "gout_peri_wdt_cpucl1_pclk",
1767 "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK, 14,
1768 CLK_SET_RATE_PARENT, 0),
1769 };
1770
1771 static const struct samsung_cmu_info peri_cmu_info __initconst = {
1772 .gate_clks = peri_gate_clks,
1773 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
1774 .clk_regs = peri_clk_regs,
1775 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
1776 .nr_clk_ids = PERI_NR_CLK,
1777 };
1778
exynos7870_cmu_probe(struct platform_device * pdev)1779 static int __init exynos7870_cmu_probe(struct platform_device *pdev)
1780 {
1781 const struct samsung_cmu_info *info;
1782 struct device *dev = &pdev->dev;
1783
1784 info = of_device_get_match_data(dev);
1785 exynos_arm64_register_cmu(dev, dev->of_node, info);
1786
1787 return 0;
1788 }
1789
1790 static const struct of_device_id exynos7870_cmu_of_match[] = {
1791 {
1792 .compatible = "samsung,exynos7870-cmu-mif",
1793 .data = &mif_cmu_info,
1794 }, {
1795 .compatible = "samsung,exynos7870-cmu-dispaud",
1796 .data = &dispaud_cmu_info,
1797 }, {
1798 .compatible = "samsung,exynos7870-cmu-fsys",
1799 .data = &fsys_cmu_info,
1800 }, {
1801 .compatible = "samsung,exynos7870-cmu-g3d",
1802 .data = &g3d_cmu_info,
1803 }, {
1804 .compatible = "samsung,exynos7870-cmu-isp",
1805 .data = &isp_cmu_info,
1806 }, {
1807 .compatible = "samsung,exynos7870-cmu-mfcmscl",
1808 .data = &mfcmscl_cmu_info,
1809 }, {
1810 .compatible = "samsung,exynos7870-cmu-peri",
1811 .data = &peri_cmu_info,
1812 }, {
1813 },
1814 };
1815
1816 static struct platform_driver exynos7870_cmu_driver __refdata = {
1817 .driver = {
1818 .name = "exynos7870-cmu",
1819 .of_match_table = exynos7870_cmu_of_match,
1820 .suppress_bind_attrs = true,
1821 },
1822 .probe = exynos7870_cmu_probe,
1823 };
1824
exynos7870_cmu_init(void)1825 static int __init exynos7870_cmu_init(void)
1826 {
1827 return platform_driver_register(&exynos7870_cmu_driver);
1828 }
1829 core_initcall(exynos7870_cmu_init);
1830