1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
4 * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
5 *
6 * Common Clock Framework support for Exynos2200 SoC.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynos2200-cmu.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_DOUT_TCXO_DIV4 + 1)
21 #define CLKS_NR_ALIVE (CLK_DOUT_ALIVE_DSP_NOC + 1)
22 #define CLKS_NR_PERIS (CLK_DOUT_PERIS_DDD_CTRL + 1)
23 #define CLKS_NR_CMGP (CLK_DOUT_CMGP_USI6 + 1)
24 #define CLKS_NR_HSI0 (CLK_DOUT_DIV_CLK_HSI0_EUSB + 1)
25 #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_USI04 + 1)
26 #define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_USI10 + 1)
27 #define CLKS_NR_PERIC2 (CLK_DOUT_PERIC2_USI11 + 1)
28 #define CLKS_NR_UFS (CLK_MOUT_UFS_UFS_EMBD_USER + 1)
29 #define CLKS_NR_VTS (CLK_DOUT_CLKVTS_SERIAL_LIF_CORE + 1)
30
31 /* ---- CMU_TOP ------------------------------------------------------------ */
32
33 /* Register Offset definitions for CMU_TOP (0x1a320000) */
34 #define PLL_LOCKTIME_PLL_MMC 0x0
35 #define PLL_LOCKTIME_PLL_SHARED0 0x4
36 #define PLL_LOCKTIME_PLL_SHARED1 0x8
37 #define PLL_LOCKTIME_PLL_SHARED2 0xc
38 #define PLL_LOCKTIME_PLL_SHARED3 0x10
39 #define PLL_LOCKTIME_PLL_SHARED4 0x14
40 #define PLL_LOCKTIME_PLL_SHARED_MIF 0x18
41 #define PLL_CON3_PLL_MMC 0x10c
42 #define PLL_CON8_PLL_MMC 0x120
43 #define PLL_CON3_PLL_SHARED0 0x14c
44 #define PLL_CON8_PLL_SHARED0 0x160
45 #define PLL_CON3_PLL_SHARED1 0x18c
46 #define PLL_CON8_PLL_SHARED1 0x1a0
47 #define PLL_CON3_PLL_SHARED2 0x1cc
48 #define PLL_CON8_PLL_SHARED2 0x1e0
49 #define PLL_CON3_PLL_SHARED3 0x20c
50 #define PLL_CON8_PLL_SHARED3 0x220
51 #define PLL_CON3_PLL_SHARED4 0x24c
52 #define PLL_CON8_PLL_SHARED4 0x260
53 #define PLL_CON3_PLL_SHARED_MIF 0x28c
54 #define PLL_CON8_PLL_SHARED_MIF 0x2a0
55 #define PLL_CON0_MUX_CP_MPLL_CLK_D2_USER 0x600
56 #define PLL_CON1_MUX_CP_MPLL_CLK_D2_USER 0x604
57 #define PLL_CON0_MUX_CP_MPLL_CLK_USER 0x610
58 #define PLL_CON1_MUX_CP_MPLL_CLK_USER 0x614
59 #define CLK_CON_MUX_CLKCMU_AUD_AUDIF0 0x1000
60 #define CLK_CON_MUX_CLKCMU_AUD_AUDIF1 0x1004
61 #define CLK_CON_MUX_CLKCMU_AUD_CPU 0x1008
62 #define CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC 0x100c
63 #define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH 0x1010
64 #define CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH 0x1014
65 #define CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH 0x1018
66 #define CLK_CON_MUX_CLKCMU_DNC_NOC 0x101c
67 #define CLK_CON_MUX_CLKCMU_DPUB_NOC 0x1020
68 #define CLK_CON_MUX_CLKCMU_DPUF_NOC 0x1024
69 #define CLK_CON_MUX_CLKCMU_DSP_NOC 0x102c
70 #define CLK_CON_MUX_CLKCMU_DSU_SWITCH 0x1030
71 #define CLK_CON_MUX_CLKCMU_G3D_SWITCH 0x1034
72 #define CLK_CON_MUX_CLKCMU_GNPU_NOC 0x103c
73 #define CLK_CON_MUX_CLKCMU_UFS_MMC_CARD 0x1040
74 #define CLK_CON_MUX_CLKCMU_M2M_NOC 0x1044
75 #define CLK_CON_MUX_CLKCMU_NOCL0_NOC 0x1048
76 #define CLK_CON_MUX_CLKCMU_NOCL1A_NOC 0x104c
77 #define CLK_CON_MUX_CLKCMU_NOCL1B_NOC0 0x1050
78 #define CLK_CON_MUX_CLKCMU_NOCL1C_NOC 0x1054
79 #define CLK_CON_MUX_CLKCMU_SDMA_NOC 0x1058
80 #define CLK_CON_MUX_CP_HISPEEDY_CLK 0x105c
81 #define CLK_CON_MUX_CP_SHARED0_CLK 0x1060
82 #define CLK_CON_MUX_CP_SHARED2_CLK 0x1064
83 #define CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC 0x1068
84 #define CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0 0x106c
85 #define CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1 0x1070
86 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1074
87 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x1078
88 #define CLK_CON_MUX_MUX_CLKCMU_BRP_NOC 0x107c
89 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1080
90 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1084
91 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1088
92 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x108c
93 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1090
94 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1094
95 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1098
96 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x109c
97 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x10a0
98 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM 0x10a4
99 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU 0x10a8
100 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF 0x10ac
101 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC 0x10b0
102 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP 0x10b4
103 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x10b8
104 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x10bc
105 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x10c0
106 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY 0x10c4
107 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC 0x10c8
108 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU 0x10cc
109 #define CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC 0x10d0
110 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x10d4
111 #define CLK_CON_MUX_MUX_CLKCMU_DPUB 0x10d8
112 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT 0x10dc
113 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x10e0
114 #define CLK_CON_MUX_MUX_CLKCMU_DPUF 0x10e4
115 #define CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT 0x10e8
116 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x10f8
117 #define CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH 0x10fc
118 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1100
119 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1104
120 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x110c
121 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x1114
122 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC 0x1118
123 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x111c
124 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD 0x1120
125 #define CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD 0x1124
126 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1128
127 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x112c
128 #define CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD 0x1130
129 #define CLK_CON_MUX_MUX_CLKCMU_LME_LME 0x1134
130 #define CLK_CON_MUX_MUX_CLKCMU_LME_NOC 0x1138
131 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x1140
132 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x1148
133 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC 0x114c
134 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0 0x1150
135 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD 0x1154
136 #define CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1 0x1158
137 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x115c
138 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x1160
139 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x1164
140 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC 0x1168
141 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0 0x116c
142 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1 0x1170
143 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC 0x1174
144 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0 0x1178
145 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1 0x117c
146 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x1180
147 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0 0x1184
148 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1 0x1188
149 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x118c
150 #define CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0 0x1190
151 #define CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1 0x1194
152 #define CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC 0x1198
153 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC 0x119c
154 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC 0x11a0
155 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x11a8
156 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x11ac
157 #define CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC 0x11b0
158 #define CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC 0x11b4
159 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x11b8
160 #define CLK_CON_MUX_MUX_CP_HISPEEDY_CLK 0x11bc
161 #define CLK_CON_MUX_MUX_CP_SHARED0_CLK 0x11c0
162 #define CLK_CON_MUX_MUX_CP_SHARED1_CLK 0x11c4
163 #define CLK_CON_MUX_MUX_CP_SHARED2_CLK 0x11c8
164 #define CLK_CON_MUX_CLKCMU_M2M_FRC 0x11cc
165 #define CLK_CON_MUX_CLKCMU_MCSC_MCSC 0x11d0
166 #define CLK_CON_MUX_CLKCMU_MCSC_NOC 0x11d4
167 #define CLK_CON_MUX_MUX_CLKCMU_M2M_FRC 0x11d8
168 #define CLK_CON_MUX_MUX_CLKCMU_UFS_NOC 0x11dc
169 #define CLK_CON_DIV_CLKCMU_ALIVE_NOC 0x1800
170 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x1804
171 #define CLK_CON_DIV_CLKCMU_BRP_NOC 0x1808
172 #define CLK_CON_DIV_CLKCMU_CMU_BOOST 0x180c
173 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM 0x1810
174 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x1814
175 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF 0x1818
176 #define CLK_CON_DIV_CLKCMU_CPUCL0_NOCP 0x181c
177 #define CLK_CON_DIV_CLKCMU_CSIS_DCPHY 0x1820
178 #define CLK_CON_DIV_CLKCMU_CSIS_NOC 0x1824
179 #define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU 0x1828
180 #define CLK_CON_DIV_CLKCMU_CSTAT_NOC 0x182c
181 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x1830
182 #define CLK_CON_DIV_CLKCMU_LME_LME 0x1834
183 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1838
184 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1840
185 #define CLK_CON_DIV_CLKCMU_HSI0_DPOSC 0x1844
186 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1848
187 #define CLK_CON_DIV_CLKCMU_HSI0_USB32DRD 0x184c
188 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1850
189 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1854
190 #define CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD 0x1858
191 #define CLK_CON_DIV_CLKCMU_LME_NOC 0x1860
192 #define CLK_CON_DIV_CLKCMU_MFC0_MFC0 0x1874
193 #define CLK_CON_DIV_CLKCMU_MFC0_WFD 0x1878
194 #define CLK_CON_DIV_CLKCMU_MFC1_MFC1 0x187c
195 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x1880
196 #define CLK_CON_DIV_CLKCMU_NOCL1B_NOC1 0x1884
197 #define CLK_CON_DIV_CLKCMU_PERIC0_IP0 0x1888
198 #define CLK_CON_DIV_CLKCMU_PERIC0_IP1 0x188c
199 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x1890
200 #define CLK_CON_DIV_CLKCMU_PERIC1_IP0 0x1894
201 #define CLK_CON_DIV_CLKCMU_PERIC1_IP1 0x1898
202 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x189c
203 #define CLK_CON_DIV_CLKCMU_PERIC2_IP0 0x18a0
204 #define CLK_CON_DIV_CLKCMU_PERIC2_IP1 0x18a4
205 #define CLK_CON_DIV_CLKCMU_PERIC2_NOC 0x18a8
206 #define CLK_CON_DIV_CLKCMU_PERIS_GIC 0x18ac
207 #define CLK_CON_DIV_CLKCMU_PERIS_NOC 0x18b0
208 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18b8
209 #define CLK_CON_DIV_CLKCMU_VTS_DMIC 0x18bc
210 #define CLK_CON_DIV_CLKCMU_YUVP_NOC 0x18c0
211 #define CLK_CON_DIV_CP_SHARED1_CLK 0x18c4
212 #define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0 0x18c8
213 #define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM 0x18cc
214 #define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1 0x18d0
215 #define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM 0x18d4
216 #define CLK_CON_DIV_DIV_CLKCMU_AUD_CPU 0x18d8
217 #define CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM 0x18dc
218 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0 0x18e0
219 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1 0x18e4
220 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2 0x18e8
221 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3 0x18ec
222 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4 0x18f0
223 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5 0x18f4
224 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6 0x18f8
225 #define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7 0x18fc
226 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC 0x1900
227 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM 0x1904
228 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH 0x1908
229 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM 0x190c
230 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH 0x1910
231 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM 0x1914
232 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH 0x1918
233 #define CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM 0x191c
234 #define CLK_CON_DIV_DIV_CLKCMU_DNC_NOC 0x1920
235 #define CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM 0x1924
236 #define CLK_CON_DIV_DIV_CLKCMU_DPUB 0x1928
237 #define CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT 0x192c
238 #define CLK_CON_DIV_DIV_CLKCMU_DPUF 0x1930
239 #define CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT 0x1934
240 #define CLK_CON_DIV_DIV_CLKCMU_DSP_NOC 0x1940
241 #define CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM 0x1944
242 #define CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH 0x1948
243 #define CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM 0x194c
244 #define CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH 0x1950
245 #define CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM 0x1954
246 #define CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC 0x1960
247 #define CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM 0x1964
248 #define CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD 0x1968
249 #define CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM 0x196c
250 #define CLK_CON_DIV_DIV_CLKCMU_M2M_NOC 0x1970
251 #define CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM 0x1974
252 #define CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC 0x1978
253 #define CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM 0x197c
254 #define CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC 0x1980
255 #define CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM 0x1984
256 #define CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0 0x1988
257 #define CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM 0x198c
258 #define CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC 0x1990
259 #define CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM 0x1994
260 #define CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC 0x1998
261 #define CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM 0x199c
262 #define CLK_CON_DIV_DIV_CP_HISPEEDY_CLK 0x19a0
263 #define CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM 0x19a4
264 #define CLK_CON_DIV_DIV_CP_SHARED0_CLK 0x19a8
265 #define CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM 0x19ac
266 #define CLK_CON_DIV_DIV_CP_SHARED2_CLK 0x19b0
267 #define CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM 0x19b4
268 #define CLK_CON_DIV_CLKCMU_UFS_NOC 0x19b8
269 #define CLK_CON_DIV_DIV_CLKCMU_M2M_FRC 0x19bc
270 #define CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM 0x19c0
271 #define CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC 0x19c4
272 #define CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM 0x19c8
273 #define CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC 0x19cc
274 #define CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM 0x19d0
275 #define CLK_CON_GAT_CLKCMU_MIF01_SWITCH 0x2000
276 #define CLK_CON_GAT_CLKCMU_MIF23_SWITCH 0x2004
277 #define CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC 0x200c
278 #define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0 0x2010
279 #define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM 0x2014
280 #define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1 0x2018
281 #define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM 0x201c
282 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2020
283 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM 0x2024
284 #define CLK_CON_GAT_GATE_CLKCMU_AUD_NOC 0x2028
285 #define CLK_CON_GAT_GATE_CLKCMU_BRP_NOC 0x202c
286 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2030
287 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2034
288 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2038
289 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x203c
290 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2040
291 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2044
292 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x2048
293 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x204c
294 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2050
295 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM 0x2054
296 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU 0x2058
297 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF 0x205c
298 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC 0x2060
299 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM 0x2064
300 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP 0x2068
301 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x206c
302 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM 0x2070
303 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2074
304 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM 0x2078
305 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x207c
306 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM 0x2080
307 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY 0x2084
308 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC 0x2088
309 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU 0x208c
310 #define CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC 0x2090
311 #define CLK_CON_GAT_GATE_CLKCMU_DNC_NOC 0x2094
312 #define CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM 0x2098
313 #define CLK_CON_GAT_GATE_CLKCMU_DPUB 0x209c
314 #define CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT 0x20a0
315 #define CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM 0x20a4
316 #define CLK_CON_GAT_GATE_CLKCMU_DPUF 0x20a8
317 #define CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT 0x20ac
318 #define CLK_CON_GAT_GATE_CLKCMU_DSP_NOC 0x20bc
319 #define CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM 0x20c0
320 #define CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH 0x20c4
321 #define CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM 0x20c8
322 #define CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP 0x20cc
323 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x20d0
324 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM 0x20d4
325 #define CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC 0x20e0
326 #define CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM 0x20e4
327 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ec
328 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC 0x20f0
329 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC 0x20f4
330 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD 0x20f8
331 #define CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD 0x20fc
332 #define CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM 0x2100
333 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC 0x2104
334 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x2108
335 #define CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD 0x210c
336 #define CLK_CON_GAT_GATE_CLKCMU_LME_LME 0x2110
337 #define CLK_CON_GAT_GATE_CLKCMU_LME_NOC 0x2114
338 #define CLK_CON_GAT_GATE_CLKCMU_M2M_NOC 0x2118
339 #define CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM 0x211c
340 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0 0x212c
341 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD 0x2130
342 #define CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1 0x2134
343 #define CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP 0x2138
344 #define CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC 0x213c
345 #define CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM 0x2140
346 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC 0x2144
347 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM 0x2148
348 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0 0x214c
349 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM 0x2150
350 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1 0x2154
351 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC 0x2158
352 #define CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM 0x215c
353 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0 0x2160
354 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1 0x2164
355 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC 0x2168
356 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0 0x216c
357 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1 0x2170
358 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC 0x2174
359 #define CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0 0x2178
360 #define CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1 0x217c
361 #define CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC 0x2180
362 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC 0x2184
363 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC 0x2188
364 #define CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC 0x2190
365 #define CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM 0x2194
366 #define CLK_CON_GAT_GATE_CLKCMU_SSP_NOC 0x2198
367 #define CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC 0x219c
368 #define CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC 0x21a0
369 #define CLK_CON_GAT_GATE_CP_HISPEEDY_CLK 0x21a4
370 #define CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM 0x21a8
371 #define CLK_CON_GAT_GATE_CP_SHARED0_CLK 0x21ac
372 #define CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM 0x21b0
373 #define CLK_CON_GAT_GATE_CP_SHARED1_CLK 0x21b4
374 #define CLK_CON_GAT_GATE_CP_SHARED2_CLK 0x21b8
375 #define CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM 0x21bc
376 #define CLK_CON_GAT_GATE_CLKCMU_UFS_NOC 0x21c0
377 #define CLK_CON_GAT_GATE_CLKCMU_M2M_FRC 0x21c4
378 #define CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM 0x21c8
379 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x21cc
380 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM 0x21d0
381 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC 0x21d4
382 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM 0x21d8
383
384 static const unsigned long top_clk_regs[] __initconst = {
385 PLL_LOCKTIME_PLL_MMC,
386 PLL_LOCKTIME_PLL_SHARED0,
387 PLL_LOCKTIME_PLL_SHARED1,
388 PLL_LOCKTIME_PLL_SHARED2,
389 PLL_LOCKTIME_PLL_SHARED3,
390 PLL_LOCKTIME_PLL_SHARED4,
391 PLL_LOCKTIME_PLL_SHARED_MIF,
392 PLL_CON3_PLL_MMC,
393 PLL_CON8_PLL_MMC,
394 PLL_CON3_PLL_SHARED0,
395 PLL_CON8_PLL_SHARED0,
396 PLL_CON3_PLL_SHARED1,
397 PLL_CON8_PLL_SHARED1,
398 PLL_CON3_PLL_SHARED2,
399 PLL_CON8_PLL_SHARED2,
400 PLL_CON3_PLL_SHARED3,
401 PLL_CON8_PLL_SHARED3,
402 PLL_CON3_PLL_SHARED4,
403 PLL_CON8_PLL_SHARED4,
404 PLL_CON3_PLL_SHARED_MIF,
405 PLL_CON8_PLL_SHARED_MIF,
406 PLL_CON0_MUX_CP_MPLL_CLK_D2_USER,
407 PLL_CON1_MUX_CP_MPLL_CLK_D2_USER,
408 PLL_CON0_MUX_CP_MPLL_CLK_USER,
409 PLL_CON1_MUX_CP_MPLL_CLK_USER,
410 CLK_CON_MUX_CLKCMU_AUD_AUDIF0,
411 CLK_CON_MUX_CLKCMU_AUD_AUDIF1,
412 CLK_CON_MUX_CLKCMU_AUD_CPU,
413 CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC,
414 CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH,
415 CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH,
416 CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH,
417 CLK_CON_MUX_CLKCMU_DNC_NOC,
418 CLK_CON_MUX_CLKCMU_DPUB_NOC,
419 CLK_CON_MUX_CLKCMU_DPUF_NOC,
420 CLK_CON_MUX_CLKCMU_DSP_NOC,
421 CLK_CON_MUX_CLKCMU_DSU_SWITCH,
422 CLK_CON_MUX_CLKCMU_G3D_SWITCH,
423 CLK_CON_MUX_CLKCMU_GNPU_NOC,
424 CLK_CON_MUX_CLKCMU_UFS_MMC_CARD,
425 CLK_CON_MUX_CLKCMU_M2M_NOC,
426 CLK_CON_MUX_CLKCMU_NOCL0_NOC,
427 CLK_CON_MUX_CLKCMU_NOCL1A_NOC,
428 CLK_CON_MUX_CLKCMU_NOCL1B_NOC0,
429 CLK_CON_MUX_CLKCMU_NOCL1C_NOC,
430 CLK_CON_MUX_CLKCMU_SDMA_NOC,
431 CLK_CON_MUX_CP_HISPEEDY_CLK,
432 CLK_CON_MUX_CP_SHARED0_CLK,
433 CLK_CON_MUX_CP_SHARED2_CLK,
434 CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC,
435 CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0,
436 CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1,
437 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
438 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
439 CLK_CON_MUX_MUX_CLKCMU_BRP_NOC,
440 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
441 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
442 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
443 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
444 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
445 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
446 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
447 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
448 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
449 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM,
450 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
451 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF,
452 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC,
453 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP,
454 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
455 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
456 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
457 CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY,
458 CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC,
459 CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
460 CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC,
461 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
462 CLK_CON_MUX_MUX_CLKCMU_DPUB,
463 CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT,
464 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
465 CLK_CON_MUX_MUX_CLKCMU_DPUF,
466 CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT,
467 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
468 CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH,
469 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
470 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
471 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
472 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
473 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC,
474 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
475 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD,
476 CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD,
477 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
478 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
479 CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD,
480 CLK_CON_MUX_MUX_CLKCMU_LME_LME,
481 CLK_CON_MUX_MUX_CLKCMU_LME_NOC,
482 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
483 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
484 CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC,
485 CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
486 CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
487 CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1,
488 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
489 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
490 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
491 CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC,
492 CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0,
493 CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1,
494 CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC,
495 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0,
496 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1,
497 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
498 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0,
499 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1,
500 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
501 CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0,
502 CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1,
503 CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC,
504 CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC,
505 CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC,
506 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
507 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
508 CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC,
509 CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC,
510 CLK_CON_MUX_MUX_CMU_CMUREF,
511 CLK_CON_MUX_MUX_CP_HISPEEDY_CLK,
512 CLK_CON_MUX_MUX_CP_SHARED0_CLK,
513 CLK_CON_MUX_MUX_CP_SHARED1_CLK,
514 CLK_CON_MUX_MUX_CP_SHARED2_CLK,
515 CLK_CON_MUX_CLKCMU_M2M_FRC,
516 CLK_CON_MUX_CLKCMU_MCSC_MCSC,
517 CLK_CON_MUX_CLKCMU_MCSC_NOC,
518 CLK_CON_MUX_MUX_CLKCMU_M2M_FRC,
519 CLK_CON_MUX_MUX_CLKCMU_UFS_NOC,
520 CLK_CON_DIV_CLKCMU_ALIVE_NOC,
521 CLK_CON_DIV_CLKCMU_AUD_NOC,
522 CLK_CON_DIV_CLKCMU_BRP_NOC,
523 CLK_CON_DIV_CLKCMU_CMU_BOOST,
524 CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM,
525 CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
526 CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF,
527 CLK_CON_DIV_CLKCMU_CPUCL0_NOCP,
528 CLK_CON_DIV_CLKCMU_CSIS_DCPHY,
529 CLK_CON_DIV_CLKCMU_CSIS_NOC,
530 CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
531 CLK_CON_DIV_CLKCMU_CSTAT_NOC,
532 CLK_CON_DIV_CLKCMU_DPUB_DSIM,
533 CLK_CON_DIV_CLKCMU_LME_LME,
534 CLK_CON_DIV_CLKCMU_G3D_NOCP,
535 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
536 CLK_CON_DIV_CLKCMU_HSI0_DPOSC,
537 CLK_CON_DIV_CLKCMU_HSI0_NOC,
538 CLK_CON_DIV_CLKCMU_HSI0_USB32DRD,
539 CLK_CON_DIV_CLKCMU_HSI1_NOC,
540 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
541 CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD,
542 CLK_CON_DIV_CLKCMU_LME_NOC,
543 CLK_CON_DIV_CLKCMU_MFC0_MFC0,
544 CLK_CON_DIV_CLKCMU_MFC0_WFD,
545 CLK_CON_DIV_CLKCMU_MFC1_MFC1,
546 CLK_CON_DIV_CLKCMU_MIF_NOCP,
547 CLK_CON_DIV_CLKCMU_NOCL1B_NOC1,
548 CLK_CON_DIV_CLKCMU_PERIC0_IP0,
549 CLK_CON_DIV_CLKCMU_PERIC0_IP1,
550 CLK_CON_DIV_CLKCMU_PERIC0_NOC,
551 CLK_CON_DIV_CLKCMU_PERIC1_IP0,
552 CLK_CON_DIV_CLKCMU_PERIC1_IP1,
553 CLK_CON_DIV_CLKCMU_PERIC1_NOC,
554 CLK_CON_DIV_CLKCMU_PERIC2_IP0,
555 CLK_CON_DIV_CLKCMU_PERIC2_IP1,
556 CLK_CON_DIV_CLKCMU_PERIC2_NOC,
557 CLK_CON_DIV_CLKCMU_PERIS_GIC,
558 CLK_CON_DIV_CLKCMU_PERIS_NOC,
559 CLK_CON_DIV_CLKCMU_SSP_NOC,
560 CLK_CON_DIV_CLKCMU_VTS_DMIC,
561 CLK_CON_DIV_CLKCMU_YUVP_NOC,
562 CLK_CON_DIV_CP_SHARED1_CLK,
563 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0,
564 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM,
565 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1,
566 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM,
567 CLK_CON_DIV_DIV_CLKCMU_AUD_CPU,
568 CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM,
569 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0,
570 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1,
571 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2,
572 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3,
573 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4,
574 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5,
575 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6,
576 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7,
577 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC,
578 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM,
579 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH,
580 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM,
581 CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH,
582 CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM,
583 CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH,
584 CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM,
585 CLK_CON_DIV_DIV_CLKCMU_DNC_NOC,
586 CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM,
587 CLK_CON_DIV_DIV_CLKCMU_DPUB,
588 CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT,
589 CLK_CON_DIV_DIV_CLKCMU_DPUF,
590 CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT,
591 CLK_CON_DIV_DIV_CLKCMU_DSP_NOC,
592 CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM,
593 CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH,
594 CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM,
595 CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH,
596 CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM,
597 CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC,
598 CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM,
599 CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD,
600 CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM,
601 CLK_CON_DIV_DIV_CLKCMU_M2M_NOC,
602 CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM,
603 CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC,
604 CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM,
605 CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC,
606 CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM,
607 CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0,
608 CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM,
609 CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC,
610 CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM,
611 CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC,
612 CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM,
613 CLK_CON_DIV_DIV_CP_HISPEEDY_CLK,
614 CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM,
615 CLK_CON_DIV_DIV_CP_SHARED0_CLK,
616 CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM,
617 CLK_CON_DIV_DIV_CP_SHARED2_CLK,
618 CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM,
619 CLK_CON_DIV_CLKCMU_UFS_NOC,
620 CLK_CON_DIV_DIV_CLKCMU_M2M_FRC,
621 CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM,
622 CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC,
623 CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM,
624 CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC,
625 CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM,
626 CLK_CON_GAT_CLKCMU_MIF01_SWITCH,
627 CLK_CON_GAT_CLKCMU_MIF23_SWITCH,
628 CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC,
629 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0,
630 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM,
631 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1,
632 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM,
633 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
634 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM,
635 CLK_CON_GAT_GATE_CLKCMU_AUD_NOC,
636 CLK_CON_GAT_GATE_CLKCMU_BRP_NOC,
637 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
638 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
639 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
640 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
641 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
642 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
643 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
644 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
645 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
646 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM,
647 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU,
648 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF,
649 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC,
650 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM,
651 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP,
652 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
653 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM,
654 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
655 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM,
656 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
657 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM,
658 CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY,
659 CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC,
660 CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
661 CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC,
662 CLK_CON_GAT_GATE_CLKCMU_DNC_NOC,
663 CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM,
664 CLK_CON_GAT_GATE_CLKCMU_DPUB,
665 CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT,
666 CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM,
667 CLK_CON_GAT_GATE_CLKCMU_DPUF,
668 CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT,
669 CLK_CON_GAT_GATE_CLKCMU_DSP_NOC,
670 CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM,
671 CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH,
672 CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM,
673 CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP,
674 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
675 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM,
676 CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC,
677 CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM,
678 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
679 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC,
680 CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC,
681 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD,
682 CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD,
683 CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM,
684 CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC,
685 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
686 CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD,
687 CLK_CON_GAT_GATE_CLKCMU_LME_LME,
688 CLK_CON_GAT_GATE_CLKCMU_LME_NOC,
689 CLK_CON_GAT_GATE_CLKCMU_M2M_NOC,
690 CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM,
691 CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
692 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
693 CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1,
694 CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP,
695 CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC,
696 CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM,
697 CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC,
698 CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM,
699 CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0,
700 CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM,
701 CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1,
702 CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC,
703 CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM,
704 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0,
705 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1,
706 CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC,
707 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0,
708 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1,
709 CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC,
710 CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0,
711 CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1,
712 CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC,
713 CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC,
714 CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC,
715 CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC,
716 CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM,
717 CLK_CON_GAT_GATE_CLKCMU_SSP_NOC,
718 CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC,
719 CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC,
720 CLK_CON_GAT_GATE_CP_HISPEEDY_CLK,
721 CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM,
722 CLK_CON_GAT_GATE_CP_SHARED0_CLK,
723 CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM,
724 CLK_CON_GAT_GATE_CP_SHARED1_CLK,
725 CLK_CON_GAT_GATE_CP_SHARED2_CLK,
726 CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM,
727 CLK_CON_GAT_GATE_CLKCMU_UFS_NOC,
728 CLK_CON_GAT_GATE_CLKCMU_M2M_FRC,
729 CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM,
730 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
731 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM,
732 CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC,
733 CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM,
734 };
735
736 /* List of parent clocks for Muxes in CMU_TOP */
737 PNAME(mout_cmu_cp_mpll_clk_d2_user_parents) = { "oscclk" };
738 PNAME(mout_cmu_cp_mpll_clk_user_parents) = { "oscclk" };
739 PNAME(mout_cmu_aud_audif0_p) = { "dout_shared0_div1",
740 "dout_shared1_div1",
741 "dout_shared3_div1",
742 "dout_shared4_div1",
743 "mout_cmu_cp_mpll_clk_d2_user",
744 "oscclk", "oscclk",
745 "oscclk" };
746 PNAME(mout_cmu_aud_audif1_p) = { "dout_shared0_div1",
747 "dout_shared1_div1",
748 "dout_shared3_div1",
749 "dout_shared4_div1",
750 "mout_cmu_cp_mpll_clk_d2_user",
751 "oscclk", "oscclk",
752 "oscclk" };
753 PNAME(mout_cmu_aud_cpu_p) = { "dout_shared0_div1",
754 "dout_shared1_div1",
755 "dout_shared2_div1",
756 "dout_shared3_div1",
757 "dout_shared4_div1",
758 "dout_shared0_div2",
759 "dout_shared1_div2",
760 "mout_cmu_cp_mpll_clk_d2_user" };
761 PNAME(mout_cmu_cpucl0_dbg_noc_p) = { "dout_shared2_div1",
762 "dout_shared4_div1",
763 "dout_shared0_div2",
764 "dout_shared1_div2" };
765 PNAME(mout_cmu_cpucl0_switch_p) = { "dout_shared0_div1",
766 "dout_shared1_div1",
767 "dout_shared2_div1",
768 "dout_shared3_div1",
769 "dout_shared4_div1",
770 "dout_shared0_div2",
771 "oscclk", "oscclk" };
772 PNAME(mout_cmu_cpucl1_switch_p) = { "dout_shared0_div1",
773 "dout_shared1_div1",
774 "dout_shared2_div1",
775 "dout_shared3_div1",
776 "dout_shared4_div1",
777 "dout_shared0_div2",
778 "oscclk", "oscclk" };
779 PNAME(mout_cmu_cpucl2_switch_p) = { "dout_shared0_div1",
780 "dout_shared1_div1",
781 "dout_shared2_div1",
782 "dout_shared3_div1",
783 "dout_shared4_div1",
784 "dout_shared0_div2",
785 "oscclk", "oscclk" };
786 PNAME(mout_cmu_dnc_noc_p) = { "dout_shared0_div1",
787 "dout_shared1_div1",
788 "dout_shared2_div1",
789 "dout_shared3_div1",
790 "dout_shared4_div1",
791 "dout_shared0_div2",
792 "dout_shared1_div2",
793 "oscclk" };
794 PNAME(mout_cmu_dpub_noc_p) = { "dout_cmu_div_dpub",
795 "dout_cmu_div_dpub_alt"};
796 PNAME(mout_cmu_dpuf_noc_p) = { "dout_cmu_div_dpuf",
797 "dout_cmu_div_dpuf_alt" };
798 PNAME(mout_cmu_dsp_noc_p) = { "dout_shared0_div1",
799 "dout_shared1_div1",
800 "dout_shared2_div1",
801 "dout_shared3_div1",
802 "dout_shared4_div1",
803 "dout_shared0_div2",
804 "dout_shared1_div2",
805 "oscclk" };
806 PNAME(mout_cmu_dsu_switch_p) = { "dout_shared0_div1",
807 "dout_shared1_div1",
808 "dout_shared2_div1",
809 "dout_shared3_div1",
810 "dout_shared4_div1",
811 "dout_shared0_div2",
812 "oscclk", "oscclk" };
813 PNAME(mout_cmu_g3d_switch_p) = { "dout_shared0_div1",
814 "dout_shared1_div1",
815 "dout_shared2_div1",
816 "dout_shared3_div1",
817 "dout_shared4_div1",
818 "dout_shared0_div2",
819 "dout_shared1_div2",
820 "dout_shared2_div2" };
821 PNAME(mout_cmu_gnpu_noc_p) = { "dout_shared0_div1",
822 "dout_shared1_div1",
823 "dout_shared2_div1",
824 "dout_shared3_div1",
825 "dout_shared4_div1",
826 "dout_shared0_div2",
827 "dout_shared1_div2",
828 "oscclk" };
829 PNAME(mout_cmu_ufs_mmc_card_p) = { "oscclk",
830 "dout_shared2_div1",
831 "dout_mmc_div1",
832 "dout_shared0_div2" };
833 PNAME(mout_cmu_m2m_noc_p) = { "dout_shared2_div1",
834 "dout_shared3_div1",
835 "dout_shared4_div1",
836 "dout_shared0_div2",
837 "dout_shared1_div2",
838 "dout_shared2_div2",
839 "dout_shared3_div2",
840 "oscclk" };
841 PNAME(mout_cmu_nocl0_noc_p) = { "dout_shared0_div1",
842 "dout_shared1_div1",
843 "dout_shared2_div1",
844 "dout_shared3_div1",
845 "dout_shared4_div1",
846 "dout_shared0_div2",
847 "mout_cmu_cp_mpll_clk_d2_user",
848 "dout_shared_mif_div2" };
849 PNAME(mout_cmu_nocl1a_noc_p) = { "dout_shared2_div1",
850 "dout_shared3_div1",
851 "dout_shared4_div1",
852 "dout_shared0_div2",
853 "dout_shared1_div2",
854 "dout_shared2_div2",
855 "dout_shared3_div2",
856 "dout_shared4_div2" };
857 PNAME(mout_cmu_nocl1b_noc0_p) = { "dout_shared2_div1",
858 "dout_shared3_div1",
859 "dout_shared4_div1",
860 "dout_shared0_div2",
861 "dout_shared1_div2",
862 "dout_shared2_div2",
863 "dout_shared3_div2",
864 "dout_shared4_div2" };
865 PNAME(mout_cmu_nocl1c_noc_p) = { "dout_shared2_div1",
866 "dout_shared3_div1",
867 "dout_shared4_div1",
868 "dout_shared0_div2",
869 "dout_shared1_div2",
870 "dout_shared2_div2",
871 "dout_shared3_div2",
872 "dout_shared4_div2" };
873 PNAME(mout_cmu_sdma_noc_p) = { "dout_shared0_div1",
874 "dout_shared1_div1",
875 "dout_shared2_div1",
876 "dout_shared3_div1",
877 "dout_shared4_div1",
878 "dout_shared0_div2",
879 "dout_shared1_div2",
880 "oscclk" };
881 PNAME(mout_cmu_cp_hispeedy_clk_p) = { "dout_shared2_div1",
882 "dout_shared3_div1" };
883 PNAME(mout_cmu_cp_shared0_clk_p) = { "dout_shared0_div1",
884 "dout_shared1_div1",
885 "dout_shared2_div1",
886 "dout_shared3_div1" };
887 PNAME(mout_cmu_cp_shared2_clk_p) = { "dout_shared2_div1",
888 "dout_shared3_div1",
889 "dout_shared4_div1",
890 "dout_shared1_div2" };
891 PNAME(mout_cmu_mux_alive_noc_p) = { "dout_shared0_div2",
892 "dout_shared2_div2" };
893 PNAME(mout_cmu_mux_aud_audif0_p) = { "dout_shared0_div1",
894 "dout_shared1_div1",
895 "dout_shared3_div1",
896 "dout_shared4_div1",
897 "mout_cmu_cp_mpll_clk_d2_user",
898 "oscclk", "oscclk",
899 "oscclk" };
900 PNAME(mout_cmu_mux_aud_audif1_p) = { "dout_shared0_div1",
901 "dout_shared1_div1",
902 "dout_shared3_div1",
903 "dout_shared4_div1",
904 "mout_cmu_cp_mpll_clk_d2_user",
905 "oscclk", "oscclk",
906 "oscclk" };
907 PNAME(mout_cmu_mux_aud_cpu_p) = { "dout_shared0_div1",
908 "dout_shared1_div1",
909 "dout_shared2_div1",
910 "dout_shared3_div1",
911 "dout_shared4_div1",
912 "dout_shared0_div2",
913 "dout_shared1_div2",
914 "mout_cmu_cp_mpll_clk_d2_user" };
915 PNAME(mout_cmu_mux_aud_noc_p) = { "dout_shared4_div1",
916 "dout_shared0_div2",
917 "dout_shared1_div2",
918 "dout_shared2_div2",
919 "dout_shared3_div2",
920 "mout_cmu_cp_mpll_clk_d2_user",
921 "oscclk", "oscclk" };
922 PNAME(mout_cmu_mux_brp_noc_p) = { "dout_shared2_div1",
923 "dout_shared3_div1",
924 "dout_shared4_div1",
925 "dout_shared0_div2",
926 "dout_shared1_div2",
927 "dout_shared2_div2",
928 "dout_shared3_div2",
929 "oscclk" };
930 PNAME(mout_cmu_mux_cis_clk0_p) = { "oscclk",
931 "dout_shared2_div2" };
932 PNAME(mout_cmu_mux_cis_clk1_p) = { "oscclk",
933 "dout_shared2_div2" };
934 PNAME(mout_cmu_mux_cis_clk2_p) = { "oscclk",
935 "dout_shared2_div2" };
936 PNAME(mout_cmu_mux_cis_clk3_p) = { "oscclk",
937 "dout_shared2_div2" };
938 PNAME(mout_cmu_mux_cis_clk4_p) = { "oscclk",
939 "dout_shared2_div2" };
940 PNAME(mout_cmu_mux_cis_clk5_p) = { "oscclk",
941 "dout_shared2_div2" };
942 PNAME(mout_cmu_mux_cis_clk6_p) = { "oscclk",
943 "dout_shared2_div2" };
944 PNAME(mout_cmu_mux_cis_clk7_p) = { "oscclk",
945 "dout_shared2_div2" };
946 PNAME(mout_cmu_mux_cmu_boost_p) = { "dout_shared0_div2",
947 "dout_shared1_div2",
948 "dout_shared2_div2",
949 "dout_shared4_div2" };
950 PNAME(mout_cmu_mux_cmu_boost_cam_p) = { "dout_shared0_div2",
951 "dout_shared1_div2",
952 "dout_shared2_div2",
953 "dout_shared4_div2" };
954 PNAME(mout_cmu_mux_cmu_boost_cpu_p) = { "dout_shared0_div2",
955 "dout_shared1_div2",
956 "dout_shared2_div2",
957 "dout_shared4_div2" };
958 PNAME(mout_cmu_mux_cmu_boost_mif_p) = { "dout_shared0_div2",
959 "dout_shared1_div2",
960 "dout_shared2_div2",
961 "dout_shared4_div2" };
962 PNAME(mout_cmu_mux_cpucl0_dbg_noc_p) = { "dout_shared2_div1",
963 "dout_shared4_div1",
964 "dout_shared0_div2",
965 "dout_shared1_div2" };
966 PNAME(mout_cmu_mux_cpucl0_nocp_p) = { "dout_shared0_div2",
967 "dout_shared1_div2",
968 "dout_shared2_div2",
969 "dout_shared4_div2" };
970 PNAME(mout_cmu_mux_cpucl0_switch_p) = { "dout_shared0_div1",
971 "dout_shared1_div1",
972 "dout_shared2_div1",
973 "dout_shared3_div1",
974 "dout_shared4_div1",
975 "dout_shared0_div2",
976 "oscclk", "oscclk" };
977 PNAME(mout_cmu_mux_cpucl1_switch_p) = { "dout_shared0_div1",
978 "dout_shared1_div1",
979 "dout_shared2_div1",
980 "dout_shared3_div1",
981 "dout_shared4_div1",
982 "dout_shared0_div2",
983 "oscclk", "oscclk" };
984 PNAME(mout_cmu_mux_cpucl2_switch_p) = { "dout_shared0_div1",
985 "dout_shared1_div1",
986 "dout_shared2_div1",
987 "dout_shared3_div1",
988 "dout_shared4_div1",
989 "dout_shared0_div2",
990 "oscclk", "oscclk" };
991 PNAME(mout_cmu_mux_csis_dcphy_p) = { "dout_shared0_div2",
992 "dout_shared1_div2",
993 "dout_shared2_div2",
994 "dout_shared4_div2" };
995 PNAME(mout_cmu_mux_csis_noc_p) = { "dout_shared2_div1",
996 "dout_shared3_div1",
997 "dout_shared4_div1",
998 "dout_shared0_div2",
999 "dout_shared1_div2",
1000 "dout_shared2_div2",
1001 "dout_shared3_div2",
1002 "oscclk" };
1003 PNAME(mout_cmu_mux_csis_ois_mcu_p) = { "dout_shared0_div2",
1004 "dout_shared2_div2" };
1005 PNAME(mout_cmu_mux_cstat_noc_p) = { "dout_shared2_div1",
1006 "dout_shared3_div1",
1007 "dout_shared4_div1",
1008 "dout_shared0_div2",
1009 "dout_shared1_div2",
1010 "dout_shared2_div2",
1011 "dout_shared3_div2",
1012 "oscclk" };
1013 PNAME(mout_cmu_mux_dnc_noc_p) = { "dout_shared0_div1",
1014 "dout_shared1_div1",
1015 "dout_shared2_div1",
1016 "dout_shared3_div1",
1017 "dout_shared4_div1",
1018 "dout_shared0_div2",
1019 "dout_shared1_div2",
1020 "oscclk" };
1021 PNAME(mout_cmu_mux_dpub_p) = { "dout_shared2_div1",
1022 "dout_shared3_div1",
1023 "dout_shared4_div1",
1024 "dout_shared0_div2",
1025 "dout_shared1_div2",
1026 "dout_shared2_div2",
1027 "oscclk", "oscclk" };
1028 PNAME(mout_cmu_mux_dpub_alt_p) = { "dout_shared2_div1",
1029 "dout_shared3_div1",
1030 "dout_shared4_div1",
1031 "dout_shared0_div2",
1032 "dout_shared1_div2",
1033 "dout_shared2_div2",
1034 "oscclk", "oscclk" };
1035 PNAME(mout_cmu_mux_dpub_dsim_p) = { "dout_shared0_div2",
1036 "dout_shared1_div2",
1037 "dout_shared2_div2",
1038 "dout_shared3_div2" };
1039 PNAME(mout_cmu_mux_dpuf_p) = { "dout_shared2_div1",
1040 "dout_shared3_div1",
1041 "dout_shared4_div1",
1042 "dout_shared0_div2",
1043 "dout_shared1_div2",
1044 "dout_shared2_div2",
1045 "oscclk", "oscclk" };
1046 PNAME(mout_cmu_mux_dpuf_alt_p) = { "dout_shared2_div1",
1047 "dout_shared3_div1",
1048 "dout_shared4_div1",
1049 "dout_shared0_div2",
1050 "dout_shared1_div2",
1051 "dout_shared2_div2",
1052 "oscclk", "oscclk" };
1053 PNAME(mout_cmu_mux_dsp_noc_p) = { "dout_shared0_div1",
1054 "dout_shared1_div1",
1055 "dout_shared2_div1",
1056 "dout_shared3_div1",
1057 "dout_shared4_div1",
1058 "dout_shared0_div2",
1059 "dout_shared1_div2",
1060 "oscclk" };
1061 PNAME(mout_cmu_mux_dsu_switch_p) = { "dout_shared0_div1",
1062 "dout_shared1_div1",
1063 "dout_shared2_div1",
1064 "dout_shared3_div1",
1065 "dout_shared4_div1",
1066 "dout_shared0_div2",
1067 "oscclk", "oscclk" };
1068 PNAME(mout_cmu_mux_g3d_nocp_p) = { "dout_shared0_div2",
1069 "dout_shared1_div2",
1070 "dout_shared2_div2",
1071 "dout_shared4_div2" };
1072 PNAME(mout_cmu_mux_g3d_switch_p) = { "dout_shared0_div1",
1073 "dout_shared1_div1",
1074 "dout_shared2_div1",
1075 "dout_shared3_div1",
1076 "dout_shared4_div1",
1077 "dout_shared0_div2",
1078 "dout_shared1_div2",
1079 "dout_shared2_div2" };
1080 PNAME(mout_cmu_mux_gnpu_noc_p) = { "dout_shared0_div1",
1081 "dout_shared1_div1",
1082 "dout_shared2_div1",
1083 "dout_shared3_div1",
1084 "dout_shared4_div1",
1085 "dout_shared0_div2",
1086 "dout_shared1_div2",
1087 "oscclk" };
1088 PNAME(mout_cmu_mux_hsi0_dpgtc_p) = { "oscclk",
1089 "dout_shared0_div2",
1090 "dout_shared2_div2",
1091 "dout_shared4_div2" };
1092 PNAME(mout_cmu_mux_hsi0_dposc_p) = { "oscclk",
1093 "dout_shared2_div1" };
1094 PNAME(mout_cmu_mux_hsi0_noc_p) = { "dout_shared0_div2",
1095 "dout_shared2_div2",
1096 "dout_shared3_div2",
1097 "dout_shared4_div2" };
1098 PNAME(mout_cmu_mux_hsi0_usb32drd_p) = { "oscclk",
1099 "dout_shared0_div2",
1100 "dout_shared2_div2",
1101 "dout_shared4_div2" };
1102 PNAME(mout_cmu_mux_ufs_mmc_card_p) = { "oscclk",
1103 "dout_shared2_div1",
1104 "dout_mmc_div1",
1105 "dout_shared0_div2" };
1106 PNAME(mout_cmu_mux_hsi1_noc_p) = { "dout_shared0_div2",
1107 "dout_shared1_div2",
1108 "dout_shared2_div2",
1109 "dout_shared4_div2" };
1110 PNAME(mout_cmu_mux_hsi1_pcie_p) = { "oscclk",
1111 "dout_shared2_div1" };
1112 PNAME(mout_cmu_mux_ufs_ufs_embd_p) = { "oscclk",
1113 "dout_shared0_div2",
1114 "dout_shared2_div2",
1115 "dout_shared4_div2" };
1116 PNAME(mout_cmu_mux_lme_lme_p) = { "dout_shared2_div1",
1117 "dout_shared3_div1",
1118 "dout_shared4_div1",
1119 "dout_shared0_div2",
1120 "dout_shared1_div2",
1121 "dout_shared2_div2",
1122 "dout_shared3_div2",
1123 "oscclk" };
1124 PNAME(mout_cmu_mux_lme_noc_p) = { "dout_shared2_div1",
1125 "dout_shared3_div1",
1126 "dout_shared4_div1",
1127 "dout_shared0_div2",
1128 "dout_shared1_div2",
1129 "dout_shared2_div2",
1130 "dout_shared3_div2",
1131 "oscclk" };
1132 PNAME(mout_cmu_mux_m2m_noc_p) = { "dout_shared2_div1",
1133 "dout_shared3_div1",
1134 "dout_shared4_div1",
1135 "dout_shared0_div2",
1136 "dout_shared1_div2",
1137 "dout_shared2_div2",
1138 "dout_shared3_div2",
1139 "oscclk" };
1140 PNAME(mout_cmu_mux_mcsc_mcsc_p) = { "dout_shared2_div1",
1141 "dout_shared3_div1",
1142 "dout_shared4_div1",
1143 "dout_shared0_div2",
1144 "dout_shared1_div2",
1145 "dout_shared2_div2",
1146 "dout_shared3_div2",
1147 "oscclk" };
1148 PNAME(mout_cmu_mux_mcsc_noc_p) = { "dout_shared2_div1",
1149 "dout_shared3_div1",
1150 "dout_shared4_div1",
1151 "dout_shared0_div2",
1152 "dout_shared1_div2",
1153 "dout_shared2_div2",
1154 "dout_shared3_div2",
1155 "oscclk" };
1156 PNAME(mout_cmu_mux_mfc0_mfc0_p) = { "dout_shared2_div1",
1157 "dout_shared3_div1",
1158 "dout_shared4_div1",
1159 "dout_shared0_div2",
1160 "dout_shared1_div2",
1161 "dout_shared2_div2",
1162 "dout_shared3_div2",
1163 "oscclk" };
1164 PNAME(mout_cmu_mux_mfc0_wfd_p) = { "dout_shared0_div2",
1165 "dout_shared1_div2",
1166 "dout_shared2_div2",
1167 "dout_shared3_div2",
1168 "dout_shared4_div2",
1169 "oscclk", "oscclk",
1170 "oscclk" };
1171 PNAME(mout_cmu_mux_mfc1_mfc1_p) = { "dout_shared2_div1",
1172 "dout_shared3_div1",
1173 "dout_shared4_div1",
1174 "dout_shared0_div2",
1175 "dout_shared1_div2",
1176 "dout_shared2_div2",
1177 "dout_shared3_div2",
1178 "oscclk" };
1179 PNAME(mout_cmu_mux_mif_nocp_p) = { "dout_shared0_div2",
1180 "dout_shared1_div2",
1181 "dout_shared2_div2",
1182 "dout_shared4_div2" };
1183 PNAME(mout_cmu_mux_mif_switch_p) = { "dout_shared0_div1",
1184 "dout_shared1_div1",
1185 "dout_shared2_div1",
1186 "dout_shared3_div1",
1187 "dout_shared4_div1",
1188 "dout_shared0_div2",
1189 "mout_cmu_cp_mpll_clk_user",
1190 "dout_shared_mif_div1" };
1191 PNAME(mout_cmu_mux_nocl0_noc_p) = { "dout_shared0_div1",
1192 "dout_shared1_div1",
1193 "dout_shared2_div1",
1194 "dout_shared3_div1",
1195 "dout_shared4_div1",
1196 "dout_shared0_div2",
1197 "mout_cmu_cp_mpll_clk_d2_user",
1198 "dout_shared_mif_div2" };
1199 PNAME(mout_cmu_mux_nocl1a_noc_p) = { "dout_shared2_div1",
1200 "dout_shared3_div1",
1201 "dout_shared4_div1",
1202 "dout_shared0_div2",
1203 "dout_shared1_div2",
1204 "dout_shared2_div2",
1205 "dout_shared3_div2",
1206 "dout_shared4_div2" };
1207 PNAME(mout_cmu_mux_nocl1b_noc0_p) = { "dout_shared2_div1",
1208 "dout_shared3_div1",
1209 "dout_shared4_div1",
1210 "dout_shared0_div2",
1211 "dout_shared1_div2",
1212 "dout_shared2_div2",
1213 "dout_shared3_div2",
1214 "dout_shared4_div2" };
1215 PNAME(mout_cmu_mux_nocl1b_noc1_p) = { "dout_shared4_div1",
1216 "dout_shared0_div2",
1217 "dout_shared1_div2",
1218 "dout_shared2_div2" };
1219 PNAME(mout_cmu_mux_nocl1c_noc_p) = { "dout_shared2_div1",
1220 "dout_shared3_div1",
1221 "dout_shared4_div1",
1222 "dout_shared0_div2",
1223 "dout_shared1_div2",
1224 "dout_shared2_div2",
1225 "dout_shared3_div2",
1226 "dout_shared4_div2" };
1227 PNAME(mout_cmu_mux_peric0_ip0_p) = { "dout_shared0_div2",
1228 "dout_shared1_div2",
1229 "dout_shared2_div2",
1230 "dout_shared4_div2" };
1231 PNAME(mout_cmu_mux_peric0_ip1_p) = { "dout_shared0_div2",
1232 "dout_shared1_div2",
1233 "dout_shared2_div2",
1234 "dout_shared4_div2" };
1235 PNAME(mout_cmu_mux_peric0_noc_p) = { "dout_shared0_div2",
1236 "dout_shared2_div2" };
1237 PNAME(mout_cmu_mux_peric1_ip0_p) = { "dout_shared0_div2",
1238 "dout_shared1_div2",
1239 "dout_shared2_div2",
1240 "dout_shared4_div2" };
1241 PNAME(mout_cmu_mux_peric1_ip1_p) = { "dout_shared0_div2",
1242 "dout_shared1_div2",
1243 "dout_shared2_div2",
1244 "dout_shared4_div2" };
1245 PNAME(mout_cmu_mux_peric1_noc_p) = { "dout_shared0_div2",
1246 "dout_shared2_div2" };
1247 PNAME(mout_cmu_mux_peric2_ip0_p) = { "dout_shared0_div2",
1248 "dout_shared1_div2",
1249 "dout_shared2_div2",
1250 "dout_shared4_div2" };
1251 PNAME(mout_cmu_mux_peric2_ip1_p) = { "dout_shared0_div2",
1252 "dout_shared1_div2",
1253 "dout_shared2_div2",
1254 "dout_shared4_div2" };
1255 PNAME(mout_cmu_mux_peric2_noc_p) = { "dout_shared0_div2",
1256 "dout_shared2_div2" };
1257 PNAME(mout_cmu_mux_peris_gic_p) = { "dout_shared0_div2",
1258 "dout_shared2_div2" };
1259 PNAME(mout_cmu_mux_peris_noc_p) = { "dout_shared0_div2",
1260 "dout_shared2_div2" };
1261 PNAME(mout_cmu_mux_sdma_noc_p) = { "dout_shared0_div1",
1262 "dout_shared1_div1",
1263 "dout_shared2_div1",
1264 "dout_shared3_div1",
1265 "dout_shared4_div1",
1266 "dout_shared0_div2",
1267 "dout_shared1_div2",
1268 "oscclk" };
1269 PNAME(mout_cmu_mux_ssp_noc_p) = { "dout_shared0_div2",
1270 "dout_shared1_div2",
1271 "dout_shared2_div2",
1272 "dout_shared4_div2" };
1273 PNAME(mout_cmu_mux_vts_dmic_p) = { "dout_shared3_div1",
1274 "dout_shared4_div1",
1275 "dout_shared0_div2",
1276 "dout_shared1_div2" };
1277 PNAME(mout_cmu_mux_yuvp_noc_p) = { "dout_shared2_div1",
1278 "dout_shared3_div1",
1279 "dout_shared4_div1",
1280 "dout_shared0_div2",
1281 "dout_shared1_div2",
1282 "dout_shared2_div2",
1283 "dout_shared3_div2",
1284 "oscclk" };
1285 PNAME(mout_cmu_mux_cmu_cmuref_p) = { "oscclk",
1286 "dout_cmu_boost" };
1287 PNAME(mout_cmu_mux_cp_hispeedy_clk_p) = { "dout_shared2_div1",
1288 "dout_shared3_div1" };
1289 PNAME(mout_cmu_mux_cp_shared0_clk_p) = { "dout_shared0_div1",
1290 "dout_shared1_div1",
1291 "dout_shared2_div1",
1292 "dout_shared3_div1" };
1293 PNAME(mout_cmu_mux_cp_shared1_clk_p) = { "dout_shared4_div1",
1294 "dout_shared0_div2",
1295 "dout_shared1_div2",
1296 "dout_shared2_div2" };
1297 PNAME(mout_cmu_mux_cp_shared2_clk_p) = { "dout_shared2_div1",
1298 "dout_shared3_div1",
1299 "dout_shared4_div1",
1300 "dout_shared1_div2" };
1301 PNAME(mout_cmu_m2m_frc_p) = { "dout_shared2_div1",
1302 "dout_shared3_div1",
1303 "dout_shared4_div1",
1304 "dout_shared0_div2",
1305 "dout_shared1_div2",
1306 "dout_shared2_div2",
1307 "dout_shared3_div2",
1308 "oscclk" };
1309 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared2_div1",
1310 "dout_shared3_div1",
1311 "dout_shared4_div1",
1312 "dout_shared0_div2",
1313 "dout_shared1_div2",
1314 "dout_shared2_div2",
1315 "dout_shared3_div2",
1316 "oscclk" };
1317 PNAME(mout_cmu_mcsc_noc_p) = { "dout_shared2_div1",
1318 "dout_shared3_div1",
1319 "dout_shared4_div1",
1320 "dout_shared0_div2",
1321 "dout_shared1_div2",
1322 "dout_shared2_div2",
1323 "dout_shared3_div2",
1324 "oscclk" };
1325 PNAME(mout_cmu_mux_m2m_frc_p) = { "dout_shared2_div1",
1326 "dout_shared3_div1",
1327 "dout_shared4_div1",
1328 "dout_shared0_div2",
1329 "dout_shared1_div2",
1330 "dout_shared2_div2",
1331 "dout_shared3_div2",
1332 "oscclk" };
1333 PNAME(mout_cmu_mux_ufs_noc_p) = { "dout_shared0_div2",
1334 "dout_shared1_div2",
1335 "dout_shared2_div2",
1336 "dout_shared4_div2" };
1337
1338 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
1339 PLL(pll_4311, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
1340 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
1341 PLL(pll_4311, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
1342 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
1343 PLL(pll_4311, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
1344 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
1345 PLL(pll_4311, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
1346 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
1347 PLL(pll_4311, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
1348 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
1349 PLL(pll_4311, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
1350 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
1351 PLL(pll_4311, CLK_FOUT_SHARED_MIF_PLL, "fout_shared_mif_pll", "oscclk",
1352 PLL_LOCKTIME_PLL_SHARED_MIF, PLL_CON3_PLL_SHARED_MIF, NULL),
1353 };
1354
1355 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
1356 MUX(CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER, "mout_cmu_cp_mpll_clk_d2_user",
1357 mout_cmu_cp_mpll_clk_d2_user_parents,
1358 PLL_CON0_MUX_CP_MPLL_CLK_D2_USER, 4, 1),
1359 MUX(CLK_MOUT_CMU_CP_MPLL_CLK_USER, "mout_cmu_cp_mpll_clk_user",
1360 mout_cmu_cp_mpll_clk_user_parents, PLL_CON0_MUX_CP_MPLL_CLK_USER,
1361 4, 1),
1362 MUX(CLK_MOUT_CMU_AUD_AUDIF0, "mout_cmu_aud_audif0",
1363 mout_cmu_aud_audif0_p, CLK_CON_MUX_CLKCMU_AUD_AUDIF0, 0, 3),
1364 MUX(CLK_MOUT_CMU_AUD_AUDIF1, "mout_cmu_aud_audif1",
1365 mout_cmu_aud_audif1_p, CLK_CON_MUX_CLKCMU_AUD_AUDIF1, 0, 3),
1366 MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", mout_cmu_aud_cpu_p,
1367 CLK_CON_MUX_CLKCMU_AUD_CPU, 0, 3),
1368 MUX(CLK_MOUT_CMU_CPUCL0_DBG_NOC, "mout_cmu_cpucl0_dbg_noc",
1369 mout_cmu_cpucl0_dbg_noc_p, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC,
1370 0, 2),
1371 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
1372 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, 0, 3),
1373 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
1374 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, 0, 3),
1375 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
1376 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, 0, 3),
1377 MUX(CLK_MOUT_CMU_DNC_NOC, "mout_cmu_dnc_noc", mout_cmu_dnc_noc_p,
1378 CLK_CON_MUX_CLKCMU_DNC_NOC, 0, 3),
1379 MUX(CLK_MOUT_CMU_DPUB_NOC, "mout_cmu_dpub_noc", mout_cmu_dpub_noc_p,
1380 CLK_CON_MUX_CLKCMU_DPUB_NOC, 0, 1),
1381 MUX(CLK_MOUT_CMU_DPUF_NOC, "mout_cmu_dpuf_noc", mout_cmu_dpuf_noc_p,
1382 CLK_CON_MUX_CLKCMU_DPUF_NOC, 0, 1),
1383 MUX(CLK_MOUT_CMU_DSP_NOC, "mout_cmu_dsp_noc", mout_cmu_dsp_noc_p,
1384 CLK_CON_MUX_CLKCMU_DSP_NOC, 0, 3),
1385 MUX(CLK_MOUT_CMU_DSU_SWITCH, "mout_cmu_dsu_switch",
1386 mout_cmu_dsu_switch_p, CLK_CON_MUX_CLKCMU_DSU_SWITCH, 0, 3),
1387 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch",
1388 mout_cmu_g3d_switch_p, CLK_CON_MUX_CLKCMU_G3D_SWITCH, 0, 3),
1389 MUX(CLK_MOUT_CMU_GNPU_NOC, "mout_cmu_gnpu_noc", mout_cmu_gnpu_noc_p,
1390 CLK_CON_MUX_CLKCMU_GNPU_NOC, 0, 3),
1391 MUX(CLK_MOUT_CMU_UFS_MMC_CARD, "mout_cmu_ufs_mmc_card",
1392 mout_cmu_ufs_mmc_card_p, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD, 0, 2),
1393 MUX(CLK_MOUT_CMU_M2M_NOC, "mout_cmu_m2m_noc", mout_cmu_m2m_noc_p,
1394 CLK_CON_MUX_CLKCMU_M2M_NOC, 0, 3),
1395 MUX(CLK_MOUT_CMU_NOCL0_NOC, "mout_cmu_nocl0_noc", mout_cmu_nocl0_noc_p,
1396 CLK_CON_MUX_CLKCMU_NOCL0_NOC, 0, 3),
1397 MUX(CLK_MOUT_CMU_NOCL1A_NOC, "mout_cmu_nocl1a_noc",
1398 mout_cmu_nocl1a_noc_p, CLK_CON_MUX_CLKCMU_NOCL1A_NOC, 0, 3),
1399 MUX(CLK_MOUT_CMU_NOCL1B_NOC0, "mout_cmu_nocl1b_noc0",
1400 mout_cmu_nocl1b_noc0_p, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0, 0, 3),
1401 MUX(CLK_MOUT_CMU_NOCL1C_NOC, "mout_cmu_nocl1c_noc",
1402 mout_cmu_nocl1c_noc_p, CLK_CON_MUX_CLKCMU_NOCL1C_NOC, 0, 3),
1403 MUX(CLK_MOUT_CMU_SDMA_NOC, "mout_cmu_sdma_noc", mout_cmu_sdma_noc_p,
1404 CLK_CON_MUX_CLKCMU_SDMA_NOC, 0, 3),
1405 MUX(CLK_MOUT_CMU_CP_HISPEEDY_CLK, "mout_cmu_cp_hispeedy_clk",
1406 mout_cmu_cp_hispeedy_clk_p, CLK_CON_MUX_CP_HISPEEDY_CLK, 0, 1),
1407 MUX(CLK_MOUT_CMU_CP_SHARED0_CLK, "mout_cmu_cp_shared0_clk",
1408 mout_cmu_cp_shared0_clk_p, CLK_CON_MUX_CP_SHARED0_CLK, 0, 2),
1409 MUX(CLK_MOUT_CMU_CP_SHARED2_CLK, "mout_cmu_cp_shared2_clk",
1410 mout_cmu_cp_shared2_clk_p, CLK_CON_MUX_CP_SHARED2_CLK, 0, 2),
1411 MUX(CLK_MOUT_CMU_MUX_ALIVE_NOC, "mout_cmu_mux_alive_noc",
1412 mout_cmu_mux_alive_noc_p, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC, 0, 1),
1413 MUX(CLK_MOUT_CMU_MUX_AUD_AUDIF0, "mout_cmu_mux_aud_audif0",
1414 mout_cmu_mux_aud_audif0_p, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0,
1415 0, 3),
1416 MUX(CLK_MOUT_CMU_MUX_AUD_AUDIF1, "mout_cmu_mux_aud_audif1",
1417 mout_cmu_mux_aud_audif1_p, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1,
1418 0, 3),
1419 MUX(CLK_MOUT_CMU_MUX_AUD_CPU, "mout_cmu_mux_aud_cpu",
1420 mout_cmu_mux_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
1421 MUX(CLK_MOUT_CMU_MUX_AUD_NOC, "mout_cmu_mux_aud_noc",
1422 mout_cmu_mux_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 3),
1423 MUX(CLK_MOUT_CMU_MUX_BRP_NOC, "mout_cmu_mux_brp_noc",
1424 mout_cmu_mux_brp_noc_p, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC, 0, 3),
1425 MUX(CLK_MOUT_CMU_MUX_CIS_CLK0, "mout_cmu_mux_cis_clk0",
1426 mout_cmu_mux_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
1427 MUX(CLK_MOUT_CMU_MUX_CIS_CLK1, "mout_cmu_mux_cis_clk1",
1428 mout_cmu_mux_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
1429 MUX(CLK_MOUT_CMU_MUX_CIS_CLK2, "mout_cmu_mux_cis_clk2",
1430 mout_cmu_mux_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
1431 MUX(CLK_MOUT_CMU_MUX_CIS_CLK3, "mout_cmu_mux_cis_clk3",
1432 mout_cmu_mux_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
1433 MUX(CLK_MOUT_CMU_MUX_CIS_CLK4, "mout_cmu_mux_cis_clk4",
1434 mout_cmu_mux_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1),
1435 MUX(CLK_MOUT_CMU_MUX_CIS_CLK5, "mout_cmu_mux_cis_clk5",
1436 mout_cmu_mux_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1),
1437 MUX(CLK_MOUT_CMU_MUX_CIS_CLK6, "mout_cmu_mux_cis_clk6",
1438 mout_cmu_mux_cis_clk6_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 1),
1439 MUX(CLK_MOUT_CMU_MUX_CIS_CLK7, "mout_cmu_mux_cis_clk7",
1440 mout_cmu_mux_cis_clk7_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 1),
1441 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST, "mout_cmu_mux_cmu_boost",
1442 mout_cmu_mux_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
1443 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_CAM, "mout_cmu_mux_cmu_boost_cam",
1444 mout_cmu_mux_cmu_boost_cam_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM,
1445 0, 2),
1446 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_CPU, "mout_cmu_mux_cmu_boost_cpu",
1447 mout_cmu_mux_cmu_boost_cpu_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
1448 0, 2),
1449 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_MIF, "mout_cmu_mux_cmu_boost_mif",
1450 mout_cmu_mux_cmu_boost_mif_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF,
1451 0, 2),
1452 MUX(CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC, "mout_cmu_mux_cpucl0_dbg_noc",
1453 mout_cmu_mux_cpucl0_dbg_noc_p,
1454 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC, 0, 2),
1455 MUX(CLK_MOUT_CMU_MUX_CPUCL0_NOCP, "mout_cmu_mux_cpucl0_nocp",
1456 mout_cmu_mux_cpucl0_nocp_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP,
1457 0, 2),
1458 MUX(CLK_MOUT_CMU_MUX_CPUCL0_SWITCH, "mout_cmu_mux_cpucl0_switch",
1459 mout_cmu_mux_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
1460 0, 3),
1461 MUX(CLK_MOUT_CMU_MUX_CPUCL1_SWITCH, "mout_cmu_mux_cpucl1_switch",
1462 mout_cmu_mux_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
1463 0, 3),
1464 MUX(CLK_MOUT_CMU_MUX_CPUCL2_SWITCH, "mout_cmu_mux_cpucl2_switch",
1465 mout_cmu_mux_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
1466 0, 3),
1467 MUX(CLK_MOUT_CMU_MUX_CSIS_DCPHY, "mout_cmu_mux_csis_dcphy",
1468 mout_cmu_mux_csis_dcphy_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY,
1469 0, 2),
1470 MUX(CLK_MOUT_CMU_MUX_CSIS_NOC, "mout_cmu_mux_csis_noc",
1471 mout_cmu_mux_csis_noc_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, 0, 3),
1472 MUX(CLK_MOUT_CMU_MUX_CSIS_OIS_MCU, "mout_cmu_mux_csis_ois_mcu",
1473 mout_cmu_mux_csis_ois_mcu_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
1474 0, 1),
1475 MUX(CLK_MOUT_CMU_MUX_CSTAT_NOC, "mout_cmu_mux_cstat_noc",
1476 mout_cmu_mux_cstat_noc_p, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC, 0, 3),
1477 MUX(CLK_MOUT_CMU_MUX_DNC_NOC, "mout_cmu_mux_dnc_noc",
1478 mout_cmu_mux_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
1479 MUX(CLK_MOUT_CMU_MUX_DPUB, "mout_cmu_mux_dpub", mout_cmu_mux_dpub_p,
1480 CLK_CON_MUX_MUX_CLKCMU_DPUB, 0, 3),
1481 MUX(CLK_MOUT_CMU_MUX_DPUB_ALT, "mout_cmu_mux_dpub_alt",
1482 mout_cmu_mux_dpub_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT, 0, 3),
1483 MUX(CLK_MOUT_CMU_MUX_DPUB_DSIM, "mout_cmu_mux_dpub_dsim",
1484 mout_cmu_mux_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 2),
1485 MUX(CLK_MOUT_CMU_MUX_DPUF, "mout_cmu_mux_dpuf", mout_cmu_mux_dpuf_p,
1486 CLK_CON_MUX_MUX_CLKCMU_DPUF, 0, 3),
1487 MUX(CLK_MOUT_CMU_MUX_DPUF_ALT, "mout_cmu_mux_dpuf_alt",
1488 mout_cmu_mux_dpuf_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT, 0, 3),
1489 MUX(CLK_MOUT_CMU_MUX_DSP_NOC, "mout_cmu_mux_dsp_noc",
1490 mout_cmu_mux_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
1491 MUX(CLK_MOUT_CMU_MUX_DSU_SWITCH, "mout_cmu_mux_dsu_switch",
1492 mout_cmu_mux_dsu_switch_p, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH,
1493 0, 3),
1494 MUX(CLK_MOUT_CMU_MUX_G3D_NOCP, "mout_cmu_mux_g3d_nocp",
1495 mout_cmu_mux_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
1496 MUX(CLK_MOUT_CMU_MUX_G3D_SWITCH, "mout_cmu_mux_g3d_switch",
1497 mout_cmu_mux_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
1498 0, 3),
1499 MUX(CLK_MOUT_CMU_MUX_GNPU_NOC, "mout_cmu_mux_gnpu_noc",
1500 mout_cmu_mux_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
1501 MUX(CLK_MOUT_CMU_MUX_HSI0_DPGTC, "mout_cmu_mux_hsi0_dpgtc",
1502 mout_cmu_mux_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
1503 0, 2),
1504 MUX(CLK_MOUT_CMU_MUX_HSI0_DPOSC, "mout_cmu_mux_hsi0_dposc",
1505 mout_cmu_mux_hsi0_dposc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC,
1506 0, 1),
1507 MUX(CLK_MOUT_CMU_MUX_HSI0_NOC, "mout_cmu_mux_hsi0_noc",
1508 mout_cmu_mux_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
1509 MUX(CLK_MOUT_CMU_MUX_HSI0_USB32DRD, "mout_cmu_mux_hsi0_usb32drd",
1510 mout_cmu_mux_hsi0_usb32drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD,
1511 0, 2),
1512 MUX(CLK_MOUT_CMU_MUX_UFS_MMC_CARD, "mout_cmu_mux_ufs_mmc_card",
1513 mout_cmu_mux_ufs_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD,
1514 0, 2),
1515 MUX(CLK_MOUT_CMU_MUX_HSI1_NOC, "mout_cmu_mux_hsi1_noc",
1516 mout_cmu_mux_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 0, 2),
1517 MUX(CLK_MOUT_CMU_MUX_HSI1_PCIE, "mout_cmu_mux_hsi1_pcie",
1518 mout_cmu_mux_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
1519 MUX(CLK_MOUT_CMU_MUX_UFS_UFS_EMBD, "mout_cmu_mux_ufs_ufs_embd",
1520 mout_cmu_mux_ufs_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD,
1521 0, 2),
1522 MUX(CLK_MOUT_CMU_MUX_LME_LME, "mout_cmu_mux_lme_lme",
1523 mout_cmu_mux_lme_lme_p, CLK_CON_MUX_MUX_CLKCMU_LME_LME, 0, 3),
1524 MUX(CLK_MOUT_CMU_MUX_LME_NOC, "mout_cmu_mux_lme_noc",
1525 mout_cmu_mux_lme_noc_p, CLK_CON_MUX_MUX_CLKCMU_LME_NOC, 0, 3),
1526 MUX(CLK_MOUT_CMU_MUX_M2M_NOC, "mout_cmu_mux_m2m_noc",
1527 mout_cmu_mux_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 3),
1528 MUX(CLK_MOUT_CMU_MUX_MCSC_MCSC, "mout_cmu_mux_mcsc_mcsc",
1529 mout_cmu_mux_mcsc_mcsc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1530 MUX(CLK_MOUT_CMU_MUX_MCSC_NOC, "mout_cmu_mux_mcsc_noc",
1531 mout_cmu_mux_mcsc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC, 0, 3),
1532 MUX(CLK_MOUT_CMU_MUX_MFC0_MFC0, "mout_cmu_mux_mfc0_mfc0",
1533 mout_cmu_mux_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 3),
1534 MUX(CLK_MOUT_CMU_MUX_MFC0_WFD, "mout_cmu_mux_mfc0_wfd",
1535 mout_cmu_mux_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 3),
1536 MUX(CLK_MOUT_CMU_MUX_MFC1_MFC1, "mout_cmu_mux_mfc1_mfc1",
1537 mout_cmu_mux_mfc1_mfc1_p, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1, 0, 3),
1538 MUX(CLK_MOUT_CMU_MUX_MIF_NOCP, "mout_cmu_mux_mif_nocp",
1539 mout_cmu_mux_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
1540 MUX(CLK_MOUT_CMU_MUX_MIF_SWITCH, "mout_cmu_mux_mif_switch",
1541 mout_cmu_mux_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
1542 0, 3),
1543 MUX(CLK_MOUT_CMU_MUX_NOCL0_NOC, "mout_cmu_mux_nocl0_noc",
1544 mout_cmu_mux_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
1545 MUX(CLK_MOUT_CMU_MUX_NOCL1A_NOC, "mout_cmu_mux_nocl1a_noc",
1546 mout_cmu_mux_nocl1a_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC,
1547 0, 3),
1548 MUX(CLK_MOUT_CMU_MUX_NOCL1B_NOC0, "mout_cmu_mux_nocl1b_noc0",
1549 mout_cmu_mux_nocl1b_noc0_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0,
1550 0, 3),
1551 MUX(CLK_MOUT_CMU_MUX_NOCL1B_NOC1, "mout_cmu_mux_nocl1b_noc1",
1552 mout_cmu_mux_nocl1b_noc1_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1,
1553 0, 2),
1554 MUX(CLK_MOUT_CMU_MUX_NOCL1C_NOC, "mout_cmu_mux_nocl1c_noc",
1555 mout_cmu_mux_nocl1c_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC,
1556 0, 3),
1557 MUX(CLK_MOUT_CMU_MUX_PERIC0_IP0, "mout_cmu_mux_peric0_ip0",
1558 mout_cmu_mux_peric0_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0,
1559 0, 2),
1560 MUX(CLK_MOUT_CMU_MUX_PERIC0_IP1, "mout_cmu_mux_peric0_ip1",
1561 mout_cmu_mux_peric0_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1,
1562 0, 2),
1563 MUX(CLK_MOUT_CMU_MUX_PERIC0_NOC, "mout_cmu_mux_peric0_noc",
1564 mout_cmu_mux_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
1565 0, 1),
1566 MUX(CLK_MOUT_CMU_MUX_PERIC1_IP0, "mout_cmu_mux_peric1_ip0",
1567 mout_cmu_mux_peric1_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0,
1568 0, 2),
1569 MUX(CLK_MOUT_CMU_MUX_PERIC1_IP1, "mout_cmu_mux_peric1_ip1",
1570 mout_cmu_mux_peric1_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1,
1571 0, 2),
1572 MUX(CLK_MOUT_CMU_MUX_PERIC1_NOC, "mout_cmu_mux_peric1_noc",
1573 mout_cmu_mux_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
1574 0, 1),
1575 MUX(CLK_MOUT_CMU_MUX_PERIC2_IP0, "mout_cmu_mux_peric2_ip0",
1576 mout_cmu_mux_peric2_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0,
1577 0, 2),
1578 MUX(CLK_MOUT_CMU_MUX_PERIC2_IP1, "mout_cmu_mux_peric2_ip1",
1579 mout_cmu_mux_peric2_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1,
1580 0, 2),
1581 MUX(CLK_MOUT_CMU_MUX_PERIC2_NOC, "mout_cmu_mux_peric2_noc",
1582 mout_cmu_mux_peric2_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC,
1583 0, 1),
1584 MUX(CLK_MOUT_CMU_MUX_PERIS_GIC, "mout_cmu_mux_peris_gic",
1585 mout_cmu_mux_peris_gic_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC, 0, 1),
1586 MUX(CLK_MOUT_CMU_MUX_PERIS_NOC, "mout_cmu_mux_peris_noc",
1587 mout_cmu_mux_peris_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC, 0, 1),
1588 MUX(CLK_MOUT_CMU_MUX_SDMA_NOC, "mout_cmu_mux_sdma_noc",
1589 mout_cmu_mux_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
1590 MUX(CLK_MOUT_CMU_MUX_SSP_NOC, "mout_cmu_mux_ssp_noc",
1591 mout_cmu_mux_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
1592 MUX(CLK_MOUT_CMU_MUX_VTS_DMIC, "mout_cmu_mux_vts_dmic",
1593 mout_cmu_mux_vts_dmic_p, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC, 0, 2),
1594 MUX(CLK_MOUT_CMU_MUX_YUVP_NOC, "mout_cmu_mux_yuvp_noc",
1595 mout_cmu_mux_yuvp_noc_p, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC, 0, 3),
1596 MUX(CLK_MOUT_CMU_MUX_CMU_CMUREF, "mout_cmu_mux_cmu_cmuref",
1597 mout_cmu_mux_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
1598 MUX(CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK, "mout_cmu_mux_cp_hispeedy_clk",
1599 mout_cmu_mux_cp_hispeedy_clk_p, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK,
1600 0, 1),
1601 MUX(CLK_MOUT_CMU_MUX_CP_SHARED0_CLK, "mout_cmu_mux_cp_shared0_clk",
1602 mout_cmu_mux_cp_shared0_clk_p, CLK_CON_MUX_MUX_CP_SHARED0_CLK,
1603 0, 2),
1604 MUX(CLK_MOUT_CMU_MUX_CP_SHARED1_CLK, "mout_cmu_mux_cp_shared1_clk",
1605 mout_cmu_mux_cp_shared1_clk_p, CLK_CON_MUX_MUX_CP_SHARED1_CLK,
1606 0, 2),
1607 MUX(CLK_MOUT_CMU_MUX_CP_SHARED2_CLK, "mout_cmu_mux_cp_shared2_clk",
1608 mout_cmu_mux_cp_shared2_clk_p, CLK_CON_MUX_MUX_CP_SHARED2_CLK,
1609 0, 2),
1610 MUX(CLK_MOUT_CMU_M2M_FRC, "mout_cmu_m2m_frc", mout_cmu_m2m_frc_p,
1611 CLK_CON_MUX_CLKCMU_M2M_FRC, 0, 3),
1612 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
1613 CLK_CON_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1614 MUX(CLK_MOUT_CMU_MCSC_NOC, "mout_cmu_mcsc_noc", mout_cmu_mcsc_noc_p,
1615 CLK_CON_MUX_CLKCMU_MCSC_NOC, 0, 3),
1616 MUX(CLK_MOUT_CMU_MUX_M2M_FRC, "mout_cmu_mux_m2m_frc",
1617 mout_cmu_mux_m2m_frc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC, 0, 3),
1618 MUX(CLK_MOUT_CMU_MUX_UFS_NOC, "mout_cmu_mux_ufs_noc",
1619 mout_cmu_mux_ufs_noc_p, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC, 0, 2),
1620 };
1621
1622 static const struct samsung_div_clock top_div_clks[] __initconst = {
1623 DIV(CLK_DOUT_CMU_ALIVE_NOC, "dout_cmu_alive_noc",
1624 "mout_cmu_mux_alive_noc", CLK_CON_DIV_CLKCMU_ALIVE_NOC, 0, 2),
1625 DIV(CLK_DOUT_CMU_AUD_NOC, "dout_cmu_aud_noc", "mout_cmu_mux_aud_noc",
1626 CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
1627 DIV(CLK_DOUT_CMU_BRP_NOC, "dout_cmu_brp_noc", "mout_cmu_mux_brp_noc",
1628 CLK_CON_DIV_CLKCMU_BRP_NOC, 0, 4),
1629 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost",
1630 "mout_cmu_mux_cmu_boost", CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 3),
1631 DIV(CLK_DOUT_CMU_CMU_BOOST_CAM, "dout_cmu_cmu_boost_cam",
1632 "mout_cmu_mux_cmu_boost_cam", CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM,
1633 0, 3),
1634 DIV(CLK_DOUT_CMU_CMU_BOOST_CPU, "dout_cmu_cmu_boost_cpu",
1635 "mout_cmu_mux_cmu_boost_cpu", CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
1636 0, 3),
1637 DIV(CLK_DOUT_CMU_CMU_BOOST_MIF, "dout_cmu_cmu_boost_mif",
1638 "mout_cmu_mux_cmu_boost_mif", CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF,
1639 0, 3),
1640 DIV(CLK_DOUT_CMU_CPUCL0_NOCP, "dout_cmu_cpucl0_nocp",
1641 "mout_cmu_mux_cpucl0_nocp", CLK_CON_DIV_CLKCMU_CPUCL0_NOCP, 0, 4),
1642 DIV(CLK_DOUT_CMU_CSIS_DCPHY, "dout_cmu_csis_dcphy",
1643 "mout_cmu_mux_csis_dcphy", CLK_CON_DIV_CLKCMU_CSIS_DCPHY, 0, 4),
1644 DIV(CLK_DOUT_CMU_CSIS_NOC, "dout_cmu_csis_noc",
1645 "mout_cmu_mux_csis_noc", CLK_CON_DIV_CLKCMU_CSIS_NOC, 0, 4),
1646 DIV(CLK_DOUT_CMU_CSIS_OIS_MCU, "dout_cmu_csis_ois_mcu",
1647 "mout_cmu_mux_csis_ois_mcu", CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
1648 0, 4),
1649 DIV(CLK_DOUT_CMU_CSTAT_NOC, "dout_cmu_cstat_noc",
1650 "mout_cmu_mux_cstat_noc", CLK_CON_DIV_CLKCMU_CSTAT_NOC, 0, 4),
1651 DIV(CLK_DOUT_CMU_DPUB_DSIM, "dout_cmu_dpub_dsim",
1652 "mout_cmu_mux_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
1653 DIV(CLK_DOUT_CMU_LME_LME, "dout_cmu_lme_lme", "mout_cmu_mux_lme_lme",
1654 CLK_CON_DIV_CLKCMU_LME_LME, 0, 4),
1655 DIV(CLK_DOUT_CMU_G3D_NOCP, "dout_cmu_g3d_nocp",
1656 "mout_cmu_mux_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
1657 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc",
1658 "mout_cmu_mux_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
1659 DIV(CLK_DOUT_CMU_HSI0_DPOSC, "dout_cmu_hsi0_dposc",
1660 "mout_cmu_mux_hsi0_dposc", CLK_CON_DIV_CLKCMU_HSI0_DPOSC, 0, 5),
1661 DIV(CLK_DOUT_CMU_HSI0_NOC, "dout_cmu_hsi0_noc",
1662 "mout_cmu_mux_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
1663 DIV(CLK_DOUT_CMU_HSI0_USB32DRD, "dout_cmu_hsi0_usb32drd",
1664 "mout_cmu_mux_hsi0_usb32drd", CLK_CON_DIV_CLKCMU_HSI0_USB32DRD,
1665 0, 5),
1666 DIV(CLK_DOUT_CMU_HSI1_NOC, "dout_cmu_hsi1_noc",
1667 "mout_cmu_mux_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
1668 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie",
1669 "mout_cmu_mux_hsi1_pcie", CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 8),
1670 DIV(CLK_DOUT_CMU_UFS_UFS_EMBD, "dout_cmu_ufs_ufs_embd",
1671 "mout_cmu_mux_ufs_ufs_embd", CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD,
1672 0, 4),
1673 DIV(CLK_DOUT_CMU_LME_NOC, "dout_cmu_lme_noc", "mout_cmu_mux_lme_noc",
1674 CLK_CON_DIV_CLKCMU_LME_NOC, 0, 4),
1675 DIV(CLK_DOUT_CMU_MFC0_MFC0, "dout_cmu_mfc0_mfc0",
1676 "mout_cmu_mux_mfc0_mfc0", CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0, 4),
1677 DIV(CLK_DOUT_CMU_MFC0_WFD, "dout_cmu_mfc0_wfd",
1678 "mout_cmu_mux_mfc0_wfd", CLK_CON_DIV_CLKCMU_MFC0_WFD, 0, 4),
1679 DIV(CLK_DOUT_CMU_MFC1_MFC1, "dout_cmu_mfc1_mfc1",
1680 "mout_cmu_mux_mfc1_mfc1", CLK_CON_DIV_CLKCMU_MFC1_MFC1, 0, 4),
1681 DIV(CLK_DOUT_CMU_MIF_NOCP, "dout_cmu_mif_nocp",
1682 "mout_cmu_mux_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
1683 DIV(CLK_DOUT_CMU_NOCL1B_NOC1, "dout_cmu_nocl1b_noc1",
1684 "mout_cmu_mux_nocl1b_noc1", CLK_CON_DIV_CLKCMU_NOCL1B_NOC1, 0, 4),
1685 DIV(CLK_DOUT_CMU_PERIC0_IP0, "dout_cmu_peric0_ip0",
1686 "mout_cmu_mux_peric0_ip0", CLK_CON_DIV_CLKCMU_PERIC0_IP0, 0, 4),
1687 DIV(CLK_DOUT_CMU_PERIC0_IP1, "dout_cmu_peric0_ip1",
1688 "mout_cmu_mux_peric0_ip1", CLK_CON_DIV_CLKCMU_PERIC0_IP1, 0, 4),
1689 DIV(CLK_DOUT_CMU_PERIC0_NOC, "dout_cmu_peric0_noc",
1690 "mout_cmu_mux_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
1691 DIV(CLK_DOUT_CMU_PERIC1_IP0, "dout_cmu_peric1_ip0",
1692 "mout_cmu_mux_peric1_ip0", CLK_CON_DIV_CLKCMU_PERIC1_IP0, 0, 4),
1693 DIV(CLK_DOUT_CMU_PERIC1_IP1, "dout_cmu_peric1_ip1",
1694 "mout_cmu_mux_peric1_ip1", CLK_CON_DIV_CLKCMU_PERIC1_IP1, 0, 4),
1695 DIV(CLK_DOUT_CMU_PERIC1_NOC, "dout_cmu_peric1_noc",
1696 "mout_cmu_mux_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
1697 DIV(CLK_DOUT_CMU_PERIC2_IP0, "dout_cmu_peric2_ip0",
1698 "mout_cmu_mux_peric2_ip0", CLK_CON_DIV_CLKCMU_PERIC2_IP0, 0, 4),
1699 DIV(CLK_DOUT_CMU_PERIC2_IP1, "dout_cmu_peric2_ip1",
1700 "mout_cmu_mux_peric2_ip1", CLK_CON_DIV_CLKCMU_PERIC2_IP1, 0, 4),
1701 DIV(CLK_DOUT_CMU_PERIC2_NOC, "dout_cmu_peric2_noc",
1702 "mout_cmu_mux_peric2_noc", CLK_CON_DIV_CLKCMU_PERIC2_NOC, 0, 4),
1703 DIV(CLK_DOUT_CMU_PERIS_GIC, "dout_cmu_peris_gic",
1704 "mout_cmu_mux_peris_gic", CLK_CON_DIV_CLKCMU_PERIS_GIC, 0, 4),
1705 DIV(CLK_DOUT_CMU_PERIS_NOC, "dout_cmu_peris_noc",
1706 "mout_cmu_mux_peris_noc", CLK_CON_DIV_CLKCMU_PERIS_NOC, 0, 4),
1707 DIV(CLK_DOUT_CMU_SSP_NOC, "dout_cmu_ssp_noc", "mout_cmu_mux_ssp_noc",
1708 CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
1709 DIV(CLK_DOUT_CMU_VTS_DMIC, "dout_cmu_vts_dmic",
1710 "mout_cmu_mux_vts_dmic", CLK_CON_DIV_CLKCMU_VTS_DMIC, 0, 6),
1711 DIV(CLK_DOUT_CMU_YUVP_NOC, "dout_cmu_yuvp_noc",
1712 "mout_cmu_mux_yuvp_noc", CLK_CON_DIV_CLKCMU_YUVP_NOC, 0, 4),
1713 DIV(CLK_DOUT_CMU_CP_SHARED1_CLK, "dout_cmu_cp_shared1_clk",
1714 "mout_cmu_mux_cp_shared1_clk", CLK_CON_DIV_CP_SHARED1_CLK, 0, 3),
1715 DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF0, "dout_cmu_div_aud_audif0",
1716 "mout_cmu_mux_aud_audif0", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0,
1717 0, 6),
1718 DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM, "dout_cmu_div_aud_audif0_sm",
1719 "mout_cmu_aud_audif0", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM, 0, 6),
1720 DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF1, "dout_cmu_div_aud_audif1",
1721 "mout_cmu_mux_aud_audif1", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1,
1722 0, 6),
1723 DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM, "dout_cmu_div_aud_audif1_sm",
1724 "mout_cmu_aud_audif1", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM, 0, 6),
1725 DIV(CLK_DOUT_CMU_DIV_AUD_CPU, "dout_cmu_div_aud_cpu",
1726 "mout_cmu_mux_aud_cpu", CLK_CON_DIV_DIV_CLKCMU_AUD_CPU, 0, 3),
1727 DIV(CLK_DOUT_CMU_DIV_AUD_CPU_SM, "dout_cmu_div_aud_cpu_sm",
1728 "mout_cmu_aud_cpu", CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM, 0, 3),
1729 DIV(CLK_DOUT_CMU_DIV_CIS_CLK0, "dout_cmu_div_cis_clk0",
1730 "mout_cmu_mux_cis_clk0", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0, 0, 5),
1731 DIV(CLK_DOUT_CMU_DIV_CIS_CLK1, "dout_cmu_div_cis_clk1",
1732 "mout_cmu_mux_cis_clk1", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1, 0, 5),
1733 DIV(CLK_DOUT_CMU_DIV_CIS_CLK2, "dout_cmu_div_cis_clk2",
1734 "mout_cmu_mux_cis_clk2", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2, 0, 5),
1735 DIV(CLK_DOUT_CMU_DIV_CIS_CLK3, "dout_cmu_div_cis_clk3",
1736 "mout_cmu_mux_cis_clk3", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3, 0, 5),
1737 DIV(CLK_DOUT_CMU_DIV_CIS_CLK4, "dout_cmu_div_cis_clk4",
1738 "mout_cmu_mux_cis_clk4", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4, 0, 5),
1739 DIV(CLK_DOUT_CMU_DIV_CIS_CLK5, "dout_cmu_div_cis_clk5",
1740 "mout_cmu_mux_cis_clk5", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5, 0, 5),
1741 DIV(CLK_DOUT_CMU_DIV_CIS_CLK6, "dout_cmu_div_cis_clk6",
1742 "mout_cmu_mux_cis_clk6", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6, 0, 5),
1743 DIV(CLK_DOUT_CMU_DIV_CIS_CLK7, "dout_cmu_div_cis_clk7",
1744 "mout_cmu_mux_cis_clk7", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7, 0, 5),
1745 DIV(CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC, "dout_cmu_div_cpucl0_dbg_noc",
1746 "mout_cmu_mux_cpucl0_dbg_noc",
1747 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC, 0, 4),
1748 DIV(CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM,
1749 "dout_cmu_div_cpucl0_dbg_noc_sm", "mout_cmu_cpucl0_dbg_noc",
1750 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM, 0, 4),
1751 DIV(CLK_DOUT_CMU_DIV_CPUCL0_SWITCH, "dout_cmu_div_cpucl0_switch",
1752 "mout_cmu_mux_cpucl0_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH,
1753 0, 3),
1754 DIV(CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM, "dout_cmu_div_cpucl0_switch_sm",
1755 "mout_cmu_cpucl0_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM,
1756 0, 3),
1757 DIV(CLK_DOUT_CMU_DIV_CPUCL1_SWITCH, "dout_cmu_div_cpucl1_switch",
1758 "mout_cmu_mux_cpucl1_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH,
1759 0, 3),
1760 DIV(CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM, "dout_cmu_div_cpucl1_switch_sm",
1761 "mout_cmu_cpucl1_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM,
1762 0, 3),
1763 DIV(CLK_DOUT_CMU_DIV_CPUCL2_SWITCH, "dout_cmu_div_cpucl2_switch",
1764 "mout_cmu_mux_cpucl2_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH,
1765 0, 3),
1766 DIV(CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM, "dout_cmu_div_cpucl2_switch_sm",
1767 "mout_cmu_cpucl2_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM,
1768 0, 3),
1769 DIV(CLK_DOUT_CMU_DIV_DNC_NOC, "dout_cmu_div_dnc_noc",
1770 "mout_cmu_mux_dnc_noc", CLK_CON_DIV_DIV_CLKCMU_DNC_NOC, 0, 4),
1771 DIV(CLK_DOUT_CMU_DIV_DNC_NOC_SM, "dout_cmu_div_dnc_noc_sm",
1772 "mout_cmu_dnc_noc", CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM, 0, 4),
1773 DIV(CLK_DOUT_CMU_DIV_DPUB, "dout_cmu_div_dpub", "mout_cmu_mux_dpub",
1774 CLK_CON_DIV_DIV_CLKCMU_DPUB, 0, 4),
1775 DIV(CLK_DOUT_CMU_DIV_DPUB_ALT, "dout_cmu_div_dpub_alt",
1776 "mout_cmu_mux_dpub_alt", CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT, 0, 4),
1777 DIV(CLK_DOUT_CMU_DIV_DPUF, "dout_cmu_div_dpuf", "mout_cmu_mux_dpuf",
1778 CLK_CON_DIV_DIV_CLKCMU_DPUF, 0, 4),
1779 DIV(CLK_DOUT_CMU_DIV_DPUF_ALT, "dout_cmu_div_dpuf_alt",
1780 "mout_cmu_mux_dpuf_alt", CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT, 0, 4),
1781 DIV(CLK_DOUT_CMU_DIV_DSP_NOC, "dout_cmu_div_dsp_noc",
1782 "mout_cmu_mux_dsp_noc", CLK_CON_DIV_DIV_CLKCMU_DSP_NOC, 0, 4),
1783 DIV(CLK_DOUT_CMU_DIV_DSP_NOC_SM, "dout_cmu_div_dsp_noc_sm",
1784 "mout_cmu_dsp_noc", CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM, 0, 4),
1785 DIV(CLK_DOUT_CMU_DIV_DSU_SWITCH, "dout_cmu_div_dsu_switch",
1786 "mout_cmu_mux_dsu_switch", CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH,
1787 0, 3),
1788 DIV(CLK_DOUT_CMU_DIV_DSU_SWITCH_SM, "dout_cmu_div_dsu_switch_sm",
1789 "mout_cmu_dsu_switch", CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM, 0, 3),
1790 DIV(CLK_DOUT_CMU_DIV_G3D_SWITCH, "dout_cmu_div_g3d_switch",
1791 "mout_cmu_mux_g3d_switch", CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH,
1792 0, 3),
1793 DIV(CLK_DOUT_CMU_DIV_G3D_SWITCH_SM, "dout_cmu_div_g3d_switch_sm",
1794 "mout_cmu_g3d_switch", CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM, 0, 3),
1795 DIV(CLK_DOUT_CMU_DIV_GNPU_NOC, "dout_cmu_div_gnpu_noc",
1796 "mout_cmu_mux_gnpu_noc", CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC, 0, 4),
1797 DIV(CLK_DOUT_CMU_DIV_GNPU_NOC_SM, "dout_cmu_div_gnpu_noc_sm",
1798 "mout_cmu_gnpu_noc", CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM, 0, 4),
1799 DIV(CLK_DOUT_CMU_DIV_UFS_MMC_CARD, "dout_cmu_div_ufs_mmc_card",
1800 "mout_cmu_mux_ufs_mmc_card", CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD,
1801 0, 9),
1802 DIV(CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM, "dout_cmu_div_ufs_mmc_card_sm",
1803 "mout_cmu_ufs_mmc_card", CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM,
1804 0, 9),
1805 DIV(CLK_DOUT_CMU_DIV_M2M_NOC, "dout_cmu_div_m2m_noc",
1806 "mout_cmu_mux_m2m_noc", CLK_CON_DIV_DIV_CLKCMU_M2M_NOC, 0, 4),
1807 DIV(CLK_DOUT_CMU_DIV_M2M_NOC_SM, "dout_cmu_div_m2m_noc_sm",
1808 "mout_cmu_m2m_noc", CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM, 0, 4),
1809 DIV(CLK_DOUT_CMU_DIV_NOCL0_NOC, "dout_cmu_div_nocl0_noc",
1810 "mout_cmu_mux_nocl0_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC,
1811 0, 4),
1812 DIV(CLK_DOUT_CMU_DIV_NOCL0_NOC_SM, "dout_cmu_div_nocl0_noc_sm",
1813 "mout_cmu_nocl0_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM, 0, 4),
1814 DIV(CLK_DOUT_CMU_DIV_NOCL1A_NOC, "dout_cmu_div_nocl1a_noc",
1815 "mout_cmu_mux_nocl1a_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC,
1816 0, 4),
1817 DIV(CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM, "dout_cmu_div_nocl1a_noc_sm",
1818 "mout_cmu_nocl1a_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM, 0, 4),
1819 DIV(CLK_DOUT_CMU_DIV_NOCL1B_NOC0, "dout_cmu_div_nocl1b_noc0",
1820 "mout_cmu_mux_nocl1b_noc0", CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0,
1821 0, 4),
1822 DIV(CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM, "dout_cmu_div_nocl1b_noc0_sm",
1823 "mout_cmu_nocl1b_noc0", CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM,
1824 0, 4),
1825 DIV(CLK_DOUT_CMU_DIV_NOCL1C_NOC, "dout_cmu_div_nocl1c_noc",
1826 "mout_cmu_mux_nocl1c_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC,
1827 0, 4),
1828 DIV(CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM, "dout_cmu_div_nocl1c_noc_sm",
1829 "mout_cmu_nocl1c_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM, 0, 4),
1830 DIV(CLK_DOUT_CMU_DIV_SDMA_NOC, "dout_cmu_div_sdma_noc",
1831 "mout_cmu_mux_sdma_noc", CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC, 0, 4),
1832 DIV(CLK_DOUT_CMU_DIV_SDMA_NOC_SM, "dout_cmu_div_sdma_noc_sm",
1833 "mout_cmu_sdma_noc", CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM, 0, 4),
1834 DIV(CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK, "dout_cmu_div_cp_hispeedy_clk",
1835 "mout_cmu_mux_cp_hispeedy_clk", CLK_CON_DIV_DIV_CP_HISPEEDY_CLK,
1836 0, 4),
1837 DIV(CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM,
1838 "dout_cmu_div_cp_hispeedy_clk_sm", "mout_cmu_mux_cp_hispeedy_clk",
1839 CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM, 0, 4),
1840 DIV(CLK_DOUT_CMU_DIV_CP_SHARED0_CLK, "dout_cmu_div_cp_shared0_clk",
1841 "mout_cmu_mux_cp_shared0_clk", CLK_CON_DIV_DIV_CP_SHARED0_CLK,
1842 0, 3),
1843 DIV(CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM,
1844 "dout_cmu_div_cp_shared0_clk_sm", "mout_cmu_cp_shared0_clk",
1845 CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM, 0, 3),
1846 DIV(CLK_DOUT_CMU_DIV_CP_SHARED2_CLK, "dout_cmu_div_cp_shared2_clk",
1847 "mout_cmu_mux_cp_shared2_clk", CLK_CON_DIV_DIV_CP_SHARED2_CLK,
1848 0, 3),
1849 DIV(CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM,
1850 "dout_cmu_div_cp_shared2_clk_sm", "mout_cmu_cp_shared2_clk",
1851 CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM, 0, 3),
1852 DIV(CLK_DOUT_CMU_UFS_NOC, "dout_cmu_ufs_noc", "mout_cmu_mux_ufs_noc",
1853 CLK_CON_DIV_CLKCMU_UFS_NOC, 0, 4),
1854 DIV(CLK_DOUT_CMU_DIV_M2M_FRC, "dout_cmu_div_m2m_frc",
1855 "mout_cmu_mux_m2m_frc", CLK_CON_DIV_DIV_CLKCMU_M2M_FRC, 0, 4),
1856 DIV(CLK_DOUT_CMU_DIV_M2M_FRC_SM, "dout_cmu_div_m2m_frc_sm",
1857 "mout_cmu_m2m_frc", CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM, 0, 4),
1858 DIV(CLK_DOUT_CMU_DIV_MCSC_MCSC, "dout_cmu_div_mcsc_mcsc",
1859 "mout_cmu_mux_mcsc_mcsc", CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC, 0, 4),
1860 DIV(CLK_DOUT_CMU_DIV_MCSC_MCSC_SM, "dout_cmu_div_mcsc_mcsc_sm",
1861 "mout_cmu_mcsc_mcsc", CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM, 0, 4),
1862 DIV(CLK_DOUT_CMU_DIV_MCSC_NOC, "dout_cmu_div_mcsc_noc",
1863 "mout_cmu_mux_mcsc_noc", CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC, 0, 4),
1864 DIV(CLK_DOUT_CMU_DIV_MCSC_NOC_SM, "dout_cmu_div_mcsc_noc_sm",
1865 "mout_cmu_mcsc_noc", CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM, 0, 4),
1866 };
1867
1868 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
1869 FFACTOR(CLK_DOUT_SHARED0_DIV1, "dout_shared0_div1",
1870 "fout_shared0_pll", 1, 1, 0),
1871 FFACTOR(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2",
1872 "fout_shared0_pll", 1, 2, 0),
1873 FFACTOR(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4",
1874 "fout_shared0_pll", 1, 4, 0),
1875 FFACTOR(CLK_DOUT_SHARED1_DIV1, "dout_shared1_div1",
1876 "fout_shared1_pll", 1, 1, 0),
1877 FFACTOR(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2",
1878 "fout_shared1_pll", 1, 2, 0),
1879 FFACTOR(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4",
1880 "fout_shared1_pll", 1, 4, 0),
1881 FFACTOR(CLK_DOUT_SHARED2_DIV1, "dout_shared2_div1",
1882 "fout_shared2_pll", 1, 1, 0),
1883 FFACTOR(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2",
1884 "fout_shared2_pll", 1, 2, 0),
1885 FFACTOR(CLK_DOUT_SHARED2_DIV4, "dout_shared2_div4",
1886 "fout_shared2_pll", 1, 4, 0),
1887 FFACTOR(CLK_DOUT_SHARED3_DIV1, "dout_shared3_div1",
1888 "fout_shared3_pll", 1, 1, 0),
1889 FFACTOR(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2",
1890 "fout_shared3_pll", 1, 2, 0),
1891 FFACTOR(CLK_DOUT_SHARED3_DIV4, "dout_shared3_div4",
1892 "fout_shared3_pll", 1, 4, 0),
1893 FFACTOR(CLK_DOUT_SHARED4_DIV1, "dout_shared4_div1",
1894 "fout_shared4_pll", 1, 1, 0),
1895 FFACTOR(CLK_DOUT_SHARED4_DIV2, "dout_shared4_div2",
1896 "fout_shared4_pll", 1, 2, 0),
1897 FFACTOR(CLK_DOUT_SHARED4_DIV4, "dout_shared4_div4",
1898 "fout_shared4_pll", 1, 4, 0),
1899 FFACTOR(CLK_DOUT_SHARED_MIF_DIV1, "dout_shared_mif_div1",
1900 "fout_shared_mif_pll", 1, 1, 0),
1901 FFACTOR(CLK_DOUT_SHARED_MIF_DIV2, "dout_shared_mif_div2",
1902 "fout_shared_mif_pll", 1, 2, 0),
1903 FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_shared_mif_div4",
1904 "fout_shared_mif_pll", 1, 4, 0),
1905 FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_mmc_div1",
1906 "fout_mmc_pll", 1, 1, 0),
1907 FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_mmc_div2",
1908 "fout_mmc_pll", 1, 2, 0),
1909 FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_mmc_div4",
1910 "fout_mmc_pll", 1, 4, 0),
1911 FFACTOR(CLK_DOUT_TCXO_DIV3, "dout_tcxo_div3",
1912 "oscclk", 1, 3, 0),
1913 FFACTOR(CLK_DOUT_TCXO_DIV4, "dout_tcxo_div4",
1914 "oscclk", 1, 4, 0),
1915 };
1916
1917 static const struct samsung_cmu_info top_cmu_info __initconst = {
1918 .pll_clks = top_pll_clks,
1919 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1920 .mux_clks = top_mux_clks,
1921 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1922 .div_clks = top_div_clks,
1923 .nr_div_clks = ARRAY_SIZE(top_div_clks),
1924 .fixed_factor_clks = top_fixed_factor_clks,
1925 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
1926 .nr_clk_ids = CLKS_NR_TOP,
1927 .clk_regs = top_clk_regs,
1928 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1929 };
1930
exynos2200_cmu_top_init(struct device_node * np)1931 static void __init exynos2200_cmu_top_init(struct device_node *np)
1932 {
1933 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1934 }
1935
1936 /* Register CMU_TOP early, as it's a dependency for other early domains */
1937 CLK_OF_DECLARE(exynos2200_cmu_top, "samsung,exynos2200-cmu-top",
1938 exynos2200_cmu_top_init);
1939
1940 /* ---- CMU_ALIVE ---------------------------------------------------------- */
1941
1942 /* Register Offset definitions for CMU_ALIVE (0x15800000) */
1943 #define PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER 0x600
1944 #define PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER 0x604
1945 #define PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER 0x610
1946 #define PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER 0x614
1947 #define PLL_CON0_MUX_CLK_RCO_ALIVE_USER 0x620
1948 #define PLL_CON1_MUX_CLK_RCO_ALIVE_USER 0x624
1949 #define CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI 0x1004
1950 #define CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC 0x1008
1951 #define CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI 0x100c
1952 #define CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC 0x1010
1953 #define CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC 0x1014
1954 #define CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC 0x1018
1955 #define CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC 0x101c
1956 #define CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC 0x1020
1957 #define CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC 0x1024
1958 #define CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC 0x1028
1959 #define CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART 0x1030
1960 #define CLK_CON_MUX_MUX_CLK_ALIVE_NOC 0x1034
1961 #define CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB 0x1038
1962 #define CLK_CON_MUX_MUX_CLK_ALIVE_SPMI 0x103c
1963 #define CLK_CON_MUX_MUX_CLK_ALIVE_TIMER 0x1040
1964 #define CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC 0x1044
1965 #define CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC 0x1048
1966 #define CLK_CON_DIV_CLKALIVE_CHUB_PERI 0x1804
1967 #define CLK_CON_DIV_CLKALIVE_CMGP_NOC 0x1808
1968 #define CLK_CON_DIV_CLKALIVE_CMGP_PERI 0x180c
1969 #define CLK_CON_DIV_CLKALIVE_DBGCORE_NOC 0x1810
1970 #define CLK_CON_DIV_CLKALIVE_DNC_NOC 0x1814
1971 #define CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC 0x1818
1972 #define CLK_CON_DIV_CLKALIVE_GNPU_NOC 0x181c
1973 #define CLK_CON_DIV_CLKALIVE_SDMA_NOC 0x1820
1974 #define CLK_CON_DIV_CLKALIVE_UFD_NOC 0x1824
1975 #define CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART 0x182c
1976 #define CLK_CON_DIV_DIV_CLK_ALIVE_NOC 0x1830
1977 #define CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB 0x1834
1978 #define CLK_CON_DIV_DIV_CLK_ALIVE_SPMI 0x1838
1979 #define CLK_CON_DIV_CLKALIVE_CSIS_NOC 0x183c
1980 #define CLK_CON_DIV_CLKALIVE_DSP_NOC 0x1840
1981 #define CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO 0x2000
1982 #define CLK_CON_GAT_CLKALIVE_DNC_RCO 0x2004
1983 #define CLK_CON_GAT_CLKALIVE_CSIS_RCO 0x2008
1984 #define CLK_CON_GAT_CLKALIVE_GNPU_RCO 0x200c
1985 #define CLK_CON_GAT_CLKALIVE_GNSS_NOC 0x2010
1986 #define CLK_CON_GAT_CLKALIVE_SDMA_RCO 0x2014
1987 #define CLK_CON_GAT_CLKALIVE_UFD_RCO 0x2018
1988 #define CLK_CON_GAT_CLKALIVE_DSP_RCO 0x201c
1989 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK 0x2020
1990 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2024
1991 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK 0x2028
1992 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK 0x202c
1993 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK 0x2030
1994 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x2034
1995 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK 0x2038
1996 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK 0x203c
1997 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK 0x2040
1998 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK 0x2044
1999 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK 0x2048
2000 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK 0x204c
2001 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x2050
2002 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK 0x2054
2003 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2058
2004 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK 0x205c
2005 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK 0x2060
2006 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK 0x2064
2007 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK 0x2068
2008 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x206c
2009 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK 0x2070
2010 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK 0x2074
2011 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK 0x2078
2012 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK 0x207c
2013 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK 0x2080
2014 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK 0x2084
2015 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK 0x2088
2016 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x208c
2017 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK 0x2090
2018 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK 0x2094
2019 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK 0x2098
2020 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK 0x209c
2021 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK 0x20a0
2022 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK 0x20a4
2023 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK 0x20a8
2024 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x20ac
2025 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK 0x20b0
2026 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB 0x20b4
2027 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK 0x20b8
2028 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK 0x20bc
2029 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK 0x20c0
2030 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK 0x20c4
2031 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK 0x20c8
2032 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK 0x20cc
2033 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK 0x20d0
2034 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK 0x20d4
2035 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK 0x20d8
2036 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK 0x20dc
2037 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK 0x20e0
2038 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK 0x20e4
2039 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK 0x20e8
2040 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK 0x20ec
2041 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK 0x20f0
2042 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK 0x20f4
2043 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK 0x20f8
2044 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK 0x20fc
2045 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK 0x2100
2046 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK 0x2104
2047 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK 0x2108
2048 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK 0x210c
2049 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK 0x2110
2050 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK 0x2114
2051 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK 0x2118
2052 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK 0x211c
2053 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK 0x2120
2054 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK 0x2124
2055 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK 0x2128
2056 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK 0x212c
2057 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK 0x2130
2058 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK 0x2134
2059 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK 0x2138
2060 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK 0x213c
2061 #define CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI 0x2140
2062 #define CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC 0x2144
2063 #define CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI 0x2148
2064 #define CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC 0x214c
2065 #define CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC 0x2150
2066 #define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK 0x2154
2067 #define CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC 0x2158
2068 #define CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC 0x215c
2069 #define CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC 0x2160
2070 #define CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC 0x2164
2071 #define CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC 0x2168
2072 #define CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC 0x216c
2073
2074 static const unsigned long alive_clk_regs[] __initconst = {
2075 PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER,
2076 PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER,
2077 PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER,
2078 PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER,
2079 PLL_CON0_MUX_CLK_RCO_ALIVE_USER,
2080 PLL_CON1_MUX_CLK_RCO_ALIVE_USER,
2081 CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI,
2082 CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC,
2083 CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI,
2084 CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC,
2085 CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC,
2086 CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC,
2087 CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC,
2088 CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC,
2089 CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC,
2090 CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC,
2091 CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART,
2092 CLK_CON_MUX_MUX_CLK_ALIVE_NOC,
2093 CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB,
2094 CLK_CON_MUX_MUX_CLK_ALIVE_SPMI,
2095 CLK_CON_MUX_MUX_CLK_ALIVE_TIMER,
2096 CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC,
2097 CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC,
2098 CLK_CON_DIV_CLKALIVE_CHUB_PERI,
2099 CLK_CON_DIV_CLKALIVE_CMGP_NOC,
2100 CLK_CON_DIV_CLKALIVE_CMGP_PERI,
2101 CLK_CON_DIV_CLKALIVE_DBGCORE_NOC,
2102 CLK_CON_DIV_CLKALIVE_DNC_NOC,
2103 CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC,
2104 CLK_CON_DIV_CLKALIVE_GNPU_NOC,
2105 CLK_CON_DIV_CLKALIVE_SDMA_NOC,
2106 CLK_CON_DIV_CLKALIVE_UFD_NOC,
2107 CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART,
2108 CLK_CON_DIV_DIV_CLK_ALIVE_NOC,
2109 CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB,
2110 CLK_CON_DIV_DIV_CLK_ALIVE_SPMI,
2111 CLK_CON_DIV_CLKALIVE_CSIS_NOC,
2112 CLK_CON_DIV_CLKALIVE_DSP_NOC,
2113 CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO,
2114 CLK_CON_GAT_CLKALIVE_DNC_RCO,
2115 CLK_CON_GAT_CLKALIVE_CSIS_RCO,
2116 CLK_CON_GAT_CLKALIVE_GNPU_RCO,
2117 CLK_CON_GAT_CLKALIVE_GNSS_NOC,
2118 CLK_CON_GAT_CLKALIVE_SDMA_RCO,
2119 CLK_CON_GAT_CLKALIVE_UFD_RCO,
2120 CLK_CON_GAT_CLKALIVE_DSP_RCO,
2121 CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK,
2122 CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
2123 CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK,
2124 CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK,
2125 CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK,
2126 CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
2127 CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK,
2128 CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK,
2129 CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK,
2130 CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK,
2131 CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK,
2132 CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK,
2133 CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
2134 CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK,
2135 CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
2136 CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK,
2137 CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK,
2138 CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK,
2139 CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK,
2140 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
2141 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK,
2142 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
2143 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK,
2144 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK,
2145 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK,
2146 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
2147 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
2148 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
2149 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK,
2150 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK,
2151 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK,
2152 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK,
2153 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK,
2154 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK,
2155 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK,
2156 CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
2157 CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK,
2158 CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB,
2159 CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK,
2160 CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK,
2161 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK,
2162 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK,
2163 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK,
2164 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK,
2165 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
2166 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK,
2167 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK,
2168 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK,
2169 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK,
2170 CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK,
2171 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK,
2172 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK,
2173 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK,
2174 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK,
2175 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK,
2176 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK,
2177 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK,
2178 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK,
2179 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK,
2180 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK,
2181 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK,
2182 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK,
2183 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK,
2184 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK,
2185 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK,
2186 CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK,
2187 CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK,
2188 CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK,
2189 CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK,
2190 CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK,
2191 CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK,
2192 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
2193 CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI,
2194 CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC,
2195 CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI,
2196 CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC,
2197 CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC,
2198 CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK,
2199 CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC,
2200 CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC,
2201 CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC,
2202 CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC,
2203 CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC,
2204 CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC,
2205 };
2206
2207 PNAME(mout_alive_noc_user_p) = { "oscclk", "dout_cmu_alive_noc" };
2208 PNAME(mout_alive_rco_spmi_user_p) = { "oscclk", "rco_i3c_pmic" };
2209 PNAME(mout_rco_alive_user_p) = { "oscclk", "rco_alive" };
2210 PNAME(mout_alive_chub_peri_p) = { "mout_rco_alive_user", "rco_400",
2211 "mout_alive_noc_user", "oscclk" };
2212 PNAME(mout_alive_cmgp_noc_p) = { "mout_rco_alive_user", "rco_400",
2213 "mout_alive_noc_user", "oscclk" };
2214 PNAME(mout_alive_cmgp_peri_p) = { "mout_rco_alive_user", "rco_400",
2215 "mout_alive_noc_user", "oscclk" };
2216 PNAME(mout_alive_dbgcore_noc_p) = { "mout_rco_alive_user", "rco_400",
2217 "mout_alive_noc_user", "oscclk" };
2218 PNAME(mout_alive_dnc_noc_p) = { "mout_rco_alive_user", "rco_400",
2219 "mout_alive_noc_user", "oscclk" };
2220 PNAME(mout_alive_chubvts_noc_p) = { "mout_rco_alive_user", "rco_400",
2221 "mout_alive_noc_user", "oscclk" };
2222 PNAME(mout_alive_gnpu_noc_p) = { "mout_rco_alive_user", "rco_400",
2223 "mout_alive_noc_user", "oscclk" };
2224 PNAME(mout_alive_gnss_noc_p) = { "rco_400", "mout_alive_noc_user" };
2225 PNAME(mout_alive_sdma_noc_p) = { "mout_rco_alive_user", "rco_400",
2226 "mout_alive_noc_user", "oscclk" };
2227 PNAME(mout_alive_ufd_noc_p) = { "mout_rco_alive_user",
2228 "rco_400",
2229 "mout_alive_noc_user",
2230 "oscclk" };
2231 PNAME(mout_alive_dbgcore_uart_p) = { "mout_rco_alive_user", "rco_400",
2232 "mout_alive_noc_user", "oscclk" };
2233 PNAME(mout_alive_noc_p) = { "mout_rco_alive_user", "rco_400",
2234 "mout_alive_noc_user", "oscclk" };
2235 PNAME(mout_alive_pmu_sub_p) = { "mout_rco_alive_user", "rco_400",
2236 "mout_alive_noc_user", "oscclk" };
2237 PNAME(mout_alive_spmi_p) = { "mout_rco_alive_user", "rco_400",
2238 "mout_alive_rco_spmi_user",
2239 "oscclk" };
2240 PNAME(mout_alive_timer_p) = { "oscclk", "oscclk" };
2241 PNAME(mout_alive_csis_noc_p) = { "mout_rco_alive_user", "rco_400",
2242 "mout_alive_noc_user", "oscclk" };
2243 PNAME(mout_alive_dsp_noc_p) = { "mout_rco_alive_user", "rco_400",
2244 "mout_alive_noc_user", "oscclk" };
2245
2246 static const struct samsung_mux_clock alive_mux_clks[] __initconst = {
2247 MUX(CLK_MOUT_ALIVE_NOC_USER, "mout_alive_noc_user",
2248 mout_alive_noc_user_p, PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER, 4, 1),
2249 MUX(CLK_MOUT_ALIVE_RCO_SPMI_USER, "mout_alive_rco_spmi_user",
2250 mout_alive_rco_spmi_user_p,
2251 PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER, 4, 1),
2252 MUX(CLK_MOUT_RCO_ALIVE_USER, "mout_rco_alive_user",
2253 mout_rco_alive_user_p, PLL_CON0_MUX_CLK_RCO_ALIVE_USER, 4, 1),
2254 MUX(CLK_MOUT_ALIVE_CHUB_PERI, "mout_alive_chub_peri",
2255 mout_alive_chub_peri_p, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI, 0, 2),
2256 MUX(CLK_MOUT_ALIVE_CMGP_NOC, "mout_alive_cmgp_noc",
2257 mout_alive_cmgp_noc_p, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC, 0, 2),
2258 MUX(CLK_MOUT_ALIVE_CMGP_PERI, "mout_alive_cmgp_peri",
2259 mout_alive_cmgp_peri_p, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI, 0, 2),
2260 MUX(CLK_MOUT_ALIVE_DBGCORE_NOC, "mout_alive_dbgcore_noc",
2261 mout_alive_dbgcore_noc_p, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC,
2262 0, 2),
2263 MUX(CLK_MOUT_ALIVE_DNC_NOC, "mout_alive_dnc_noc", mout_alive_dnc_noc_p,
2264 CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC, 0, 2),
2265 MUX(CLK_MOUT_ALIVE_CHUBVTS_NOC, "mout_alive_chubvts_noc",
2266 mout_alive_chubvts_noc_p, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC,
2267 0, 2),
2268 MUX(CLK_MOUT_ALIVE_GNPU_NOC, "mout_alive_gnpu_noc",
2269 mout_alive_gnpu_noc_p, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC, 0, 2),
2270 MUX(CLK_MOUT_ALIVE_GNSS_NOC, "mout_alive_gnss_noc",
2271 mout_alive_gnss_noc_p, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC, 0, 1),
2272 MUX(CLK_MOUT_ALIVE_SDMA_NOC, "mout_alive_sdma_noc",
2273 mout_alive_sdma_noc_p, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC, 0, 2),
2274 MUX(CLK_MOUT_ALIVE_UFD_NOC, "mout_alive_ufd_noc", mout_alive_ufd_noc_p,
2275 CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC, 0, 2),
2276 MUX(CLK_MOUT_ALIVE_DBGCORE_UART, "mout_alive_dbgcore_uart",
2277 mout_alive_dbgcore_uart_p, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART,
2278 0, 2),
2279 MUX(CLK_MOUT_ALIVE_NOC, "mout_alive_noc", mout_alive_noc_p,
2280 CLK_CON_MUX_MUX_CLK_ALIVE_NOC, 0, 2),
2281 MUX(CLK_MOUT_ALIVE_PMU_SUB, "mout_alive_pmu_sub", mout_alive_pmu_sub_p,
2282 CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB, 0, 2),
2283 MUX(CLK_MOUT_ALIVE_SPMI, "mout_alive_spmi", mout_alive_spmi_p,
2284 CLK_CON_MUX_MUX_CLK_ALIVE_SPMI, 0, 2),
2285 MUX(CLK_MOUT_ALIVE_TIMER, "mout_alive_timer", mout_alive_timer_p,
2286 CLK_CON_MUX_MUX_CLK_ALIVE_TIMER, 0, 1),
2287 MUX(CLK_MOUT_ALIVE_CSIS_NOC, "mout_alive_csis_noc",
2288 mout_alive_csis_noc_p, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC, 0, 2),
2289 MUX(CLK_MOUT_ALIVE_DSP_NOC, "mout_alive_dsp_noc", mout_alive_dsp_noc_p,
2290 CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC, 0, 2),
2291 };
2292
2293 static const struct samsung_div_clock alive_div_clks[] __initconst = {
2294 DIV(CLK_DOUT_ALIVE_CHUB_PERI, "dout_alive_chub_peri",
2295 "mout_alive_chub_peri", CLK_CON_DIV_CLKALIVE_CHUB_PERI, 0, 3),
2296 DIV(CLK_DOUT_ALIVE_CMGP_NOC, "dout_alive_cmgp_noc",
2297 "mout_alive_cmgp_noc", CLK_CON_DIV_CLKALIVE_CMGP_NOC, 0, 3),
2298 DIV(CLK_DOUT_ALIVE_CMGP_PERI, "dout_alive_cmgp_peri",
2299 "mout_alive_cmgp_peri", CLK_CON_DIV_CLKALIVE_CMGP_PERI, 0, 3),
2300 DIV(CLK_DOUT_ALIVE_DBGCORE_NOC, "dout_alive_dbgcore_noc",
2301 "mout_alive_dbgcore_noc", CLK_CON_DIV_CLKALIVE_DBGCORE_NOC, 0, 3),
2302 DIV(CLK_DOUT_ALIVE_DNC_NOC, "dout_alive_dnc_noc", "mout_alive_dnc_noc",
2303 CLK_CON_DIV_CLKALIVE_DNC_NOC, 0, 3),
2304 DIV(CLK_DOUT_ALIVE_CHUBVTS_NOC, "dout_alive_chubvts_noc",
2305 "mout_alive_chubvts_noc", CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC, 0, 3),
2306 DIV(CLK_DOUT_ALIVE_GNPU_NOC, "dout_alive_gnpu_noc",
2307 "mout_alive_gnpu_noc", CLK_CON_DIV_CLKALIVE_GNPU_NOC, 0, 3),
2308 DIV(CLK_DOUT_ALIVE_SDMA_NOC, "dout_alive_sdma_noc",
2309 "mout_alive_sdma_noc", CLK_CON_DIV_CLKALIVE_SDMA_NOC, 0, 3),
2310 DIV(CLK_DOUT_ALIVE_UFD_NOC, "dout_alive_ufd_noc", "mout_alive_ufd_noc",
2311 CLK_CON_DIV_CLKALIVE_UFD_NOC, 0, 3),
2312 DIV(CLK_DOUT_ALIVE_DBGCORE_UART, "dout_alive_dbgcore_uart",
2313 "mout_alive_dbgcore_uart", CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART,
2314 0, 4),
2315 DIV(CLK_DOUT_ALIVE_NOC, "dout_alive_noc", "mout_alive_noc",
2316 CLK_CON_DIV_DIV_CLK_ALIVE_NOC, 0, 3),
2317 DIV(CLK_DOUT_ALIVE_PMU_SUB, "dout_alive_pmu_sub", "mout_alive_pmu_sub",
2318 CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB, 0, 3),
2319 DIV(CLK_DOUT_ALIVE_SPMI, "dout_alive_spmi", "mout_alive_spmi",
2320 CLK_CON_DIV_DIV_CLK_ALIVE_SPMI, 0, 5),
2321 DIV(CLK_DOUT_ALIVE_CSIS_NOC, "dout_alive_csis_noc",
2322 "mout_alive_csis_noc", CLK_CON_DIV_CLKALIVE_CSIS_NOC, 0, 3),
2323 DIV(CLK_DOUT_ALIVE_DSP_NOC, "dout_alive_dsp_noc",
2324 "mout_alive_dsp_noc", CLK_CON_DIV_CLKALIVE_DSP_NOC, 0, 3),
2325 };
2326
2327 static const struct samsung_fixed_rate_clock alive_fixed_clks[] __initconst = {
2328 FRATE(0, "rco_i3c_pmic", NULL, 0, 49152000),
2329 FRATE(0, "rco_alive", NULL, 0, 49152000),
2330 FRATE(0, "rco_400", NULL, 0, 393216000),
2331 };
2332
2333 static const struct samsung_cmu_info alive_cmu_info __initconst = {
2334 .mux_clks = alive_mux_clks,
2335 .nr_mux_clks = ARRAY_SIZE(alive_mux_clks),
2336 .div_clks = alive_div_clks,
2337 .nr_div_clks = ARRAY_SIZE(alive_div_clks),
2338 .fixed_clks = alive_fixed_clks,
2339 .nr_fixed_clks = ARRAY_SIZE(alive_fixed_clks),
2340 .nr_clk_ids = CLKS_NR_ALIVE,
2341 .clk_regs = alive_clk_regs,
2342 .nr_clk_regs = ARRAY_SIZE(alive_clk_regs),
2343 .clk_name = "noc",
2344 };
2345
exynos2200_cmu_alive_init(struct device_node * np)2346 static void __init exynos2200_cmu_alive_init(struct device_node *np)
2347 {
2348 exynos_arm64_register_cmu(NULL, np, &alive_cmu_info);
2349 }
2350
2351 /* Register CMU_ALIVE early, as it's a dependency for other early domains */
2352 CLK_OF_DECLARE(exynos2200_cmu_alive, "samsung,exynos2200-cmu-alive",
2353 exynos2200_cmu_alive_init);
2354
2355 /* ---- CMU_PERIS ---------------------------------------------------------- */
2356
2357 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2358 #define PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER 0x600
2359 #define PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER 0x604
2360 #define PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER 0x610
2361 #define PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER 0x614
2362 #define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
2363 #define CLK_CON_DIV_CLKCMU_OTP 0x1800
2364 #define CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL 0x1804
2365 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK 0x2000
2366 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK 0x2004
2367 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN 0x2008
2368 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x200c
2369 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK 0x2010
2370 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK 0x2014
2371 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK 0x2018
2372 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x201c
2373 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2020
2374 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2024
2375 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2028
2376 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x202c
2377 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x2030
2378 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK 0x2038
2379 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x203c
2380 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK 0x2040
2381 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK 0x2044
2382 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK 0x2048
2383 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x204c
2384 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2050
2385 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2054
2386 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK 0x2058
2387 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK 0x205c
2388 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK 0x2060
2389 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK 0x2064
2390 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2068
2391 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK 0x206c
2392
2393 static const unsigned long peris_clk_regs[] __initconst = {
2394 PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER,
2395 PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER,
2396 PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER,
2397 PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER,
2398 CLK_CON_MUX_MUX_CLK_PERIS_GIC,
2399 CLK_CON_DIV_CLKCMU_OTP,
2400 CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL,
2401 CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK,
2402 CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK,
2403 CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN,
2404 CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
2405 CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK,
2406 CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
2407 CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
2408 CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
2409 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
2410 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
2411 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
2412 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
2413 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
2414 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK,
2415 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
2416 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK,
2417 CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK,
2418 CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK,
2419 CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2420 CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
2421 CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
2422 CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
2423 CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
2424 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK,
2425 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK,
2426 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK,
2427 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK,
2428 };
2429
2430 PNAME(mout_peris_gic_user_p) = { "dout_tcxo_div3",
2431 "dout_cmu_peris_gic" };
2432 PNAME(mout_peris_noc_user_p) = { "dout_tcxo_div3",
2433 "dout_cmu_peris_noc" };
2434 PNAME(mout_peris_gic_p) = { "mout_peris_gic_user", "dout_tcxo_div3" };
2435
2436 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
2437 MUX(CLK_MOUT_PERIS_GIC_USER, "mout_peris_gic_user",
2438 mout_peris_gic_user_p, PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER, 4, 1),
2439 MUX(CLK_MOUT_PERIS_NOC_USER, "mout_peris_noc_user",
2440 mout_peris_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, 4, 1),
2441 MUX(CLK_MOUT_PERIS_GIC, "mout_peris_gic", mout_peris_gic_p,
2442 CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0, 0),
2443 };
2444
2445 static const struct samsung_fixed_factor_clock peris_fixed_factor_clks[] __initconst = {
2446 FFACTOR(CLK_DOUT_PERIS_OTP, "dout_peris_otp",
2447 "dout_tcxo_div3", 1, 8, 0),
2448 FFACTOR(CLK_DOUT_PERIS_DDD_CTRL, "dout_peris_ddd_ctrl",
2449 "mout_peris_gic", 1, 4, 0),
2450 };
2451
2452 static const struct samsung_cmu_info peris_cmu_info __initconst = {
2453 .mux_clks = peris_mux_clks,
2454 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
2455 .fixed_factor_clks = peris_fixed_factor_clks,
2456 .nr_fixed_factor_clks = ARRAY_SIZE(peris_fixed_factor_clks),
2457 .nr_clk_ids = CLKS_NR_PERIS,
2458 .clk_regs = peris_clk_regs,
2459 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
2460 .clk_name = "noc",
2461 };
2462
exynos2200_cmu_peris_init(struct device_node * np)2463 static void __init exynos2200_cmu_peris_init(struct device_node *np)
2464 {
2465 exynos_arm64_register_cmu(NULL, np, &peris_cmu_info);
2466 }
2467
2468 /* Register CMU_PERIS early, as it's a dependency for GIC and MCT */
2469 CLK_OF_DECLARE(exynos2200_cmu_peris, "samsung,exynos2200-cmu-peris",
2470 exynos2200_cmu_peris_init);
2471
2472 /* ---- CMU_CMGP ----------------------------------------------------------- */
2473
2474 /* Register Offset definitions for CMU_CMGP (0x14e00000) */
2475 #define PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER 0x610
2476 #define PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER 0x614
2477 #define PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER 0x620
2478 #define PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER 0x624
2479 #define CLK_CON_MUX_MUX_CLK_CMGP_I2C 0x1000
2480 #define CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0 0x1008
2481 #define CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1 0x100c
2482 #define CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL 0x1010
2483 #define CLK_CON_MUX_MUX_CLK_CMGP_USI0 0x1014
2484 #define CLK_CON_MUX_MUX_CLK_CMGP_USI1 0x1018
2485 #define CLK_CON_MUX_MUX_CLK_CMGP_USI2 0x101c
2486 #define CLK_CON_MUX_MUX_CLK_CMGP_USI3 0x1020
2487 #define CLK_CON_MUX_MUX_CLK_CMGP_USI4 0x1024
2488 #define CLK_CON_MUX_MUX_CLK_CMGP_USI5 0x1028
2489 #define CLK_CON_MUX_MUX_CLK_CMGP_USI6 0x102c
2490 #define CLK_CON_DIV_DIV_CLK_CMGP_I2C 0x1800
2491 #define CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0 0x1808
2492 #define CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1 0x180c
2493 #define CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL 0x1810
2494 #define CLK_CON_DIV_DIV_CLK_CMGP_USI0 0x1814
2495 #define CLK_CON_DIV_DIV_CLK_CMGP_USI1 0x1818
2496 #define CLK_CON_DIV_DIV_CLK_CMGP_USI2 0x181c
2497 #define CLK_CON_DIV_DIV_CLK_CMGP_USI3 0x1820
2498 #define CLK_CON_DIV_DIV_CLK_CMGP_USI4 0x1824
2499 #define CLK_CON_DIV_DIV_CLK_CMGP_USI5 0x1828
2500 #define CLK_CON_DIV_DIV_CLK_CMGP_USI6 0x182c
2501 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK 0x2000
2502 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK 0x2004
2503 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK 0x2008
2504 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK 0x200c
2505 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK 0x2010
2506 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK 0x2014
2507 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK 0x2018
2508 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK 0x201c
2509 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK 0x2020
2510 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK 0x2024
2511 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK 0x2028
2512 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK 0x202c
2513 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK 0x2030
2514 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK 0x2034
2515 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK 0x2038
2516 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK 0x2040
2517 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK 0x2044
2518 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK 0x2048
2519 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK 0x2050
2520 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK 0x2054
2521 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK 0x2058
2522 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK 0x205c
2523 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK 0x2060
2524 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK 0x2064
2525 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK 0x2068
2526 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK 0x206c
2527 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK 0x2070
2528 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK 0x2074
2529 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK 0x2078
2530 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK 0x207c
2531 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK 0x2080
2532 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK 0x2084
2533 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK 0x2088
2534 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK 0x208c
2535 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK 0x2090
2536 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK 0x2094
2537 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK 0x2098
2538 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK 0x209c
2539 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK 0x20a0
2540 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK 0x20a4
2541 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK 0x20a8
2542 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK 0x20ac
2543 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK 0x20b0
2544 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK 0x20b4
2545 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK 0x20b8
2546 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK 0x20bc
2547 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK 0x20c0
2548 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK 0x20c4
2549 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK 0x20c8
2550 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK 0x20cc
2551 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK 0x20d0
2552 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK 0x20d4
2553 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK 0x20d8
2554 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK 0x20dc
2555 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK 0x20e0
2556 #define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK 0x20e4
2557
2558 static const unsigned long cmgp_clk_regs[] __initconst = {
2559 PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER,
2560 PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER,
2561 PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER,
2562 PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER,
2563 CLK_CON_MUX_MUX_CLK_CMGP_I2C,
2564 CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0,
2565 CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1,
2566 CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL,
2567 CLK_CON_MUX_MUX_CLK_CMGP_USI0,
2568 CLK_CON_MUX_MUX_CLK_CMGP_USI1,
2569 CLK_CON_MUX_MUX_CLK_CMGP_USI2,
2570 CLK_CON_MUX_MUX_CLK_CMGP_USI3,
2571 CLK_CON_MUX_MUX_CLK_CMGP_USI4,
2572 CLK_CON_MUX_MUX_CLK_CMGP_USI5,
2573 CLK_CON_MUX_MUX_CLK_CMGP_USI6,
2574 CLK_CON_DIV_DIV_CLK_CMGP_I2C,
2575 CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0,
2576 CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1,
2577 CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL,
2578 CLK_CON_DIV_DIV_CLK_CMGP_USI0,
2579 CLK_CON_DIV_DIV_CLK_CMGP_USI1,
2580 CLK_CON_DIV_DIV_CLK_CMGP_USI2,
2581 CLK_CON_DIV_DIV_CLK_CMGP_USI3,
2582 CLK_CON_DIV_DIV_CLK_CMGP_USI4,
2583 CLK_CON_DIV_DIV_CLK_CMGP_USI5,
2584 CLK_CON_DIV_DIV_CLK_CMGP_USI6,
2585 CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK,
2586 CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
2587 CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK,
2588 CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK,
2589 CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK,
2590 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
2591 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
2592 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
2593 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
2594 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK,
2595 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK,
2596 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK,
2597 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK,
2598 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK,
2599 CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK,
2600 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK,
2601 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK,
2602 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK,
2603 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK,
2604 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK,
2605 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK,
2606 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK,
2607 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK,
2608 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK,
2609 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK,
2610 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK,
2611 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK,
2612 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK,
2613 CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK,
2614 CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK,
2615 CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK,
2616 CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK,
2617 CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK,
2618 CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK,
2619 CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK,
2620 CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK,
2621 CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
2622 CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK,
2623 CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
2624 CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
2625 CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
2626 CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
2627 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
2628 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
2629 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
2630 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
2631 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
2632 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
2633 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
2634 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
2635 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK,
2636 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK,
2637 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK,
2638 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK,
2639 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK,
2640 CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK,
2641 };
2642
2643 PNAME(mout_cmgp_clkalive_noc_user_p) = { "oscclk", "dout_alive_cmgp_noc" };
2644 PNAME(mout_cmgp_clkalive_peri_user_p) = { "oscclk", "dout_alive_cmgp_peri" };
2645 PNAME(mout_cmgp_i2c_p) = { "oscclk",
2646 "mout_cmgp_clkalive_peri_user" };
2647 PNAME(mout_cmgp_spi_i2c0_p) = { "oscclk",
2648 "mout_cmgp_clkalive_peri_user" };
2649 PNAME(mout_cmgp_spi_i2c1_p) = { "oscclk",
2650 "mout_cmgp_clkalive_peri_user" };
2651 PNAME(mout_cmgp_spi_ms_ctrl_p) = { "oscclk",
2652 "mout_cmgp_clkalive_peri_user" };
2653 PNAME(mout_cmgp_usi0_p) = { "oscclk",
2654 "mout_cmgp_clkalive_peri_user" };
2655 PNAME(mout_cmgp_usi1_p) = { "oscclk",
2656 "mout_cmgp_clkalive_peri_user" };
2657 PNAME(mout_cmgp_usi2_p) = { "oscclk",
2658 "mout_cmgp_clkalive_peri_user" };
2659 PNAME(mout_cmgp_usi3_p) = { "oscclk",
2660 "mout_cmgp_clkalive_peri_user" };
2661 PNAME(mout_cmgp_usi4_p) = { "oscclk",
2662 "mout_cmgp_clkalive_peri_user" };
2663 PNAME(mout_cmgp_usi5_p) = { "oscclk",
2664 "mout_cmgp_clkalive_peri_user" };
2665 PNAME(mout_cmgp_usi6_p) = { "oscclk",
2666 "mout_cmgp_clkalive_peri_user" };
2667
2668 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
2669 MUX(CLK_MOUT_CMGP_CLKALIVE_NOC_USER, "mout_cmgp_clkalive_noc_user",
2670 mout_cmgp_clkalive_noc_user_p, PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER,
2671 4, 1),
2672 MUX(CLK_MOUT_CMGP_CLKALIVE_PERI_USER, "mout_cmgp_clkalive_peri_user",
2673 mout_cmgp_clkalive_peri_user_p,
2674 PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER, 4, 1),
2675 MUX(CLK_MOUT_CMGP_I2C, "mout_cmgp_i2c", mout_cmgp_i2c_p,
2676 CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0, 1),
2677 MUX(CLK_MOUT_CMGP_SPI_I2C0, "mout_cmgp_spi_i2c0", mout_cmgp_spi_i2c0_p,
2678 CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0, 0, 1),
2679 MUX(CLK_MOUT_CMGP_SPI_I2C1, "mout_cmgp_spi_i2c1", mout_cmgp_spi_i2c1_p,
2680 CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1, 0, 1),
2681 MUX(CLK_MOUT_CMGP_SPI_MS_CTRL, "mout_cmgp_spi_ms_ctrl",
2682 mout_cmgp_spi_ms_ctrl_p, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL,
2683 0, 1),
2684 MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
2685 CLK_CON_MUX_MUX_CLK_CMGP_USI0, 0, 1),
2686 MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
2687 CLK_CON_MUX_MUX_CLK_CMGP_USI1, 0, 1),
2688 MUX(CLK_MOUT_CMGP_USI2, "mout_cmgp_usi2", mout_cmgp_usi2_p,
2689 CLK_CON_MUX_MUX_CLK_CMGP_USI2, 0, 1),
2690 MUX(CLK_MOUT_CMGP_USI3, "mout_cmgp_usi3", mout_cmgp_usi3_p,
2691 CLK_CON_MUX_MUX_CLK_CMGP_USI3, 0, 1),
2692 MUX(CLK_MOUT_CMGP_USI4, "mout_cmgp_usi4", mout_cmgp_usi4_p,
2693 CLK_CON_MUX_MUX_CLK_CMGP_USI4, 0, 1),
2694 MUX(CLK_MOUT_CMGP_USI5, "mout_cmgp_usi5", mout_cmgp_usi5_p,
2695 CLK_CON_MUX_MUX_CLK_CMGP_USI5, 0, 1),
2696 MUX(CLK_MOUT_CMGP_USI6, "mout_cmgp_usi6", mout_cmgp_usi6_p,
2697 CLK_CON_MUX_MUX_CLK_CMGP_USI6, 0, 1),
2698 };
2699
2700 static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
2701 DIV(CLK_DOUT_CMGP_I2C, "dout_cmgp_i2c", "mout_cmgp_i2c",
2702 CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0, 4),
2703 DIV(CLK_DOUT_CMGP_SPI_I2C0, "dout_cmgp_spi_i2c0", "mout_cmgp_spi_i2c0",
2704 CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0, 0, 4),
2705 DIV(CLK_DOUT_CMGP_SPI_I2C1, "dout_cmgp_spi_i2c1", "mout_cmgp_spi_i2c1",
2706 CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1, 0, 4),
2707 DIV(CLK_DOUT_CMGP_SPI_MS_CTRL, "dout_cmgp_spi_ms_ctrl",
2708 "mout_cmgp_spi_ms_ctrl", CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL,
2709 0, 4),
2710 DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
2711 CLK_CON_DIV_DIV_CLK_CMGP_USI0, 0, 4),
2712 DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
2713 CLK_CON_DIV_DIV_CLK_CMGP_USI1, 0, 4),
2714 DIV(CLK_DOUT_CMGP_USI2, "dout_cmgp_usi2", "mout_cmgp_usi2",
2715 CLK_CON_DIV_DIV_CLK_CMGP_USI2, 0, 4),
2716 DIV(CLK_DOUT_CMGP_USI3, "dout_cmgp_usi3", "mout_cmgp_usi3",
2717 CLK_CON_DIV_DIV_CLK_CMGP_USI3, 0, 4),
2718 DIV(CLK_DOUT_CMGP_USI4, "dout_cmgp_usi4", "mout_cmgp_usi4",
2719 CLK_CON_DIV_DIV_CLK_CMGP_USI4, 0, 4),
2720 DIV(CLK_DOUT_CMGP_USI5, "dout_cmgp_usi5", "mout_cmgp_usi5",
2721 CLK_CON_DIV_DIV_CLK_CMGP_USI5, 0, 4),
2722 DIV(CLK_DOUT_CMGP_USI6, "dout_cmgp_usi6", "mout_cmgp_usi6",
2723 CLK_CON_DIV_DIV_CLK_CMGP_USI6, 0, 4),
2724 };
2725
2726 static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
2727 .mux_clks = cmgp_mux_clks,
2728 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
2729 .div_clks = cmgp_div_clks,
2730 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
2731 .nr_clk_ids = CLKS_NR_CMGP,
2732 .clk_regs = cmgp_clk_regs,
2733 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
2734 .clk_name = "noc",
2735 };
2736
2737 /* ---- CMU_HSI0 ----------------------------------------------------------- */
2738
2739 /* Register Offset definitions for CMU_HSI0 (0x10a00000) */
2740 #define PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER 0x600
2741 #define PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER 0x604
2742 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x610
2743 #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x614
2744 #define PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER 0x620
2745 #define PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER 0x624
2746 #define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x630
2747 #define PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER 0x634
2748 #define PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER 0x640
2749 #define PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER 0x644
2750 #define CLK_CON_MUX_MUX_CLK_HSI0_NOC 0x1000
2751 #define CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK 0x1004
2752 #define CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD 0x1008
2753 #define CLK_CON_DIV_DIV_CLK_HSI0_EUSB 0x1800
2754 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM 0x2000
2755 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x2004
2756 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK 0x2008
2757 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x200c
2758 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2010
2759 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2014
2760 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK 0x2018
2761 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK 0x201c
2762 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK 0x2020
2763 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK 0x2024
2764 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK 0x2028
2765 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK 0x202c
2766 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK 0x2030
2767 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK 0x2034
2768 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK 0x2038
2769 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x203c
2770 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2 0x2040
2771 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2044
2772 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK 0x2048
2773 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK 0x204c
2774 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK 0x2050
2775 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40 0x2054
2776 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK 0x2058
2777 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK 0x205c
2778 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK 0x2060
2779 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK 0x2064
2780 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK 0x2068
2781 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK 0x206c
2782 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK 0x2070
2783 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK 0x2074
2784 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK 0x2078
2785 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK 0x207c
2786 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK 0x2080
2787
2788 static const unsigned long hsi0_clk_regs[] __initconst = {
2789 PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER,
2790 PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER,
2791 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
2792 PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
2793 PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER,
2794 PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER,
2795 PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
2796 PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER,
2797 PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER,
2798 PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER,
2799 CLK_CON_MUX_MUX_CLK_HSI0_NOC,
2800 CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK,
2801 CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD,
2802 CLK_CON_DIV_DIV_CLK_HSI0_EUSB,
2803 CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM,
2804 CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2805 CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK,
2806 CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
2807 CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2808 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2809 CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
2810 CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
2811 CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK,
2812 CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK,
2813 CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK,
2814 CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK,
2815 CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK,
2816 CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK,
2817 CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK,
2818 CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
2819 CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2,
2820 CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2821 CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK,
2822 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK,
2823 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK,
2824 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40,
2825 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK,
2826 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK,
2827 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK,
2828 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK,
2829 CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
2830 CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
2831 CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK,
2832 CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK,
2833 CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK,
2834 CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK,
2835 CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK,
2836 };
2837
2838 PNAME(mout_clkcmu_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
2839 PNAME(mout_clkcmu_hsi0_dposc_user_p) = { "oscclk", "dout_cmu_hsi0_dposc" };
2840 PNAME(mout_clkcmu_hsi0_noc_user_p) = { "oscclk", "dout_cmu_hsi0_noc" };
2841 PNAME(mout_clkcmu_hsi0_usb32drd_user_p) = { "oscclk",
2842 "dout_cmu_hsi0_usb32drd" };
2843 PNAME(mout_mux_clk_hsi0_noc_p) = { "mout_clkcmu_hsi0_noc_user" };
2844 PNAME(mout_mux_clk_hsi0_rtcclk_p) = { "rtcclk", "oscclk" };
2845 PNAME(mout_mux_clk_hsi0_usb32drd_p) = { "dout_tcxo_div4",
2846 "mout_clkcmu_hsi0_usb32drd_user" };
2847
2848 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
2849 MUX(CLK_MOUT_CLKCMU_HSI0_DPGTC_USER, "mout_clkcmu_hsi0_dpgtc_user",
2850 mout_clkcmu_hsi0_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
2851 4, 1),
2852 MUX(CLK_MOUT_CLKCMU_HSI0_DPOSC_USER, "mout_clkcmu_hsi0_dposc_user",
2853 mout_clkcmu_hsi0_dposc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER,
2854 4, 1),
2855 MUX(CLK_MOUT_CLKCMU_HSI0_NOC_USER, "mout_clkcmu_hsi0_noc_user",
2856 mout_clkcmu_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
2857 4, 1),
2858 MUX(CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER,
2859 "mout_clkcmu_hsi0_usb32drd_user", mout_clkcmu_hsi0_usb32drd_user_p,
2860 PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER, 4, 1),
2861 MUX(CLK_MOUT_HSI0_NOC, "mout_hsi0_noc", mout_mux_clk_hsi0_noc_p,
2862 CLK_CON_MUX_MUX_CLK_HSI0_NOC, 0, 1),
2863 MUX(CLK_MOUT_HSI0_RTCCLK, "mout_hsi0_rtcclk",
2864 mout_mux_clk_hsi0_rtcclk_p, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK, 0, 1),
2865 MUX(CLK_MOUT_HSI0_USB32DRD, "mout_hsi0_usb32drd",
2866 mout_mux_clk_hsi0_usb32drd_p, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD,
2867 0, 1),
2868 };
2869
2870 static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
2871 DIV(CLK_DOUT_DIV_CLK_HSI0_EUSB, "dout_div_clk_hsi0_eusb",
2872 "mout_hsi0_noc", CLK_CON_DIV_DIV_CLK_HSI0_EUSB, 0, 2),
2873 };
2874
2875 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
2876 .mux_clks = hsi0_mux_clks,
2877 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
2878 .div_clks = hsi0_div_clks,
2879 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
2880 .nr_clk_ids = CLKS_NR_HSI0,
2881 .clk_regs = hsi0_clk_regs,
2882 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
2883 .clk_name = "noc",
2884 };
2885
2886 /* ---- CMU_PERIC0 --------------------------------------------------------- */
2887
2888 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */
2889 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER 0x600
2890 #define PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER 0x604
2891 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER 0x610
2892 #define PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER 0x614
2893 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x620
2894 #define PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER 0x624
2895 #define CLK_CON_MUX_MUX_CLK_PERIC0_I2C 0x1000
2896 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04 0x1010
2897 #define CLK_CON_DIV_DIV_CLK_PERIC0_I2C 0x1800
2898 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04 0x1810
2899 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x2000
2900 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2004
2901 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2008
2902 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK 0x200c
2903 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK 0x2010
2904 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK 0x2014
2905 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK 0x2018
2906 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK 0x201c
2907 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x2020
2908 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK 0x2024
2909 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK 0x2028
2910 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK 0x202c
2911 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK 0x2030
2912 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK 0x2034
2913 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK 0x2038
2914 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK 0x203c
2915 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK 0x2040
2916 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK 0x2044
2917 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK 0x2048
2918 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK 0x204c
2919 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK 0x2050
2920
2921 static const unsigned long peric0_clk_regs[] __initconst = {
2922 PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER,
2923 PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER,
2924 PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER,
2925 PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER,
2926 PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER,
2927 PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER,
2928 CLK_CON_MUX_MUX_CLK_PERIC0_I2C,
2929 CLK_CON_MUX_MUX_CLK_PERIC0_USI04,
2930 CLK_CON_DIV_DIV_CLK_PERIC0_I2C,
2931 CLK_CON_DIV_DIV_CLK_PERIC0_USI04,
2932 CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
2933 CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
2934 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
2935 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK,
2936 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK,
2937 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK,
2938 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK,
2939 CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK,
2940 CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
2941 CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK,
2942 CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK,
2943 CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK,
2944 CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK,
2945 CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK,
2946 CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK,
2947 CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK,
2948 CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK,
2949 CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK,
2950 CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK,
2951 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK,
2952 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK,
2953 };
2954
2955 PNAME(mout_peric0_ip0_user_p) = { "oscclk", "dout_cmu_peric0_ip0" };
2956 PNAME(mout_peric0_ip1_user_p) = { "oscclk", "dout_cmu_peric0_ip1" };
2957 PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_cmu_peric0_noc" };
2958 PNAME(mout_peric0_i2c_p) = { "oscclk", "mout_peric0_ip0_user",
2959 "mout_peric0_ip0_user", "oscclk" };
2960 PNAME(mout_peric0_usi04_p) = { "oscclk", "mout_peric0_ip0_user",
2961 "mout_peric0_ip0_user", "oscclk" };
2962
2963 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
2964 MUX(CLK_MOUT_PERIC0_IP0_USER, "mout_peric0_ip0_user",
2965 mout_peric0_ip0_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER, 4, 1),
2966 MUX(CLK_MOUT_PERIC0_IP1_USER, "mout_peric0_ip1_user",
2967 mout_peric0_ip1_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER, 4, 1),
2968 MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user",
2969 mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1),
2970 MUX(CLK_MOUT_PERIC0_I2C, "mout_peric0_i2c", mout_peric0_i2c_p,
2971 CLK_CON_MUX_MUX_CLK_PERIC0_I2C, 0, 2),
2972 MUX(CLK_MOUT_PERIC0_USI04, "mout_peric0_usi04", mout_peric0_usi04_p,
2973 CLK_CON_MUX_MUX_CLK_PERIC0_USI04, 0, 2),
2974 };
2975
2976 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
2977 DIV(CLK_DOUT_PERIC0_I2C, "dout_peric0_i2c", "mout_peric0_i2c",
2978 CLK_CON_DIV_DIV_CLK_PERIC0_I2C, 0, 4),
2979 DIV(CLK_DOUT_PERIC0_USI04, "dout_peric0_usi04", "mout_peric0_usi04",
2980 CLK_CON_DIV_DIV_CLK_PERIC0_USI04, 0, 7),
2981 };
2982
2983 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
2984 .mux_clks = peric0_mux_clks,
2985 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
2986 .div_clks = peric0_div_clks,
2987 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
2988 .nr_clk_ids = CLKS_NR_PERIC0,
2989 .clk_regs = peric0_clk_regs,
2990 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
2991 .clk_name = "noc",
2992 };
2993
2994 /* ---- CMU_PERIC1 --------------------------------------------------------- */
2995
2996 /* Register Offset definitions for CMU_PERIC1 (0x10700000) */
2997 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER 0x600
2998 #define PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER 0x604
2999 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER 0x610
3000 #define PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER 0x614
3001 #define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x620
3002 #define PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER 0x624
3003 #define CLK_CON_MUX_MUX_CLK_PERIC1_I2C 0x1000
3004 #define CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL 0x1004
3005 #define CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT 0x1008
3006 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07 0x100c
3007 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C 0x1010
3008 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08 0x1014
3009 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C 0x1018
3010 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09 0x101c
3011 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10 0x1020
3012 #define CLK_CON_DIV_DIV_CLK_PERIC1_I2C 0x1800
3013 #define CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL 0x1804
3014 #define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1808
3015 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07 0x180c
3016 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C 0x1810
3017 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08 0x1814
3018 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C 0x1818
3019 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09 0x181c
3020 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10 0x1820
3021 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK 0x2000
3022 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK 0x2004
3023 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2008
3024 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x200c
3025 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK 0x2010
3026 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK 0x2014
3027 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2028
3028 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK 0x202c
3029 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK 0x2034
3030 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK 0x2038
3031 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK 0x203c
3032 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK 0x2040
3033 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK 0x2044
3034 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK 0x2048
3035 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK 0x204c
3036 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK 0x2050
3037 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK 0x2054
3038 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK 0x205c
3039 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK 0x2060
3040 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2064
3041 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK 0x2068
3042 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK 0x206c
3043 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK 0x2070
3044 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK 0x2074
3045 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK 0x2078
3046 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK 0x207c
3047 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK 0x2080
3048 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK 0x2084
3049 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK 0x2088
3050 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK 0x208c
3051 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK 0x2090
3052 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK 0x2094
3053 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK 0x2098
3054 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK 0x209c
3055 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK 0x20a0
3056 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK 0x20a4
3057 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x20a8
3058
3059 static const unsigned long peric1_clk_regs[] __initconst = {
3060 PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER,
3061 PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER,
3062 PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER,
3063 PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER,
3064 PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
3065 PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER,
3066 CLK_CON_MUX_MUX_CLK_PERIC1_I2C,
3067 CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL,
3068 CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT,
3069 CLK_CON_MUX_MUX_CLK_PERIC1_USI07,
3070 CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C,
3071 CLK_CON_MUX_MUX_CLK_PERIC1_USI08,
3072 CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C,
3073 CLK_CON_MUX_MUX_CLK_PERIC1_USI09,
3074 CLK_CON_MUX_MUX_CLK_PERIC1_USI10,
3075 CLK_CON_DIV_DIV_CLK_PERIC1_I2C,
3076 CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL,
3077 CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
3078 CLK_CON_DIV_DIV_CLK_PERIC1_USI07,
3079 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C,
3080 CLK_CON_DIV_DIV_CLK_PERIC1_USI08,
3081 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C,
3082 CLK_CON_DIV_DIV_CLK_PERIC1_USI09,
3083 CLK_CON_DIV_DIV_CLK_PERIC1_USI10,
3084 CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK,
3085 CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK,
3086 CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
3087 CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
3088 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK,
3089 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK,
3090 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
3091 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK,
3092 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK,
3093 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
3094 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK,
3095 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK,
3096 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK,
3097 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK,
3098 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK,
3099 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK,
3100 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK,
3101 CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK,
3102 CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK,
3103 CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
3104 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK,
3105 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK,
3106 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK,
3107 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK,
3108 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK,
3109 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK,
3110 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK,
3111 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK,
3112 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK,
3113 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK,
3114 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK,
3115 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK,
3116 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK,
3117 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK,
3118 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK,
3119 CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK,
3120 CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
3121 };
3122
3123 PNAME(mout_peric1_ip0_user_p) = { "oscclk", "dout_cmu_peric1_ip0" };
3124 PNAME(mout_peric1_ip1_user_p) = { "oscclk", "dout_cmu_peric1_ip1" };
3125 PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_cmu_peric1_noc" };
3126 PNAME(mout_peric1_i2c_p) = { "oscclk", "mout_peric1_ip0_user",
3127 "mout_peric1_ip1_user", "oscclk" };
3128 PNAME(mout_peric1_spi_ms_ctrl_p) = { "oscclk", "mout_peric1_ip0_user",
3129 "mout_peric1_ip1_user", "oscclk" };
3130 PNAME(mout_peric1_uart_bt_p) = { "oscclk", "mout_peric1_ip0_user",
3131 "mout_peric1_ip1_user", "oscclk" };
3132 PNAME(mout_peric1_usi07_p) = { "oscclk", "mout_peric1_ip0_user",
3133 "mout_peric1_ip1_user", "oscclk" };
3134 PNAME(mout_peric1_usi07_spi_i2c_p) = { "oscclk", "mout_peric1_ip0_user",
3135 "mout_peric1_ip1_user", "oscclk" };
3136 PNAME(mout_peric1_usi08_p) = { "oscclk", "mout_peric1_ip0_user",
3137 "mout_peric1_ip1_user", "oscclk" };
3138 PNAME(mout_peric1_usi08_spi_i2c_p) = { "oscclk", "mout_peric1_ip0_user",
3139 "mout_peric1_ip1_user", "oscclk" };
3140 PNAME(mout_peric1_usi09_p) = { "oscclk", "mout_peric1_ip0_user",
3141 "mout_peric1_ip1_user", "oscclk" };
3142 PNAME(mout_peric1_usi10_p) = { "oscclk", "mout_peric1_ip0_user",
3143 "mout_peric1_ip1_user", "oscclk" };
3144
3145 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
3146 MUX(CLK_MOUT_PERIC1_IP0_USER, "mout_peric1_ip0_user",
3147 mout_peric1_ip0_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER, 4, 1),
3148 MUX(CLK_MOUT_PERIC1_IP1_USER, "mout_peric1_ip1_user",
3149 mout_peric1_ip1_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER, 4, 1),
3150 MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
3151 mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
3152 MUX(CLK_MOUT_PERIC1_I2C, "mout_peric1_i2c", mout_peric1_i2c_p,
3153 CLK_CON_MUX_MUX_CLK_PERIC1_I2C, 0, 2),
3154 MUX(CLK_MOUT_PERIC1_SPI_MS_CTRL, "mout_peric1_spi_ms_ctrl",
3155 mout_peric1_spi_ms_ctrl_p, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL,
3156 0, 2),
3157 MUX(CLK_MOUT_PERIC1_UART_BT, "mout_peric1_uart_bt",
3158 mout_peric1_uart_bt_p, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT, 0, 2),
3159 MUX(CLK_MOUT_PERIC1_USI07, "mout_peric1_usi07", mout_peric1_usi07_p,
3160 CLK_CON_MUX_MUX_CLK_PERIC1_USI07, 0, 2),
3161 MUX(CLK_MOUT_PERIC1_USI07_SPI_I2C, "mout_peric1_usi07_spi_i2c",
3162 mout_peric1_usi07_spi_i2c_p,
3163 CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C, 0, 2),
3164 MUX(CLK_MOUT_PERIC1_USI08, "mout_peric1_usi08", mout_peric1_usi08_p,
3165 CLK_CON_MUX_MUX_CLK_PERIC1_USI08, 0, 2),
3166 MUX(CLK_MOUT_PERIC1_USI08_SPI_I2C, "mout_peric1_usi08_spi_i2c",
3167 mout_peric1_usi08_spi_i2c_p,
3168 CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C, 0, 2),
3169 MUX(CLK_MOUT_PERIC1_USI09, "mout_peric1_usi09", mout_peric1_usi09_p,
3170 CLK_CON_MUX_MUX_CLK_PERIC1_USI09, 0, 2),
3171 MUX(CLK_MOUT_PERIC1_USI10, "mout_peric1_usi10", mout_peric1_usi10_p,
3172 CLK_CON_MUX_MUX_CLK_PERIC1_USI10, 0, 2),
3173 };
3174
3175 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
3176 DIV(CLK_DOUT_PERIC1_I2C, "dout_peric1_i2c", "mout_peric1_i2c",
3177 CLK_CON_DIV_DIV_CLK_PERIC1_I2C, 0, 4),
3178 DIV(CLK_DOUT_PERIC1_SPI_MS_CTRL, "dout_peric1_spi_ms_ctrl",
3179 "mout_peric1_spi_ms_ctrl", CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL,
3180 0, 7),
3181 DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt",
3182 "mout_peric1_uart_bt", CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0, 4),
3183 DIV(CLK_DOUT_PERIC1_USI07, "dout_peric1_usi07", "mout_peric1_usi07",
3184 CLK_CON_DIV_DIV_CLK_PERIC1_USI07, 0, 7),
3185 DIV(CLK_DOUT_PERIC1_USI07_SPI_I2C, "dout_peric1_usi07_spi_i2c",
3186 "mout_peric1_usi07_spi_i2c",
3187 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C, 0, 4),
3188 DIV(CLK_DOUT_PERIC1_USI08, "dout_peric1_usi08", "mout_peric1_usi08",
3189 CLK_CON_DIV_DIV_CLK_PERIC1_USI08, 0, 7),
3190 DIV(CLK_DOUT_PERIC1_USI08_SPI_I2C, "dout_peric1_usi08_spi_i2c",
3191 "mout_peric1_usi08_spi_i2c",
3192 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C, 0, 4),
3193 DIV(CLK_DOUT_PERIC1_USI09, "dout_peric1_usi09", "mout_peric1_usi09",
3194 CLK_CON_DIV_DIV_CLK_PERIC1_USI09, 0, 7),
3195 DIV(CLK_DOUT_PERIC1_USI10, "dout_peric1_usi10", "mout_peric1_usi10",
3196 CLK_CON_DIV_DIV_CLK_PERIC1_USI10, 0, 7),
3197 };
3198
3199 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
3200 .mux_clks = peric1_mux_clks,
3201 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
3202 .div_clks = peric1_div_clks,
3203 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
3204 .nr_clk_ids = CLKS_NR_PERIC1,
3205 .clk_regs = peric1_clk_regs,
3206 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
3207 .clk_name = "noc",
3208 };
3209
3210 /* ---- CMU_PERIC2 --------------------------------------------------------- */
3211
3212 /* Register Offset definitions for CMU_PERIC2 (0x11c00000) */
3213 #define PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER 0x600
3214 #define PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER 0x604
3215 #define PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER 0x610
3216 #define PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER 0x614
3217 #define PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER 0x620
3218 #define PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER 0x624
3219 #define CLK_CON_MUX_MUX_CLK_PERIC2_I2C 0x1000
3220 #define CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL 0x1004
3221 #define CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG 0x1008
3222 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI00 0x100c
3223 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C 0x1010
3224 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI01 0x1014
3225 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C 0x1018
3226 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI02 0x101c
3227 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI03 0x1020
3228 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI05 0x1024
3229 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI06 0x1028
3230 #define CLK_CON_MUX_MUX_CLK_PERIC2_USI11 0x102c
3231 #define CLK_CON_DIV_DIV_CLK_PERIC2_I2C 0x1800
3232 #define CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL 0x1804
3233 #define CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG 0x1808
3234 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI00 0x180c
3235 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C 0x1810
3236 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI01 0x1814
3237 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C 0x1818
3238 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI02 0x181c
3239 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI03 0x1820
3240 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI05 0x1824
3241 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI06 0x1828
3242 #define CLK_CON_DIV_DIV_CLK_PERIC2_USI11 0x182c
3243 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK 0x2000
3244 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK 0x2004
3245 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK 0x2008
3246 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK 0x200c
3247 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK 0x2010
3248 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK 0x2014
3249 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK 0x2018
3250 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK 0x201c
3251 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK 0x2020
3252 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK 0x2024
3253 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK 0x2028
3254 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK 0x202c
3255 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK 0x2030
3256 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK 0x2034
3257 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK 0x2038
3258 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK 0x203c
3259 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK 0x2040
3260 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK 0x2044
3261 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK 0x2048
3262 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK 0x204c
3263 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK 0x2050
3264 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK 0x2054
3265 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK 0x2058
3266 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0 0x205c
3267 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK 0x2060
3268 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK 0x2064
3269 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK 0x2068
3270 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK 0x206c
3271 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK 0x2070
3272 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK 0x2074
3273 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK 0x2078
3274 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK 0x207c
3275 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK 0x2080
3276 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK 0x2084
3277 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK 0x2088
3278 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK 0x208c
3279 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK 0x2090
3280 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK 0x2094
3281 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK 0x2098
3282 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK 0x209c
3283 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK 0x20a0
3284 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK 0x20a4
3285 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK 0x20a8
3286 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK 0x20ac
3287 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK 0x20b0
3288 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK 0x20b4
3289 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK 0x20b8
3290 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK 0x20bc
3291 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK 0x20c0
3292 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK 0x20c4
3293 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK 0x20c8
3294 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK 0x20cc
3295 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK 0x20d0
3296 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK 0x20d4
3297 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK 0x20d8
3298 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK 0x20dc
3299 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK 0x20e0
3300 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK 0x20e4
3301 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK 0x20e8
3302 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK 0x20ec
3303 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK 0x20f0
3304 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK 0x20f4
3305 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK 0x20f8
3306 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK 0x20fc
3307 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK 0x2100
3308 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK 0x2104
3309 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK 0x2108
3310 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK 0x210c
3311 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK 0x2110
3312 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK 0x2114
3313 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK 0x2118
3314 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK 0x211c
3315 #define CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK 0x2120
3316
3317 static const unsigned long peric2_clk_regs[] __initconst = {
3318 PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER,
3319 PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER,
3320 PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER,
3321 PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER,
3322 PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER,
3323 PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER,
3324 CLK_CON_MUX_MUX_CLK_PERIC2_I2C,
3325 CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL,
3326 CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG,
3327 CLK_CON_MUX_MUX_CLK_PERIC2_USI00,
3328 CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C,
3329 CLK_CON_MUX_MUX_CLK_PERIC2_USI01,
3330 CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C,
3331 CLK_CON_MUX_MUX_CLK_PERIC2_USI02,
3332 CLK_CON_MUX_MUX_CLK_PERIC2_USI03,
3333 CLK_CON_MUX_MUX_CLK_PERIC2_USI05,
3334 CLK_CON_MUX_MUX_CLK_PERIC2_USI06,
3335 CLK_CON_MUX_MUX_CLK_PERIC2_USI11,
3336 CLK_CON_DIV_DIV_CLK_PERIC2_I2C,
3337 CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL,
3338 CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG,
3339 CLK_CON_DIV_DIV_CLK_PERIC2_USI00,
3340 CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C,
3341 CLK_CON_DIV_DIV_CLK_PERIC2_USI01,
3342 CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C,
3343 CLK_CON_DIV_DIV_CLK_PERIC2_USI02,
3344 CLK_CON_DIV_DIV_CLK_PERIC2_USI03,
3345 CLK_CON_DIV_DIV_CLK_PERIC2_USI05,
3346 CLK_CON_DIV_DIV_CLK_PERIC2_USI06,
3347 CLK_CON_DIV_DIV_CLK_PERIC2_USI11,
3348 CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK,
3349 CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK,
3350 CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK,
3351 CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK,
3352 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK,
3353 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK,
3354 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK,
3355 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK,
3356 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK,
3357 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK,
3358 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK,
3359 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK,
3360 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK,
3361 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK,
3362 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK,
3363 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK,
3364 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK,
3365 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK,
3366 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK,
3367 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK,
3368 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK,
3369 CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK,
3370 CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK,
3371 CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0,
3372 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK,
3373 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK,
3374 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK,
3375 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK,
3376 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK,
3377 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK,
3378 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK,
3379 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK,
3380 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK,
3381 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK,
3382 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK,
3383 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK,
3384 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK,
3385 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK,
3386 CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK,
3387 CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK,
3388 CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK,
3389 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK,
3390 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK,
3391 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK,
3392 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK,
3393 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK,
3394 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK,
3395 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK,
3396 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK,
3397 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK,
3398 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK,
3399 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK,
3400 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK,
3401 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK,
3402 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK,
3403 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK,
3404 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK,
3405 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK,
3406 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK,
3407 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK,
3408 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK,
3409 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK,
3410 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK,
3411 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK,
3412 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK,
3413 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK,
3414 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK,
3415 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK,
3416 CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK,
3417 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK,
3418 CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK,
3419 CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK,
3420 CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK,
3421 };
3422
3423 PNAME(mout_peric2_ip0_user_p) = { "oscclk",
3424 "dout_cmu_peric2_ip0" };
3425 PNAME(mout_peric2_ip1_user_p) = { "oscclk",
3426 "dout_cmu_peric2_ip1" };
3427 PNAME(mout_peric2_noc_user_p) = { "oscclk",
3428 "dout_cmu_peric2_noc" };
3429 PNAME(mout_peric2_i2c_p) = { "oscclk",
3430 "mout_peric2_ip0_user",
3431 "mout_peric2_ip1_user",
3432 "oscclk" };
3433 PNAME(mout_peric2_spi_ms_ctrl_p) = { "oscclk",
3434 "mout_peric2_ip0_user",
3435 "mout_peric2_ip1_user",
3436 "oscclk" };
3437 PNAME(mout_peric2_uart_dbg_p) = { "oscclk",
3438 "mout_peric2_ip0_user",
3439 "mout_peric2_ip1_user",
3440 "oscclk" };
3441 PNAME(mout_peric2_usi00_p) = { "oscclk",
3442 "mout_peric2_ip0_user",
3443 "mout_peric2_ip1_user",
3444 "oscclk" };
3445 PNAME(mout_peric2_usi00_spi_i2c_p) = { "oscclk",
3446 "mout_peric2_ip0_user",
3447 "mout_peric2_ip1_user",
3448 "oscclk" };
3449 PNAME(mout_peric2_usi01_p) = { "oscclk",
3450 "mout_peric2_ip0_user",
3451 "mout_peric2_ip1_user",
3452 "oscclk" };
3453 PNAME(mout_peric2_usi01_spi_i2c_p) = { "oscclk",
3454 "mout_peric2_ip0_user",
3455 "mout_peric2_ip1_user",
3456 "oscclk" };
3457 PNAME(mout_peric2_usi02_p) = { "oscclk",
3458 "mout_peric2_ip0_user",
3459 "mout_peric2_ip1_user",
3460 "oscclk" };
3461 PNAME(mout_peric2_usi03_p) = { "oscclk",
3462 "mout_peric2_ip0_user",
3463 "mout_peric2_ip1_user",
3464 "oscclk" };
3465 PNAME(mout_peric2_usi05_p) = { "oscclk",
3466 "mout_peric2_ip0_user",
3467 "mout_peric2_ip1_user",
3468 "oscclk" };
3469 PNAME(mout_peric2_usi06_p) = { "oscclk",
3470 "mout_peric2_ip0_user",
3471 "mout_peric2_ip1_user",
3472 "oscclk" };
3473 PNAME(mout_peric2_usi11_p) = { "oscclk",
3474 "mout_peric2_ip0_user",
3475 "mout_peric2_ip1_user",
3476 "oscclk" };
3477
3478 static const struct samsung_mux_clock peric2_mux_clks[] __initconst = {
3479 MUX(CLK_MOUT_PERIC2_IP0_USER, "mout_peric2_ip0_user",
3480 mout_peric2_ip0_user_p, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER, 4, 1),
3481 MUX(CLK_MOUT_PERIC2_IP1_USER, "mout_peric2_ip1_user",
3482 mout_peric2_ip1_user_p, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER, 4, 1),
3483 MUX(CLK_MOUT_PERIC2_NOC_USER, "mout_peric2_noc_user",
3484 mout_peric2_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER, 4, 1),
3485 MUX(CLK_MOUT_PERIC2_I2C, "mout_peric2_i2c", mout_peric2_i2c_p,
3486 CLK_CON_MUX_MUX_CLK_PERIC2_I2C, 0, 2),
3487 MUX(CLK_MOUT_PERIC2_SPI_MS_CTRL, "mout_peric2_spi_ms_ctrl",
3488 mout_peric2_spi_ms_ctrl_p,
3489 CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL, 0, 2),
3490 MUX(CLK_MOUT_PERIC2_UART_DBG, "mout_peric2_uart_dbg",
3491 mout_peric2_uart_dbg_p, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG, 0, 2),
3492 MUX(CLK_MOUT_PERIC2_USI00, "mout_peric2_usi00", mout_peric2_usi00_p,
3493 CLK_CON_MUX_MUX_CLK_PERIC2_USI00, 0, 2),
3494 MUX(CLK_MOUT_PERIC2_USI00_SPI_I2C, "mout_peric2_usi00_spi_i2c",
3495 mout_peric2_usi00_spi_i2c_p, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C,
3496 0, 2),
3497 MUX(CLK_MOUT_PERIC2_USI01, "mout_peric2_usi01", mout_peric2_usi01_p,
3498 CLK_CON_MUX_MUX_CLK_PERIC2_USI01, 0, 2),
3499 MUX(CLK_MOUT_PERIC2_USI01_SPI_I2C, "mout_peric2_usi01_spi_i2c",
3500 mout_peric2_usi01_spi_i2c_p,
3501 CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C, 0, 2),
3502 MUX(CLK_MOUT_PERIC2_USI02, "mout_peric2_usi02", mout_peric2_usi02_p,
3503 CLK_CON_MUX_MUX_CLK_PERIC2_USI02, 0, 2),
3504 MUX(CLK_MOUT_PERIC2_USI03, "mout_peric2_usi03", mout_peric2_usi03_p,
3505 CLK_CON_MUX_MUX_CLK_PERIC2_USI03, 0, 2),
3506 MUX(CLK_MOUT_PERIC2_USI05, "mout_peric2_usi05", mout_peric2_usi05_p,
3507 CLK_CON_MUX_MUX_CLK_PERIC2_USI05, 0, 2),
3508 MUX(CLK_MOUT_PERIC2_USI06, "mout_peric2_usi06", mout_peric2_usi06_p,
3509 CLK_CON_MUX_MUX_CLK_PERIC2_USI06, 0, 2),
3510 MUX(CLK_MOUT_PERIC2_USI11, "mout_peric2_usi11", mout_peric2_usi11_p,
3511 CLK_CON_MUX_MUX_CLK_PERIC2_USI11, 0, 2),
3512 };
3513
3514 static const struct samsung_div_clock peric2_div_clks[] __initconst = {
3515 DIV(CLK_DOUT_PERIC2_I2C, "dout_peric2_i2c", "mout_peric2_i2c",
3516 CLK_CON_DIV_DIV_CLK_PERIC2_I2C, 0, 4),
3517 DIV(CLK_DOUT_PERIC2_SPI_MS_CTRL, "dout_peric2_spi_ms_ctrl",
3518 "mout_peric2_spi_ms_ctrl", CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL,
3519 0, 7),
3520 DIV(CLK_DOUT_PERIC2_UART_DBG, "dout_peric2_uart_dbg",
3521 "mout_peric2_uart_dbg", CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG, 0, 4),
3522 DIV(CLK_DOUT_PERIC2_USI00, "dout_peric2_usi00", "mout_peric2_usi00",
3523 CLK_CON_DIV_DIV_CLK_PERIC2_USI00, 0, 7),
3524 DIV(CLK_DOUT_PERIC2_USI00_SPI_I2C, "dout_peric2_usi00_spi_i2c",
3525 "mout_peric2_usi00_spi_i2c",
3526 CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C, 0, 4),
3527 DIV(CLK_DOUT_PERIC2_USI01, "dout_peric2_usi01", "mout_peric2_usi01",
3528 CLK_CON_DIV_DIV_CLK_PERIC2_USI01, 0, 7),
3529 DIV(CLK_DOUT_PERIC2_USI01_SPI_I2C, "dout_peric2_usi01_spi_i2c",
3530 "mout_peric2_usi01_spi_i2c",
3531 CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C, 0, 4),
3532 DIV(CLK_DOUT_PERIC2_USI02, "dout_peric2_usi02", "mout_peric2_usi02",
3533 CLK_CON_DIV_DIV_CLK_PERIC2_USI02, 0, 7),
3534 DIV(CLK_DOUT_PERIC2_USI03, "dout_peric2_usi03", "mout_peric2_usi03",
3535 CLK_CON_DIV_DIV_CLK_PERIC2_USI03, 0, 7),
3536 DIV(CLK_DOUT_PERIC2_USI05, "dout_peric2_usi05", "mout_peric2_usi05",
3537 CLK_CON_DIV_DIV_CLK_PERIC2_USI05, 0, 7),
3538 DIV(CLK_DOUT_PERIC2_USI06, "dout_peric2_usi06", "mout_peric2_usi06",
3539 CLK_CON_DIV_DIV_CLK_PERIC2_USI06, 0, 7),
3540 DIV(CLK_DOUT_PERIC2_USI11, "dout_peric2_usi11", "mout_peric2_usi11",
3541 CLK_CON_DIV_DIV_CLK_PERIC2_USI11, 0, 7),
3542 };
3543
3544 static const struct samsung_cmu_info peric2_cmu_info __initconst = {
3545 .mux_clks = peric2_mux_clks,
3546 .nr_mux_clks = ARRAY_SIZE(peric2_mux_clks),
3547 .div_clks = peric2_div_clks,
3548 .nr_div_clks = ARRAY_SIZE(peric2_div_clks),
3549 .nr_clk_ids = CLKS_NR_PERIC2,
3550 .clk_regs = peric2_clk_regs,
3551 .nr_clk_regs = ARRAY_SIZE(peric2_clk_regs),
3552 .clk_name = "noc",
3553 };
3554
3555 /* ---- CMU_UFS ------------------------------------------------------------ */
3556
3557 /* Register Offset definitions for CMU_UFS(0x11000000) */
3558 #define PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER 0x600
3559 #define PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER 0x604
3560 #define PLL_CON0_MUX_CLKCMU_UFS_NOC_USER 0x610
3561 #define PLL_CON1_MUX_CLKCMU_UFS_NOC_USER 0x614
3562 #define PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER 0x620
3563 #define PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER 0x624
3564 #define CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x2000
3565 #define CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK 0x2004
3566 #define CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK 0x2008
3567 #define CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK 0x200c
3568 #define CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK 0x2010
3569 #define CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2014
3570 #define CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2018
3571 #define CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK 0x201c
3572 #define CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK 0x2024
3573 #define CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK 0x2028
3574 #define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK 0x202c
3575 #define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK 0x2030
3576 #define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK 0x2034
3577 #define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK 0x2038
3578 #define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK 0x203c
3579 #define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK 0x2040
3580 #define CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK 0x2044
3581 #define CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK 0x2048
3582 #define CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK 0x204c
3583 #define CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2 0x2050
3584 #define CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK 0x2054
3585 #define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK 0x2058
3586 #define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x205c
3587 #define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2060
3588 #define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x2064
3589 #define CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK 0x2068
3590 #define CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK 0x206c
3591 #define CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK 0x2070
3592
3593 static const unsigned long ufs_clk_regs[] __initconst = {
3594 PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER,
3595 PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER,
3596 PLL_CON0_MUX_CLKCMU_UFS_NOC_USER,
3597 PLL_CON1_MUX_CLKCMU_UFS_NOC_USER,
3598 PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER,
3599 PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER,
3600 CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
3601 CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK,
3602 CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK,
3603 CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK,
3604 CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK,
3605 CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK,
3606 CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
3607 CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK,
3608 CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK,
3609 CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK,
3610 CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK,
3611 CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK,
3612 CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK,
3613 CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK,
3614 CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK,
3615 CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK,
3616 CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK,
3617 CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK,
3618 CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK,
3619 CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2,
3620 CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK,
3621 CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK,
3622 CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
3623 CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
3624 CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
3625 CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK,
3626 CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK,
3627 CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK,
3628 };
3629
3630 PNAME(mout_clkcmu_ufs_mmc_card_user_p) = { "oscclk",
3631 "mout_cmu_ufs_mmc_card" };
3632 PNAME(mout_clkcmu_ufs_noc_user_p) = { "oscclk", "dout_cmu_ufs_noc" };
3633 PNAME(mout_clkcmu_ufs_ufs_embd_user_p) = { "oscclk",
3634 "dout_cmu_ufs_ufs_embd" };
3635
3636 static const struct samsung_mux_clock ufs_mux_clks[] __initconst = {
3637 MUX(CLK_MOUT_UFS_MMC_CARD_USER, "mout_ufs_mmc_card_user",
3638 mout_clkcmu_ufs_mmc_card_user_p,
3639 PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER, 4, 1),
3640 MUX(CLK_MOUT_UFS_NOC_USER, "mout_ufs_noc_user",
3641 mout_clkcmu_ufs_noc_user_p,
3642 PLL_CON0_MUX_CLKCMU_UFS_NOC_USER, 4, 1),
3643 MUX(CLK_MOUT_UFS_UFS_EMBD_USER, "mout_ufs_ufs_embd_user",
3644 mout_clkcmu_ufs_ufs_embd_user_p,
3645 PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER, 4, 1),
3646 };
3647
3648 static const struct samsung_cmu_info ufs_cmu_info __initconst = {
3649 .mux_clks = ufs_mux_clks,
3650 .nr_mux_clks = ARRAY_SIZE(ufs_mux_clks),
3651 .nr_clk_ids = CLKS_NR_UFS,
3652 .clk_regs = ufs_clk_regs,
3653 .nr_clk_regs = ARRAY_SIZE(ufs_clk_regs),
3654 .clk_name = "noc",
3655 };
3656
3657 /* ---- CMU_VTS ------------------------------------------------------------ */
3658
3659 /* Register Offset definitions for CMU_VTS (0x15300000) */
3660 #define PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER 0x600
3661 #define PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER 0x604
3662 #define PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER 0x610
3663 #define PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER 0x614
3664 #define PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER 0x620
3665 #define PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER 0x624
3666 #define CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1 0x1000
3667 #define CLK_CON_MUX_MUX_CLK_VTS_NOC 0x1004
3668 #define CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD 0x100c
3669 #define CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0 0x1800
3670 #define CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1 0x1804
3671 #define CLK_CON_DIV_DIV_CLK_VTS_CPU 0x1808
3672 #define CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF 0x1814
3673 #define CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2 0x1818
3674 #define CLK_CON_DIV_DIV_CLK_VTS_NOC 0x181c
3675 #define CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF 0x1820
3676 #define CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE 0x1824
3677 #define CLK_CON_GAT_CLKVTS_AUD_DMIC0 0x2000
3678 #define CLK_CON_GAT_CLKVTS_AUD_DMIC1 0x2004
3679 #define CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK 0x2008
3680 #define CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK 0x200c
3681 #define CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK 0x2010
3682 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK 0x2014
3683 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK 0x2018
3684 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK 0x2020
3685 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK 0x2024
3686 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK 0x2028
3687 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK 0x202c
3688 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x2030
3689 #define CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK 0x2034
3690 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK 0x2068
3691 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK 0x206c
3692 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK 0x2070
3693 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK 0x2074
3694 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK 0x2078
3695 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK 0x207c
3696 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK 0x2080
3697 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK 0x2084
3698 #define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK 0x2088
3699 #define CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK 0x2090
3700 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK 0x20ac
3701 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK 0x20b0
3702 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK 0x20b4
3703 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK 0x20b8
3704 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK 0x20bc
3705 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK 0x20c0
3706 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK 0x20c4
3707 #define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK 0x20c8
3708 #define CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK 0x20cc
3709 #define CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK 0x20d0
3710 #define CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK 0x20d4
3711 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK 0x20ec
3712 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK 0x20f8
3713 #define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK 0x20fc
3714 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK 0x2104
3715 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK 0x2108
3716 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK 0x210c
3717 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU 0x2124
3718 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK 0x2128
3719 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0 0x212c
3720 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1 0x2130
3721 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2 0x2134
3722 #define CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK 0x213c
3723 #define CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK 0x2140
3724 #define CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK 0x2144
3725 #define CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK 0x2148
3726 #define CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK 0x2150
3727 #define CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK 0x2154
3728 #define CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK 0x2158
3729 #define CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN 0x215c
3730 #define CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK 0x2160
3731 #define CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK 0x2164
3732
3733 static const unsigned long vts_clk_regs[] __initconst = {
3734 PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER,
3735 PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER,
3736 PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER,
3737 PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER,
3738 PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER,
3739 PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER,
3740 CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1,
3741 CLK_CON_MUX_MUX_CLK_VTS_NOC,
3742 CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD,
3743 CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0,
3744 CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1,
3745 CLK_CON_DIV_DIV_CLK_VTS_CPU,
3746 CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF,
3747 CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2,
3748 CLK_CON_DIV_DIV_CLK_VTS_NOC,
3749 CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF,
3750 CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE,
3751 CLK_CON_GAT_CLKVTS_AUD_DMIC0,
3752 CLK_CON_GAT_CLKVTS_AUD_DMIC1,
3753 CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK,
3754 CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK,
3755 CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK,
3756 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK,
3757 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
3758 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK,
3759 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK,
3760 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK,
3761 CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK,
3762 CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
3763 CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK,
3764 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK,
3765 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK,
3766 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK,
3767 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK,
3768 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK,
3769 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK,
3770 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK,
3771 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK,
3772 CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK,
3773 CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
3774 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK,
3775 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK,
3776 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK,
3777 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK,
3778 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK,
3779 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK,
3780 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK,
3781 CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK,
3782 CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
3783 CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
3784 CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK,
3785 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK,
3786 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK,
3787 CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK,
3788 CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK,
3789 CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK,
3790 CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK,
3791 CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
3792 CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK,
3793 CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0,
3794 CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1,
3795 CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2,
3796 CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
3797 CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK,
3798 CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK,
3799 CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK,
3800 CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
3801 CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
3802 CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK,
3803 CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN,
3804 CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK,
3805 CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK,
3806 };
3807
3808 PNAME(mout_clkalive_vts_noc_user_p) = { "oscclk" };
3809 PNAME(mout_clkalive_vts_rco_user_p) = { "oscclk" };
3810 PNAME(mout_clkcmu_vts_dmic_user_p) = { "oscclk", "dout_cmu_vts_dmic" };
3811 PNAME(mout_clkvts_aud_dmic1_p) = { "dout_clkvts_aud_dmic1",
3812 "dout_clkvts_dmic_if_div2",
3813 "dmic_clk0_in", "dmic_clk1_in",
3814 "dmic_clk2_in", "oscclk", "oscclk",
3815 "oscclk" };
3816 PNAME(mout_clkvts_noc_p) = { "mout_clkalive_vts_noc_user",
3817 "mout_clkalive_vts_rco_user" };
3818 PNAME(mout_clkvts_dmic_pad_p) = { "mout_clkalive_vts_rco_user",
3819 "mout_clkcmu_vts_dmic_user" };
3820
3821 static const struct samsung_mux_clock vts_mux_clks[] __initconst = {
3822 MUX(CLK_MOUT_CLKALIVE_VTS_NOC_USER, "mout_clkalive_vts_noc_user",
3823 mout_clkalive_vts_noc_user_p, PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER,
3824 4, 1),
3825 MUX(CLK_MOUT_CLKALIVE_VTS_RCO_USER, "mout_clkalive_vts_rco_user",
3826 mout_clkalive_vts_rco_user_p, PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER,
3827 4, 1),
3828 MUX(CLK_MOUT_CLKCMU_VTS_DMIC_USER, "mout_clkcmu_vts_dmic_user",
3829 mout_clkcmu_vts_dmic_user_p, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER,
3830 4, 1),
3831 MUX(CLK_MOUT_CLKVTS_AUD_DMIC1, "mout_clkvts_aud_dmic1",
3832 mout_clkvts_aud_dmic1_p, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1, 0, 3),
3833 MUX(CLK_MOUT_CLKVTS_NOC, "mout_clkvts_noc", mout_clkvts_noc_p,
3834 CLK_CON_MUX_MUX_CLK_VTS_NOC, 0, 1),
3835 MUX(CLK_MOUT_CLKVTS_DMIC_PAD, "mout_clkvts_dmic_pad",
3836 mout_clkvts_dmic_pad_p, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD, 0, 1),
3837 };
3838
3839 static const struct samsung_div_clock vts_div_clks[] __initconst = {
3840 DIV(CLK_DOUT_CLKVTS_AUD_DMIC0, "dout_clkvts_aud_dmic0",
3841 "mout_clkvts_dmic_pad", CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0, 0, 5),
3842 DIV(CLK_DOUT_CLKVTS_AUD_DMIC1, "dout_clkvts_aud_dmic1",
3843 "dout_clkvts_aud_dmic0", CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1, 0, 4),
3844 DIV(CLK_DOUT_CLKVTS_CPU, "dout_clkvts_cpu", "mout_clkvts_noc",
3845 CLK_CON_DIV_DIV_CLK_VTS_CPU, 0, 3),
3846 DIV(CLK_DOUT_CLKVTS_DMIC_IF, "dout_clkvts_dmic_if",
3847 "dout_clkvts_aud_dmic0", CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, 0, 7),
3848 DIV(CLK_DOUT_CLKVTS_DMIC_IF_DIV2, "dout_clkvts_dmic_if_div2",
3849 "dout_clkvts_dmic_if", CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, 0, 4),
3850 DIV(CLK_DOUT_CLKVTS_NOC, "dout_clkvts_noc", "dout_clkvts_cpu",
3851 CLK_CON_DIV_DIV_CLK_VTS_NOC, 0, 3),
3852 DIV(CLK_DOUT_CLKVTS_SERIAL_LIF, "dout_clkvts_serial_lif",
3853 "mout_clkalive_vts_rco_user", CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF,
3854 0, 7),
3855 DIV(CLK_DOUT_CLKVTS_SERIAL_LIF_CORE, "dout_clkvts_serial_lif_core",
3856 "mout_clkalive_vts_rco_user",
3857 CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE, 0, 7),
3858 };
3859
3860 static const struct samsung_fixed_rate_clock vts_fixed_clks[] __initconst = {
3861 FRATE(0, "dmic_clk0_in", NULL, 0, 100000000),
3862 FRATE(0, "dmic_clk1_in", NULL, 0, 100000000),
3863 FRATE(0, "dmic_clk2_in", NULL, 0, 100000000),
3864 };
3865
3866 static const struct samsung_cmu_info vts_cmu_info __initconst = {
3867 .mux_clks = vts_mux_clks,
3868 .nr_mux_clks = ARRAY_SIZE(vts_mux_clks),
3869 .div_clks = vts_div_clks,
3870 .nr_div_clks = ARRAY_SIZE(vts_div_clks),
3871 .fixed_clks = vts_fixed_clks,
3872 .nr_fixed_clks = ARRAY_SIZE(vts_fixed_clks),
3873 .nr_clk_ids = CLKS_NR_VTS,
3874 .clk_regs = vts_clk_regs,
3875 .nr_clk_regs = ARRAY_SIZE(vts_clk_regs),
3876 .clk_name = "dmic",
3877 };
3878
exynos2200_cmu_probe(struct platform_device * pdev)3879 static int __init exynos2200_cmu_probe(struct platform_device *pdev)
3880 {
3881 const struct samsung_cmu_info *info;
3882 struct device *dev = &pdev->dev;
3883
3884 info = of_device_get_match_data(dev);
3885 exynos_arm64_register_cmu(dev, dev->of_node, info);
3886
3887 return 0;
3888 }
3889
3890 static const struct of_device_id exynos2200_cmu_of_match[] = {
3891 {
3892 .compatible = "samsung,exynos2200-cmu-cmgp",
3893 .data = &cmgp_cmu_info,
3894 }, {
3895 .compatible = "samsung,exynos2200-cmu-hsi0",
3896 .data = &hsi0_cmu_info,
3897 }, {
3898 .compatible = "samsung,exynos2200-cmu-peric0",
3899 .data = &peric0_cmu_info,
3900 }, {
3901 .compatible = "samsung,exynos2200-cmu-peric1",
3902 .data = &peric1_cmu_info,
3903 }, {
3904 .compatible = "samsung,exynos2200-cmu-peric2",
3905 .data = &peric2_cmu_info,
3906 }, {
3907 .compatible = "samsung,exynos2200-cmu-ufs",
3908 .data = &ufs_cmu_info,
3909 }, {
3910 .compatible = "samsung,exynos2200-cmu-vts",
3911 .data = &vts_cmu_info,
3912 }, { }
3913 };
3914
3915 static struct platform_driver exynos2200_cmu_driver __refdata = {
3916 .driver = {
3917 .name = "exynos2200-cmu",
3918 .of_match_table = exynos2200_cmu_of_match,
3919 .suppress_bind_attrs = true,
3920 },
3921 .probe = exynos2200_cmu_probe,
3922 };
3923
exynos2200_cmu_init(void)3924 static int __init exynos2200_cmu_init(void)
3925 {
3926 return platform_driver_register(&exynos2200_cmu_driver);
3927 }
3928 core_initcall(exynos2200_cmu_init);
3929