1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 * Author: Detlev Casanova <detlev.casanova@collabora.com>
6 * Based on Sebastien Reichel's implementation for RK3588
7 */
8
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
12 #include "clk.h"
13
14 /* 0xff100000 + 0x0A00 */
15 #define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0xff110000 + 0x0A00 */
17 #define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
18 /* 0xff118000 + 0x0A00 */
19 #define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit)
20 /* 0xff120000 + 0x0A00 */
21 #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
22 /* 0xff128000 + 0x0A00 */
23 #define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit)
24 /* 0xff130000 + 0x0A00 */
25 #define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
26
27 /* mapping table for reset ID to register offset */
28 static const int rk3562_register_offset[] = {
29 /* SOFTRST_CON01 */
30 RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0),
31 RK3562_CRU_RESET_OFFSET(SRST_A_TOP_VIO_BIU, 1, 1),
32 RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_LOGIC, 1, 2),
33
34 /* SOFTRST_CON03 */
35 RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0),
36 RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET1, 3, 1),
37 RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET2, 3, 2),
38 RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET3, 3, 3),
39 RK3562_CRU_RESET_OFFSET(SRST_NCORESET0, 3, 4),
40 RK3562_CRU_RESET_OFFSET(SRST_NCORESET1, 3, 5),
41 RK3562_CRU_RESET_OFFSET(SRST_NCORESET2, 3, 6),
42 RK3562_CRU_RESET_OFFSET(SRST_NCORESET3, 3, 7),
43 RK3562_CRU_RESET_OFFSET(SRST_NL2RESET, 3, 8),
44
45 /* SOFTRST_CON04 */
46 RK3562_CRU_RESET_OFFSET(SRST_DAP, 4, 9),
47 RK3562_CRU_RESET_OFFSET(SRST_P_DBG_DAPLITE, 4, 10),
48 RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 4, 13),
49
50 /* SOFTRST_CON05 */
51 RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0),
52 RK3562_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 5, 1),
53 RK3562_CRU_RESET_OFFSET(SRST_H_CORE_BIU, 5, 2),
54
55 /* SOFTRST_CON06 */
56 RK3562_CRU_RESET_OFFSET(SRST_A_NPU_BIU, 6, 2),
57 RK3562_CRU_RESET_OFFSET(SRST_H_NPU_BIU, 6, 3),
58 RK3562_CRU_RESET_OFFSET(SRST_A_RKNN, 6, 4),
59 RK3562_CRU_RESET_OFFSET(SRST_H_RKNN, 6, 5),
60 RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 6, 6),
61
62 /* SOFTRST_CON08 */
63 RK3562_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 8, 3),
64 RK3562_CRU_RESET_OFFSET(SRST_GPU, 8, 4),
65 RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 8, 5),
66 RK3562_CRU_RESET_OFFSET(SRST_GPU_BRG_BIU, 8, 8),
67
68 /* SOFTRST_CON09 */
69 RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0),
70 RK3562_CRU_RESET_OFFSET(SRST_A_VEPU_BIU, 9, 3),
71 RK3562_CRU_RESET_OFFSET(SRST_H_VEPU_BIU, 9, 4),
72 RK3562_CRU_RESET_OFFSET(SRST_A_RKVENC, 9, 5),
73 RK3562_CRU_RESET_OFFSET(SRST_H_RKVENC, 9, 6),
74
75 /* SOFTRST_CON10 */
76 RK3562_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 10, 2),
77 RK3562_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 10, 5),
78 RK3562_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 10, 6),
79 RK3562_CRU_RESET_OFFSET(SRST_A_RKVDEC, 10, 7),
80 RK3562_CRU_RESET_OFFSET(SRST_H_RKVDEC, 10, 8),
81
82 /* SOFTRST_CON11 */
83 RK3562_CRU_RESET_OFFSET(SRST_A_VI_BIU, 11, 3),
84 RK3562_CRU_RESET_OFFSET(SRST_H_VI_BIU, 11, 4),
85 RK3562_CRU_RESET_OFFSET(SRST_P_VI_BIU, 11, 5),
86 RK3562_CRU_RESET_OFFSET(SRST_ISP, 11, 8),
87 RK3562_CRU_RESET_OFFSET(SRST_A_VICAP, 11, 9),
88 RK3562_CRU_RESET_OFFSET(SRST_H_VICAP, 11, 10),
89 RK3562_CRU_RESET_OFFSET(SRST_D_VICAP, 11, 11),
90 RK3562_CRU_RESET_OFFSET(SRST_I0_VICAP, 11, 12),
91 RK3562_CRU_RESET_OFFSET(SRST_I1_VICAP, 11, 13),
92 RK3562_CRU_RESET_OFFSET(SRST_I2_VICAP, 11, 14),
93 RK3562_CRU_RESET_OFFSET(SRST_I3_VICAP, 11, 15),
94
95 /* SOFTRST_CON12 */
96 RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST0, 12, 0),
97 RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST1, 12, 1),
98 RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST2, 12, 2),
99 RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST3, 12, 3),
100 RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 12, 4),
101 RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 12, 5),
102
103 /* SOFTRST_CON13 */
104 RK3562_CRU_RESET_OFFSET(SRST_A_VO_BIU, 13, 3),
105 RK3562_CRU_RESET_OFFSET(SRST_H_VO_BIU, 13, 4),
106 RK3562_CRU_RESET_OFFSET(SRST_A_VOP, 13, 6),
107 RK3562_CRU_RESET_OFFSET(SRST_H_VOP, 13, 7),
108 RK3562_CRU_RESET_OFFSET(SRST_D_VOP, 13, 8),
109 RK3562_CRU_RESET_OFFSET(SRST_D_VOP1, 13, 9),
110
111 /* SOFTRST_CON14 */
112 RK3562_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 14, 3),
113 RK3562_CRU_RESET_OFFSET(SRST_H_RGA_BIU, 14, 4),
114 RK3562_CRU_RESET_OFFSET(SRST_A_RGA, 14, 6),
115 RK3562_CRU_RESET_OFFSET(SRST_H_RGA, 14, 7),
116 RK3562_CRU_RESET_OFFSET(SRST_RGA_CORE, 14, 8),
117 RK3562_CRU_RESET_OFFSET(SRST_A_JDEC, 14, 9),
118 RK3562_CRU_RESET_OFFSET(SRST_H_JDEC, 14, 10),
119
120 /* SOFTRST_CON15 */
121 RK3562_CRU_RESET_OFFSET(SRST_B_EBK_BIU, 15, 2),
122 RK3562_CRU_RESET_OFFSET(SRST_P_EBK_BIU, 15, 3),
123 RK3562_CRU_RESET_OFFSET(SRST_AHB2AXI_EBC, 15, 4),
124 RK3562_CRU_RESET_OFFSET(SRST_H_EBC, 15, 5),
125 RK3562_CRU_RESET_OFFSET(SRST_D_EBC, 15, 6),
126 RK3562_CRU_RESET_OFFSET(SRST_H_EINK, 15, 7),
127 RK3562_CRU_RESET_OFFSET(SRST_P_EINK, 15, 8),
128
129 /* SOFTRST_CON16 */
130 RK3562_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 16, 2),
131 RK3562_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 16, 3),
132 RK3562_CRU_RESET_OFFSET(SRST_P_PCIE20, 16, 7),
133 RK3562_CRU_RESET_OFFSET(SRST_PCIE20_POWERUP, 16, 8),
134 RK3562_CRU_RESET_OFFSET(SRST_USB3OTG, 16, 10),
135
136 /* SOFTRST_CON17 */
137 RK3562_CRU_RESET_OFFSET(SRST_PIPEPHY, 17, 3),
138
139 /* SOFTRST_CON18 */
140 RK3562_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 18, 3),
141 RK3562_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 18, 4),
142 RK3562_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 18, 5),
143
144 /* SOFTRST_CON19 */
145 RK3562_CRU_RESET_OFFSET(SRST_P_I2C1, 19, 0),
146 RK3562_CRU_RESET_OFFSET(SRST_P_I2C2, 19, 1),
147 RK3562_CRU_RESET_OFFSET(SRST_P_I2C3, 19, 2),
148 RK3562_CRU_RESET_OFFSET(SRST_P_I2C4, 19, 3),
149 RK3562_CRU_RESET_OFFSET(SRST_P_I2C5, 19, 4),
150 RK3562_CRU_RESET_OFFSET(SRST_I2C1, 19, 6),
151 RK3562_CRU_RESET_OFFSET(SRST_I2C2, 19, 7),
152 RK3562_CRU_RESET_OFFSET(SRST_I2C3, 19, 8),
153 RK3562_CRU_RESET_OFFSET(SRST_I2C4, 19, 9),
154 RK3562_CRU_RESET_OFFSET(SRST_I2C5, 19, 10),
155
156 /* SOFTRST_CON20 */
157 RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO3, 20, 5),
158 RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO4, 20, 6),
159
160 /* SOFTRST_CON21 */
161 RK3562_CRU_RESET_OFFSET(SRST_P_TIMER, 21, 0),
162 RK3562_CRU_RESET_OFFSET(SRST_TIMER0, 21, 1),
163 RK3562_CRU_RESET_OFFSET(SRST_TIMER1, 21, 2),
164 RK3562_CRU_RESET_OFFSET(SRST_TIMER2, 21, 3),
165 RK3562_CRU_RESET_OFFSET(SRST_TIMER3, 21, 4),
166 RK3562_CRU_RESET_OFFSET(SRST_TIMER4, 21, 5),
167 RK3562_CRU_RESET_OFFSET(SRST_TIMER5, 21, 6),
168 RK3562_CRU_RESET_OFFSET(SRST_P_STIMER, 21, 7),
169 RK3562_CRU_RESET_OFFSET(SRST_STIMER0, 21, 8),
170 RK3562_CRU_RESET_OFFSET(SRST_STIMER1, 21, 9),
171
172 /* SOFTRST_CON22 */
173 RK3562_CRU_RESET_OFFSET(SRST_P_WDTNS, 22, 0),
174 RK3562_CRU_RESET_OFFSET(SRST_WDTNS, 22, 1),
175 RK3562_CRU_RESET_OFFSET(SRST_P_GRF, 22, 2),
176 RK3562_CRU_RESET_OFFSET(SRST_P_SGRF, 22, 3),
177 RK3562_CRU_RESET_OFFSET(SRST_P_MAILBOX, 22, 4),
178 RK3562_CRU_RESET_OFFSET(SRST_P_INTC, 22, 5),
179 RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400, 22, 6),
180 RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400_DEBUG, 22, 7),
181
182 /* SOFTRST_CON23 */
183 RK3562_CRU_RESET_OFFSET(SRST_A_BUS_SPINLOCK, 23, 0),
184 RK3562_CRU_RESET_OFFSET(SRST_A_DCF, 23, 1),
185 RK3562_CRU_RESET_OFFSET(SRST_P_DCF, 23, 2),
186 RK3562_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 23, 3),
187 RK3562_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 23, 5),
188 RK3562_CRU_RESET_OFFSET(SRST_H_ICACHE, 23, 8),
189 RK3562_CRU_RESET_OFFSET(SRST_H_DCACHE, 23, 9),
190
191 /* SOFTRST_CON24 */
192 RK3562_CRU_RESET_OFFSET(SRST_P_TSADC, 24, 0),
193 RK3562_CRU_RESET_OFFSET(SRST_TSADC, 24, 1),
194 RK3562_CRU_RESET_OFFSET(SRST_TSADCPHY, 24, 2),
195 RK3562_CRU_RESET_OFFSET(SRST_P_DFT2APB, 24, 4),
196
197 /* SOFTRST_CON25 */
198 RK3562_CRU_RESET_OFFSET(SRST_A_GMAC, 25, 0),
199 RK3562_CRU_RESET_OFFSET(SRST_P_APB2ASB_VCCIO156, 25, 1),
200 RK3562_CRU_RESET_OFFSET(SRST_P_DSIPHY, 25, 5),
201 RK3562_CRU_RESET_OFFSET(SRST_P_DSITX, 25, 8),
202 RK3562_CRU_RESET_OFFSET(SRST_P_CPU_EMA_DET, 25, 9),
203 RK3562_CRU_RESET_OFFSET(SRST_P_HASH, 25, 10),
204 RK3562_CRU_RESET_OFFSET(SRST_P_TOPCRU, 25, 11),
205
206 /* SOFTRST_CON26 */
207 RK3562_CRU_RESET_OFFSET(SRST_P_ASB2APB_VCCIO156, 26, 0),
208 RK3562_CRU_RESET_OFFSET(SRST_P_IOC_VCCIO156, 26, 1),
209 RK3562_CRU_RESET_OFFSET(SRST_P_GPIO3_VCCIO156, 26, 2),
210 RK3562_CRU_RESET_OFFSET(SRST_P_GPIO4_VCCIO156, 26, 3),
211 RK3562_CRU_RESET_OFFSET(SRST_P_SARADC_VCCIO156, 26, 4),
212 RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156, 26, 5),
213 RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156_PHY, 26, 6),
214
215 /* SOFTRST_CON27 */
216 RK3562_CRU_RESET_OFFSET(SRST_A_MAC100, 27, 1),
217
218 /* PMU0_SOFTRST_CON00 */
219 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_CRU, 0, 0),
220 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PMU, 0, 1),
221 RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PMU, 0, 2),
222 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_HP_TIMER, 0, 3),
223 RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_HP_TIMER, 0, 4),
224 RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_32K_HP_TIMER, 0, 5),
225 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PVTM, 0, 6),
226 RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PVTM, 0, 7),
227 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_IOC_PMUIO, 0, 8),
228 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GPIO0, 0, 9),
229 RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_GPIO0, 0, 10),
230 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GRF, 0, 11),
231 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SGRF, 0, 12),
232
233 /* PMU0_SOFTRST_CON01 */
234 RK3562_PMU0CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 0),
235 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SCRKEYGEN, 1, 1),
236
237 /* PMU0_SOFTRST_CON02 */
238 RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_I2C0, 2, 8),
239 RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_I2C0, 2, 9),
240
241 /* PMU1_SOFTRST_CON00 */
242 RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_CRU, 0, 0),
243 RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_MEM, 0, 2),
244 RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 3),
245 RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 4),
246 RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_UART0, 0, 7),
247 RK3562_PMU1CRU_RESET_OFFSET(SRST_S_PMU1_UART0, 0, 10),
248
249 /* PMU1_SOFTRST_CON01 */
250 RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_SPI0, 1, 0),
251 RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_SPI0, 1, 1),
252 RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_PWM0, 1, 3),
253 RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_PWM0, 1, 4),
254
255 /* PMU1_SOFTRST_CON02 */
256 RK3562_PMU1CRU_RESET_OFFSET(SRST_F_PMU1_CM0_CORE, 2, 0),
257 RK3562_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 2, 2),
258 RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_WDTNS, 2, 3),
259 RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_WDTNS, 2, 4),
260 RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_MAILBOX, 2, 8),
261
262 /* DDR_SOFTRST_CON00 */
263 RK3562_DDRCRU_RESET_OFFSET(SRST_MSCH_BRG_BIU, 0, 4),
264 RK3562_DDRCRU_RESET_OFFSET(SRST_P_MSCH_BIU, 0, 5),
265 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 0, 6),
266 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
267 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DFICTL, 0, 9),
268 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DMA2DDR, 0, 10),
269
270 /* DDR_SOFTRST_CON01 */
271 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_MON, 1, 0),
272 RK3562_DDRCRU_RESET_OFFSET(SRST_TM_DDR_MON, 1, 1),
273 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 1, 2),
274 RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 3),
275 RK3562_DDRCRU_RESET_OFFSET(SRST_P_SUBDDR_CRU, 1, 4),
276
277 /* SUBDDR_SOFTRST_CON00 */
278 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 1),
279 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 4),
280 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DFICTL, 0, 5),
281 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_SCRAMBLE, 0, 6),
282 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_MON, 0, 7),
283 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_SPLIT, 0, 8),
284 RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DMA2DDR, 0, 9),
285
286 /* PERI_SOFTRST_CON01 */
287 RK3562_PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 1, 3),
288 RK3562_PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 1, 4),
289 RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 1, 5),
290 RK3562_PERICRU_RESET_OFFSET(SRST_P_PERICRU, 1, 6),
291
292 /* PERI_SOFTRST_CON02 */
293 RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI0_8CH, 2, 0),
294 RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI0_8CH, 2, 3),
295 RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI1_8CH, 2, 5),
296 RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI1_8CH, 2, 8),
297 RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI2_2CH, 2, 10),
298 RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI2_2CH, 2, 13),
299
300 /* PERI_SOFTRST_CON03 */
301 RK3562_PERICRU_RESET_OFFSET(SRST_H_DSM, 3, 1),
302 RK3562_PERICRU_RESET_OFFSET(SRST_DSM, 3, 2),
303 RK3562_PERICRU_RESET_OFFSET(SRST_H_PDM, 3, 4),
304 RK3562_PERICRU_RESET_OFFSET(SRST_M_PDM, 3, 5),
305 RK3562_PERICRU_RESET_OFFSET(SRST_H_SPDIF, 3, 8),
306 RK3562_PERICRU_RESET_OFFSET(SRST_M_SPDIF, 3, 11),
307
308 /* PERI_SOFTRST_CON04 */
309 RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC0, 4, 0),
310 RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC1, 4, 2),
311 RK3562_PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 8),
312 RK3562_PERICRU_RESET_OFFSET(SRST_A_EMMC, 4, 9),
313 RK3562_PERICRU_RESET_OFFSET(SRST_C_EMMC, 4, 10),
314 RK3562_PERICRU_RESET_OFFSET(SRST_B_EMMC, 4, 11),
315 RK3562_PERICRU_RESET_OFFSET(SRST_T_EMMC, 4, 12),
316 RK3562_PERICRU_RESET_OFFSET(SRST_S_SFC, 4, 13),
317 RK3562_PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14),
318
319 /* PERI_SOFTRST_CON05 */
320 RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 5, 0),
321 RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST_ARB, 5, 1),
322 RK3562_PERICRU_RESET_OFFSET(SRST_USB2HOST_UTMI, 5, 2),
323
324 /* PERI_SOFTRST_CON06 */
325 RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI1, 6, 0),
326 RK3562_PERICRU_RESET_OFFSET(SRST_SPI1, 6, 1),
327 RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI2, 6, 3),
328 RK3562_PERICRU_RESET_OFFSET(SRST_SPI2, 6, 4),
329
330 /* PERI_SOFTRST_CON07 */
331 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART1, 7, 0),
332 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART2, 7, 1),
333 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART3, 7, 2),
334 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART4, 7, 3),
335 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART5, 7, 4),
336 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART6, 7, 5),
337 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART7, 7, 6),
338 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART8, 7, 7),
339 RK3562_PERICRU_RESET_OFFSET(SRST_P_UART9, 7, 8),
340 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 11),
341 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART2, 7, 14),
342
343 /* PERI_SOFTRST_CON08 */
344 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART3, 8, 1),
345 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART4, 8, 4),
346 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART5, 8, 7),
347 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART6, 8, 10),
348 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART7, 8, 13),
349
350 /* PERI_SOFTRST_CON09 */
351 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART8, 9, 0),
352 RK3562_PERICRU_RESET_OFFSET(SRST_S_UART9, 9, 3),
353
354 /* PERI_SOFTRST_CON10 */
355 RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 10, 0),
356 RK3562_PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 10, 1),
357 RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 10, 3),
358 RK3562_PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 10, 4),
359 RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM3_PERI, 10, 6),
360 RK3562_PERICRU_RESET_OFFSET(SRST_PWM3_PERI, 10, 7),
361
362 /* PERI_SOFTRST_CON11 */
363 RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN0, 11, 0),
364 RK3562_PERICRU_RESET_OFFSET(SRST_CAN0, 11, 1),
365 RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN1, 11, 2),
366 RK3562_PERICRU_RESET_OFFSET(SRST_CAN1, 11, 3),
367
368 /* PERI_SOFTRST_CON12 */
369 RK3562_PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 12, 0),
370 RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 12, 1),
371 RK3562_PERICRU_RESET_OFFSET(SRST_P_CRYPTO, 12, 2),
372 RK3562_PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 12, 3),
373 RK3562_PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 12, 4),
374 RK3562_PERICRU_RESET_OFFSET(SRST_H_KLAD, 12, 5),
375 RK3562_PERICRU_RESET_OFFSET(SRST_P_KEY_READER, 12, 6),
376 RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_NS, 12, 7),
377 RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_S, 12, 8),
378 RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 12, 9),
379 RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 12, 10),
380 RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO_S, 12, 11),
381
382 /* PERI_SOFTRST_CON13 */
383 RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_WDT, 13, 0),
384 RK3562_PERICRU_RESET_OFFSET(SRST_T_PERI_WDT, 13, 1),
385 RK3562_PERICRU_RESET_OFFSET(SRST_A_SYSMEM, 13, 2),
386 RK3562_PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 13, 3),
387 RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 13, 4),
388 RK3562_PERICRU_RESET_OFFSET(SRST_A_DMAC, 13, 5),
389 RK3562_PERICRU_RESET_OFFSET(SRST_A_RKDMAC, 13, 6),
390
391 /* PERI_SOFTRST_CON14 */
392 RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_NS, 14, 0),
393 RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 14, 1),
394 RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_NS, 14, 2),
395 RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_S, 14, 3),
396 RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 14, 4),
397 RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_S, 14, 5),
398 RK3562_PERICRU_RESET_OFFSET(SRST_OTPC_ARB, 14, 6),
399 RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPPHY, 14, 7),
400 RK3562_PERICRU_RESET_OFFSET(SRST_OTP_NPOR, 14, 8),
401
402 /* PERI_SOFTRST_CON15 */
403 RK3562_PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 15, 0),
404 RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_POR, 15, 4),
405 RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_OTG, 15, 5),
406 RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_HOST, 15, 6),
407 RK3562_PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 15, 7),
408
409 /* PERI_SOFTRST_CON16 */
410 RK3562_PERICRU_RESET_OFFSET(SRST_P_SARADC, 16, 4),
411 RK3562_PERICRU_RESET_OFFSET(SRST_SARADC, 16, 5),
412 RK3562_PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 16, 6),
413 RK3562_PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO234, 16, 12),
414
415 /* PERI_SOFTRST_CON17 */
416 RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO1, 17, 0),
417 RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO2, 17, 1),
418 RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO1, 17, 2),
419 RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO2, 17, 3),
420 };
421
rk3562_rst_init(struct device_node * np,void __iomem * reg_base)422 void rk3562_rst_init(struct device_node *np, void __iomem *reg_base)
423 {
424 rockchip_register_softrst_lut(np,
425 rk3562_register_offset,
426 ARRAY_SIZE(rk3562_register_offset),
427 reg_base + RK3562_SOFTRST_CON(0),
428 ROCKCHIP_SOFTRST_HIWORD_MASK);
429 }
430