1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G3E CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 33 /* Internal Core Clocks */ 34 CLK_PLLCM33_DIV16, 35 CLK_PLLCLN_DIV2, 36 CLK_PLLCLN_DIV8, 37 CLK_PLLCLN_DIV16, 38 CLK_PLLCLN_DIV20, 39 CLK_PLLDTY_ACPU, 40 CLK_PLLDTY_ACPU_DIV2, 41 CLK_PLLDTY_ACPU_DIV4, 42 CLK_PLLDTY_DIV16, 43 CLK_PLLVDO_CRU0, 44 45 /* Module Clocks */ 46 MOD_CLK_BASE, 47 }; 48 49 static const struct clk_div_table dtable_1_8[] = { 50 {0, 1}, 51 {1, 2}, 52 {2, 4}, 53 {3, 8}, 54 {0, 0}, 55 }; 56 57 static const struct clk_div_table dtable_2_4[] = { 58 {0, 2}, 59 {1, 4}, 60 {0, 0}, 61 }; 62 63 static const struct clk_div_table dtable_2_64[] = { 64 {0, 2}, 65 {1, 4}, 66 {2, 8}, 67 {3, 16}, 68 {4, 64}, 69 {0, 0}, 70 }; 71 72 static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 73 /* External Clock Inputs */ 74 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 75 DEF_INPUT("rtxin", CLK_RTXIN), 76 DEF_INPUT("qextal", CLK_QEXTAL), 77 78 /* PLL Clocks */ 79 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 80 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 81 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 82 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), 83 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 84 85 /* Internal Core Clocks */ 86 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 87 88 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 89 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 90 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 91 DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), 92 93 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 94 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 95 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 96 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 97 98 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 99 100 /* Core Clocks */ 101 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 102 DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, 103 CDDIV1_DIVCTL0, dtable_1_8), 104 DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, 105 CDDIV1_DIVCTL1, dtable_1_8), 106 DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, 107 CDDIV1_DIVCTL2, dtable_1_8), 108 DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, 109 CDDIV1_DIVCTL3, dtable_1_8), 110 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 111 }; 112 113 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 114 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 115 BUS_MSTOP_NONE), 116 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 117 BUS_MSTOP(3, BIT(5))), 118 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 119 BUS_MSTOP(1, BIT(0))), 120 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 121 BUS_MSTOP(1, BIT(0))), 122 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 123 BUS_MSTOP(5, BIT(12))), 124 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 125 BUS_MSTOP(5, BIT(12))), 126 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 127 BUS_MSTOP(5, BIT(13))), 128 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 129 BUS_MSTOP(5, BIT(13))), 130 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 131 BUS_MSTOP(3, BIT(14))), 132 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 133 BUS_MSTOP(3, BIT(13))), 134 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 135 BUS_MSTOP(1, BIT(1))), 136 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 137 BUS_MSTOP(1, BIT(2))), 138 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 139 BUS_MSTOP(1, BIT(3))), 140 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 141 BUS_MSTOP(1, BIT(4))), 142 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 143 BUS_MSTOP(1, BIT(5))), 144 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 145 BUS_MSTOP(1, BIT(6))), 146 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 147 BUS_MSTOP(1, BIT(7))), 148 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 149 BUS_MSTOP(1, BIT(8))), 150 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28, 151 BUS_MSTOP(10, BIT(14))), 152 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29, 153 BUS_MSTOP(10, BIT(14))), 154 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30, 155 BUS_MSTOP(10, BIT(14))), 156 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 157 BUS_MSTOP(8, BIT(2))), 158 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 159 BUS_MSTOP(8, BIT(2))), 160 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 161 BUS_MSTOP(8, BIT(2))), 162 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 163 BUS_MSTOP(8, BIT(2))), 164 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 165 BUS_MSTOP(8, BIT(3))), 166 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 167 BUS_MSTOP(8, BIT(3))), 168 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 169 BUS_MSTOP(8, BIT(3))), 170 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 171 BUS_MSTOP(8, BIT(3))), 172 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 173 BUS_MSTOP(8, BIT(4))), 174 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 175 BUS_MSTOP(8, BIT(4))), 176 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 177 BUS_MSTOP(8, BIT(4))), 178 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 179 BUS_MSTOP(8, BIT(4))), 180 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 181 BUS_MSTOP(9, BIT(4))), 182 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 183 BUS_MSTOP(9, BIT(4))), 184 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 185 BUS_MSTOP(9, BIT(4))), 186 DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, 187 BUS_MSTOP(2, BIT(15))), 188 }; 189 190 static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 191 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 192 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 193 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 194 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 195 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 196 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 197 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 198 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 199 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 200 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 201 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 202 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 203 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 204 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 205 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 206 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 207 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 208 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */ 209 DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */ 210 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 211 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 212 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 213 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 214 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 215 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 216 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ 217 }; 218 219 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { 220 /* Core Clocks */ 221 .core_clks = r9a09g047_core_clks, 222 .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), 223 .last_dt_core_clk = LAST_DT_CORE_CLK, 224 .num_total_core_clks = MOD_CLK_BASE, 225 226 /* Module Clocks */ 227 .mod_clks = r9a09g047_mod_clks, 228 .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), 229 .num_hw_mod_clks = 28 * 16, 230 231 /* Resets */ 232 .resets = r9a09g047_resets, 233 .num_resets = ARRAY_SIZE(r9a09g047_resets), 234 235 .num_mstop_bits = 208, 236 }; 237