1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/delay.h>
10 #include <linux/platform_device.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/regmap.h>
16
17 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
18 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
19
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26
27 enum {
28 P_PXO,
29 P_PLL8,
30 P_PLL2,
31 P_PLL3,
32 P_PLL15,
33 P_HDMI_PLL,
34 P_DSI1_PLL_DSICLK,
35 P_DSI2_PLL_DSICLK,
36 P_DSI1_PLL_BYTECLK,
37 P_DSI2_PLL_BYTECLK,
38 P_LVDS_PLL,
39 };
40
41 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
42
43 static struct clk_pll pll2 = {
44 .l_reg = 0x320,
45 .m_reg = 0x324,
46 .n_reg = 0x328,
47 .config_reg = 0x32c,
48 .mode_reg = 0x31c,
49 .status_reg = 0x334,
50 .status_bit = 16,
51 .clkr.hw.init = &(struct clk_init_data){
52 .name = "pll2",
53 .parent_data = (const struct clk_parent_data[]){
54 { .fw_name = "pxo", .name = "pxo_board" },
55 },
56 .num_parents = 1,
57 .ops = &clk_pll_ops,
58 },
59 };
60
61 static struct clk_pll pll15 = {
62 .l_reg = 0x33c,
63 .m_reg = 0x340,
64 .n_reg = 0x344,
65 .config_reg = 0x348,
66 .mode_reg = 0x338,
67 .status_reg = 0x350,
68 .status_bit = 16,
69 .clkr.hw.init = &(struct clk_init_data){
70 .name = "pll15",
71 .parent_data = (const struct clk_parent_data[]){
72 { .fw_name = "pxo", .name = "pxo_board" },
73 },
74 .num_parents = 1,
75 .ops = &clk_pll_ops,
76 },
77 };
78
79 static const struct pll_config pll15_config = {
80 .l = 33,
81 .m = 1,
82 .n = 3,
83 .vco_val = 0x2 << 16,
84 .vco_mask = 0x3 << 16,
85 .pre_div_val = 0x0,
86 .pre_div_mask = BIT(19),
87 .post_div_val = 0x0,
88 .post_div_mask = 0x3 << 20,
89 .mn_ena_mask = BIT(22),
90 .main_output_mask = BIT(23),
91 };
92
93 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
94 { P_PXO, 0 },
95 { P_PLL8, 2 },
96 { P_PLL2, 1 }
97 };
98
99 static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = {
100 { .fw_name = "pxo", .name = "pxo_board" },
101 { .fw_name = "pll8_vote", .name = "pll8_vote" },
102 { .hw = &pll2.clkr.hw },
103 };
104
105 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
106 { P_PXO, 0 },
107 { P_PLL8, 2 },
108 { P_PLL2, 1 },
109 { P_PLL3, 3 }
110 };
111
112 static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = {
113 { .fw_name = "pxo", .name = "pxo_board" },
114 { .fw_name = "pll8_vote", .name = "pll8_vote" },
115 { .hw = &pll2.clkr.hw },
116 { .hw = &pll15.clkr.hw },
117 };
118
119 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
120 { P_PXO, 0 },
121 { P_PLL8, 2 },
122 { P_PLL2, 1 },
123 { P_PLL15, 3 }
124 };
125
126 static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = {
127 { .fw_name = "pxo", .name = "pxo_board" },
128 { .fw_name = "pll8_vote", .name = "pll8_vote" },
129 { .hw = &pll2.clkr.hw },
130 { .fw_name = "pll3", .name = "pll3" },
131 };
132
133 static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
134 { P_PXO, 0 },
135 { P_DSI2_PLL_DSICLK, 1 },
136 { P_DSI1_PLL_DSICLK, 3 },
137 };
138
139 static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = {
140 { .fw_name = "pxo", .name = "pxo_board" },
141 { .fw_name = "dsi2pll", .name = "dsi2pll" },
142 { .fw_name = "dsi1pll", .name = "dsi1pll" },
143 };
144
145 static const struct parent_map mmcc_pxo_dsi2_dsi1_lvds_map[] = {
146 { P_PXO, 0 },
147 { P_DSI2_PLL_DSICLK, 1 },
148 { P_LVDS_PLL, 2 },
149 { P_DSI1_PLL_DSICLK, 3 },
150 };
151
152 static const struct clk_parent_data mmcc_pxo_dsi2_dsi1_lvds[] = {
153 { .fw_name = "pxo", .name = "pxo_board" },
154 { .fw_name = "dsi2pll", .name = "dsi2pll" },
155 { .fw_name = "lvdspll", .name = "mpd4_lvds_pll" },
156 { .fw_name = "dsi1pll", .name = "dsi1pll" },
157 };
158
159 static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
160 { P_PXO, 0 },
161 { P_DSI1_PLL_BYTECLK, 1 },
162 { P_DSI2_PLL_BYTECLK, 2 },
163 };
164
165 static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
166 { .fw_name = "pxo", .name = "pxo_board" },
167 { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
168 { .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
169 };
170
171 static const struct freq_tbl clk_tbl_cam[] = {
172 { 6000000, P_PLL8, 4, 1, 16 },
173 { 8000000, P_PLL8, 4, 1, 12 },
174 { 12000000, P_PLL8, 4, 1, 8 },
175 { 16000000, P_PLL8, 4, 1, 6 },
176 { 19200000, P_PLL8, 4, 1, 5 },
177 { 24000000, P_PLL8, 4, 1, 4 },
178 { 32000000, P_PLL8, 4, 1, 3 },
179 { 48000000, P_PLL8, 4, 1, 2 },
180 { 64000000, P_PLL8, 3, 1, 2 },
181 { 96000000, P_PLL8, 4, 0, 0 },
182 { 128000000, P_PLL8, 3, 0, 0 },
183 { }
184 };
185
186 static struct clk_rcg camclk0_src = {
187 .ns_reg = 0x0148,
188 .md_reg = 0x0144,
189 .mn = {
190 .mnctr_en_bit = 5,
191 .mnctr_reset_bit = 8,
192 .reset_in_cc = true,
193 .mnctr_mode_shift = 6,
194 .n_val_shift = 24,
195 .m_val_shift = 8,
196 .width = 8,
197 },
198 .p = {
199 .pre_div_shift = 14,
200 .pre_div_width = 2,
201 },
202 .s = {
203 .src_sel_shift = 0,
204 .parent_map = mmcc_pxo_pll8_pll2_map,
205 },
206 .freq_tbl = clk_tbl_cam,
207 .clkr = {
208 .enable_reg = 0x0140,
209 .enable_mask = BIT(2),
210 .hw.init = &(struct clk_init_data){
211 .name = "camclk0_src",
212 .parent_data = mmcc_pxo_pll8_pll2,
213 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
214 .ops = &clk_rcg_ops,
215 },
216 },
217 };
218
219 static struct clk_branch camclk0_clk = {
220 .halt_reg = 0x01e8,
221 .halt_bit = 15,
222 .clkr = {
223 .enable_reg = 0x0140,
224 .enable_mask = BIT(0),
225 .hw.init = &(struct clk_init_data){
226 .name = "camclk0_clk",
227 .parent_hws = (const struct clk_hw*[]){
228 &camclk0_src.clkr.hw
229 },
230 .num_parents = 1,
231 .ops = &clk_branch_ops,
232 },
233 },
234
235 };
236
237 static struct clk_rcg camclk1_src = {
238 .ns_reg = 0x015c,
239 .md_reg = 0x0158,
240 .mn = {
241 .mnctr_en_bit = 5,
242 .mnctr_reset_bit = 8,
243 .reset_in_cc = true,
244 .mnctr_mode_shift = 6,
245 .n_val_shift = 24,
246 .m_val_shift = 8,
247 .width = 8,
248 },
249 .p = {
250 .pre_div_shift = 14,
251 .pre_div_width = 2,
252 },
253 .s = {
254 .src_sel_shift = 0,
255 .parent_map = mmcc_pxo_pll8_pll2_map,
256 },
257 .freq_tbl = clk_tbl_cam,
258 .clkr = {
259 .enable_reg = 0x0154,
260 .enable_mask = BIT(2),
261 .hw.init = &(struct clk_init_data){
262 .name = "camclk1_src",
263 .parent_data = mmcc_pxo_pll8_pll2,
264 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
265 .ops = &clk_rcg_ops,
266 },
267 },
268 };
269
270 static struct clk_branch camclk1_clk = {
271 .halt_reg = 0x01e8,
272 .halt_bit = 16,
273 .clkr = {
274 .enable_reg = 0x0154,
275 .enable_mask = BIT(0),
276 .hw.init = &(struct clk_init_data){
277 .name = "camclk1_clk",
278 .parent_hws = (const struct clk_hw*[]){
279 &camclk1_src.clkr.hw
280 },
281 .num_parents = 1,
282 .ops = &clk_branch_ops,
283 },
284 },
285
286 };
287
288 static struct clk_rcg camclk2_src = {
289 .ns_reg = 0x0228,
290 .md_reg = 0x0224,
291 .mn = {
292 .mnctr_en_bit = 5,
293 .mnctr_reset_bit = 8,
294 .reset_in_cc = true,
295 .mnctr_mode_shift = 6,
296 .n_val_shift = 24,
297 .m_val_shift = 8,
298 .width = 8,
299 },
300 .p = {
301 .pre_div_shift = 14,
302 .pre_div_width = 2,
303 },
304 .s = {
305 .src_sel_shift = 0,
306 .parent_map = mmcc_pxo_pll8_pll2_map,
307 },
308 .freq_tbl = clk_tbl_cam,
309 .clkr = {
310 .enable_reg = 0x0220,
311 .enable_mask = BIT(2),
312 .hw.init = &(struct clk_init_data){
313 .name = "camclk2_src",
314 .parent_data = mmcc_pxo_pll8_pll2,
315 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
316 .ops = &clk_rcg_ops,
317 },
318 },
319 };
320
321 static struct clk_branch camclk2_clk = {
322 .halt_reg = 0x01e8,
323 .halt_bit = 16,
324 .clkr = {
325 .enable_reg = 0x0220,
326 .enable_mask = BIT(0),
327 .hw.init = &(struct clk_init_data){
328 .name = "camclk2_clk",
329 .parent_hws = (const struct clk_hw*[]){
330 &camclk2_src.clkr.hw
331 },
332 .num_parents = 1,
333 .ops = &clk_branch_ops,
334 },
335 },
336
337 };
338
339 static const struct freq_tbl clk_tbl_csi[] = {
340 { 27000000, P_PXO, 1, 0, 0 },
341 { 85330000, P_PLL8, 1, 2, 9 },
342 { 177780000, P_PLL2, 1, 2, 9 },
343 { }
344 };
345
346 static struct clk_rcg csi0_src = {
347 .ns_reg = 0x0048,
348 .md_reg = 0x0044,
349 .mn = {
350 .mnctr_en_bit = 5,
351 .mnctr_reset_bit = 7,
352 .mnctr_mode_shift = 6,
353 .n_val_shift = 24,
354 .m_val_shift = 8,
355 .width = 8,
356 },
357 .p = {
358 .pre_div_shift = 14,
359 .pre_div_width = 2,
360 },
361 .s = {
362 .src_sel_shift = 0,
363 .parent_map = mmcc_pxo_pll8_pll2_map,
364 },
365 .freq_tbl = clk_tbl_csi,
366 .clkr = {
367 .enable_reg = 0x0040,
368 .enable_mask = BIT(2),
369 .hw.init = &(struct clk_init_data){
370 .name = "csi0_src",
371 .parent_data = mmcc_pxo_pll8_pll2,
372 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
373 .ops = &clk_rcg_ops,
374 },
375 },
376 };
377
378 static struct clk_branch csi0_clk = {
379 .halt_reg = 0x01cc,
380 .halt_bit = 13,
381 .clkr = {
382 .enable_reg = 0x0040,
383 .enable_mask = BIT(0),
384 .hw.init = &(struct clk_init_data){
385 .parent_hws = (const struct clk_hw*[]){
386 &csi0_src.clkr.hw
387 },
388 .num_parents = 1,
389 .name = "csi0_clk",
390 .ops = &clk_branch_ops,
391 .flags = CLK_SET_RATE_PARENT,
392 },
393 },
394 };
395
396 static struct clk_branch csi0_phy_clk = {
397 .halt_reg = 0x01e8,
398 .halt_bit = 9,
399 .clkr = {
400 .enable_reg = 0x0040,
401 .enable_mask = BIT(8),
402 .hw.init = &(struct clk_init_data){
403 .parent_hws = (const struct clk_hw*[]){
404 &csi0_src.clkr.hw
405 },
406 .num_parents = 1,
407 .name = "csi0_phy_clk",
408 .ops = &clk_branch_ops,
409 .flags = CLK_SET_RATE_PARENT,
410 },
411 },
412 };
413
414 static struct clk_rcg csi1_src = {
415 .ns_reg = 0x0010,
416 .md_reg = 0x0028,
417 .mn = {
418 .mnctr_en_bit = 5,
419 .mnctr_reset_bit = 7,
420 .mnctr_mode_shift = 6,
421 .n_val_shift = 24,
422 .m_val_shift = 8,
423 .width = 8,
424 },
425 .p = {
426 .pre_div_shift = 14,
427 .pre_div_width = 2,
428 },
429 .s = {
430 .src_sel_shift = 0,
431 .parent_map = mmcc_pxo_pll8_pll2_map,
432 },
433 .freq_tbl = clk_tbl_csi,
434 .clkr = {
435 .enable_reg = 0x0024,
436 .enable_mask = BIT(2),
437 .hw.init = &(struct clk_init_data){
438 .name = "csi1_src",
439 .parent_data = mmcc_pxo_pll8_pll2,
440 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
441 .ops = &clk_rcg_ops,
442 },
443 },
444 };
445
446 static struct clk_branch csi1_clk = {
447 .halt_reg = 0x01cc,
448 .halt_bit = 14,
449 .clkr = {
450 .enable_reg = 0x0024,
451 .enable_mask = BIT(0),
452 .hw.init = &(struct clk_init_data){
453 .parent_hws = (const struct clk_hw*[]){
454 &csi1_src.clkr.hw
455 },
456 .num_parents = 1,
457 .name = "csi1_clk",
458 .ops = &clk_branch_ops,
459 .flags = CLK_SET_RATE_PARENT,
460 },
461 },
462 };
463
464 static struct clk_branch csi1_phy_clk = {
465 .halt_reg = 0x01e8,
466 .halt_bit = 10,
467 .clkr = {
468 .enable_reg = 0x0024,
469 .enable_mask = BIT(8),
470 .hw.init = &(struct clk_init_data){
471 .parent_hws = (const struct clk_hw*[]){
472 &csi1_src.clkr.hw
473 },
474 .num_parents = 1,
475 .name = "csi1_phy_clk",
476 .ops = &clk_branch_ops,
477 .flags = CLK_SET_RATE_PARENT,
478 },
479 },
480 };
481
482 static struct clk_rcg csi2_src = {
483 .ns_reg = 0x0234,
484 .md_reg = 0x022c,
485 .mn = {
486 .mnctr_en_bit = 5,
487 .mnctr_reset_bit = 7,
488 .mnctr_mode_shift = 6,
489 .n_val_shift = 24,
490 .m_val_shift = 8,
491 .width = 8,
492 },
493 .p = {
494 .pre_div_shift = 14,
495 .pre_div_width = 2,
496 },
497 .s = {
498 .src_sel_shift = 0,
499 .parent_map = mmcc_pxo_pll8_pll2_map,
500 },
501 .freq_tbl = clk_tbl_csi,
502 .clkr = {
503 .enable_reg = 0x022c,
504 .enable_mask = BIT(2),
505 .hw.init = &(struct clk_init_data){
506 .name = "csi2_src",
507 .parent_data = mmcc_pxo_pll8_pll2,
508 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
509 .ops = &clk_rcg_ops,
510 },
511 },
512 };
513
514 static struct clk_branch csi2_clk = {
515 .halt_reg = 0x01cc,
516 .halt_bit = 29,
517 .clkr = {
518 .enable_reg = 0x022c,
519 .enable_mask = BIT(0),
520 .hw.init = &(struct clk_init_data){
521 .parent_hws = (const struct clk_hw*[]){
522 &csi2_src.clkr.hw
523 },
524 .num_parents = 1,
525 .name = "csi2_clk",
526 .ops = &clk_branch_ops,
527 .flags = CLK_SET_RATE_PARENT,
528 },
529 },
530 };
531
532 static struct clk_branch csi2_phy_clk = {
533 .halt_reg = 0x01e8,
534 .halt_bit = 29,
535 .clkr = {
536 .enable_reg = 0x022c,
537 .enable_mask = BIT(8),
538 .hw.init = &(struct clk_init_data){
539 .parent_hws = (const struct clk_hw*[]){
540 &csi2_src.clkr.hw
541 },
542 .num_parents = 1,
543 .name = "csi2_phy_clk",
544 .ops = &clk_branch_ops,
545 .flags = CLK_SET_RATE_PARENT,
546 },
547 },
548 };
549
550 struct clk_pix_rdi {
551 u32 s_reg;
552 u32 s_mask;
553 u32 s2_reg;
554 u32 s2_mask;
555 struct clk_regmap clkr;
556 };
557
558 #define to_clk_pix_rdi(_hw) \
559 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
560
pix_rdi_set_parent(struct clk_hw * hw,u8 index)561 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
562 {
563 int i;
564 int ret = 0;
565 u32 val;
566 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
567 int num_parents = clk_hw_get_num_parents(hw);
568
569 /*
570 * These clocks select three inputs via two muxes. One mux selects
571 * between csi0 and csi1 and the second mux selects between that mux's
572 * output and csi2. The source and destination selections for each
573 * mux must be clocking for the switch to succeed so just turn on
574 * all three sources because it's easier than figuring out what source
575 * needs to be on at what time.
576 */
577 for (i = 0; i < num_parents; i++) {
578 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
579 ret = clk_prepare_enable(p->clk);
580 if (ret)
581 goto err;
582 }
583
584 if (index == 2)
585 val = rdi->s2_mask;
586 else
587 val = 0;
588 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
589 /*
590 * Wait at least 6 cycles of slowest clock
591 * for the glitch-free MUX to fully switch sources.
592 */
593 udelay(1);
594
595 if (index == 1)
596 val = rdi->s_mask;
597 else
598 val = 0;
599 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
600 /*
601 * Wait at least 6 cycles of slowest clock
602 * for the glitch-free MUX to fully switch sources.
603 */
604 udelay(1);
605
606 err:
607 for (i--; i >= 0; i--) {
608 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
609 clk_disable_unprepare(p->clk);
610 }
611
612 return ret;
613 }
614
pix_rdi_get_parent(struct clk_hw * hw)615 static u8 pix_rdi_get_parent(struct clk_hw *hw)
616 {
617 u32 val;
618 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
619
620
621 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
622 if (val & rdi->s2_mask)
623 return 2;
624
625 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
626 if (val & rdi->s_mask)
627 return 1;
628
629 return 0;
630 }
631
632 static const struct clk_ops clk_ops_pix_rdi = {
633 .enable = clk_enable_regmap,
634 .disable = clk_disable_regmap,
635 .set_parent = pix_rdi_set_parent,
636 .get_parent = pix_rdi_get_parent,
637 .determine_rate = __clk_mux_determine_rate,
638 };
639
640 static const struct clk_hw *pix_rdi_parents[] = {
641 &csi0_clk.clkr.hw,
642 &csi1_clk.clkr.hw,
643 &csi2_clk.clkr.hw,
644 };
645
646 static struct clk_pix_rdi csi_pix_clk = {
647 .s_reg = 0x0058,
648 .s_mask = BIT(25),
649 .s2_reg = 0x0238,
650 .s2_mask = BIT(13),
651 .clkr = {
652 .enable_reg = 0x0058,
653 .enable_mask = BIT(26),
654 .hw.init = &(struct clk_init_data){
655 .name = "csi_pix_clk",
656 .parent_hws = pix_rdi_parents,
657 .num_parents = ARRAY_SIZE(pix_rdi_parents),
658 .ops = &clk_ops_pix_rdi,
659 },
660 },
661 };
662
663 static struct clk_pix_rdi csi_pix1_clk = {
664 .s_reg = 0x0238,
665 .s_mask = BIT(8),
666 .s2_reg = 0x0238,
667 .s2_mask = BIT(9),
668 .clkr = {
669 .enable_reg = 0x0238,
670 .enable_mask = BIT(10),
671 .hw.init = &(struct clk_init_data){
672 .name = "csi_pix1_clk",
673 .parent_hws = pix_rdi_parents,
674 .num_parents = ARRAY_SIZE(pix_rdi_parents),
675 .ops = &clk_ops_pix_rdi,
676 },
677 },
678 };
679
680 static struct clk_pix_rdi csi_rdi_clk = {
681 .s_reg = 0x0058,
682 .s_mask = BIT(12),
683 .s2_reg = 0x0238,
684 .s2_mask = BIT(12),
685 .clkr = {
686 .enable_reg = 0x0058,
687 .enable_mask = BIT(13),
688 .hw.init = &(struct clk_init_data){
689 .name = "csi_rdi_clk",
690 .parent_hws = pix_rdi_parents,
691 .num_parents = ARRAY_SIZE(pix_rdi_parents),
692 .ops = &clk_ops_pix_rdi,
693 },
694 },
695 };
696
697 static struct clk_pix_rdi csi_rdi1_clk = {
698 .s_reg = 0x0238,
699 .s_mask = BIT(0),
700 .s2_reg = 0x0238,
701 .s2_mask = BIT(1),
702 .clkr = {
703 .enable_reg = 0x0238,
704 .enable_mask = BIT(2),
705 .hw.init = &(struct clk_init_data){
706 .name = "csi_rdi1_clk",
707 .parent_hws = pix_rdi_parents,
708 .num_parents = ARRAY_SIZE(pix_rdi_parents),
709 .ops = &clk_ops_pix_rdi,
710 },
711 },
712 };
713
714 static struct clk_pix_rdi csi_rdi2_clk = {
715 .s_reg = 0x0238,
716 .s_mask = BIT(4),
717 .s2_reg = 0x0238,
718 .s2_mask = BIT(5),
719 .clkr = {
720 .enable_reg = 0x0238,
721 .enable_mask = BIT(6),
722 .hw.init = &(struct clk_init_data){
723 .name = "csi_rdi2_clk",
724 .parent_hws = pix_rdi_parents,
725 .num_parents = ARRAY_SIZE(pix_rdi_parents),
726 .ops = &clk_ops_pix_rdi,
727 },
728 },
729 };
730
731 static const struct freq_tbl clk_tbl_csiphytimer[] = {
732 { 85330000, P_PLL8, 1, 2, 9 },
733 { 177780000, P_PLL2, 1, 2, 9 },
734 { }
735 };
736
737 static struct clk_rcg csiphytimer_src = {
738 .ns_reg = 0x0168,
739 .md_reg = 0x0164,
740 .mn = {
741 .mnctr_en_bit = 5,
742 .mnctr_reset_bit = 8,
743 .reset_in_cc = true,
744 .mnctr_mode_shift = 6,
745 .n_val_shift = 24,
746 .m_val_shift = 8,
747 .width = 8,
748 },
749 .p = {
750 .pre_div_shift = 14,
751 .pre_div_width = 2,
752 },
753 .s = {
754 .src_sel_shift = 0,
755 .parent_map = mmcc_pxo_pll8_pll2_map,
756 },
757 .freq_tbl = clk_tbl_csiphytimer,
758 .clkr = {
759 .enable_reg = 0x0160,
760 .enable_mask = BIT(2),
761 .hw.init = &(struct clk_init_data){
762 .name = "csiphytimer_src",
763 .parent_data = mmcc_pxo_pll8_pll2,
764 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
765 .ops = &clk_rcg_ops,
766 },
767 },
768 };
769
770 static struct clk_branch csiphy0_timer_clk = {
771 .halt_reg = 0x01e8,
772 .halt_bit = 17,
773 .clkr = {
774 .enable_reg = 0x0160,
775 .enable_mask = BIT(0),
776 .hw.init = &(struct clk_init_data){
777 .parent_hws = (const struct clk_hw*[]){
778 &csiphytimer_src.clkr.hw,
779 },
780 .num_parents = 1,
781 .name = "csiphy0_timer_clk",
782 .ops = &clk_branch_ops,
783 .flags = CLK_SET_RATE_PARENT,
784 },
785 },
786 };
787
788 static struct clk_branch csiphy1_timer_clk = {
789 .halt_reg = 0x01e8,
790 .halt_bit = 18,
791 .clkr = {
792 .enable_reg = 0x0160,
793 .enable_mask = BIT(9),
794 .hw.init = &(struct clk_init_data){
795 .parent_hws = (const struct clk_hw*[]){
796 &csiphytimer_src.clkr.hw,
797 },
798 .num_parents = 1,
799 .name = "csiphy1_timer_clk",
800 .ops = &clk_branch_ops,
801 .flags = CLK_SET_RATE_PARENT,
802 },
803 },
804 };
805
806 static struct clk_branch csiphy2_timer_clk = {
807 .halt_reg = 0x01e8,
808 .halt_bit = 30,
809 .clkr = {
810 .enable_reg = 0x0160,
811 .enable_mask = BIT(11),
812 .hw.init = &(struct clk_init_data){
813 .parent_hws = (const struct clk_hw*[]){
814 &csiphytimer_src.clkr.hw,
815 },
816 .num_parents = 1,
817 .name = "csiphy2_timer_clk",
818 .ops = &clk_branch_ops,
819 .flags = CLK_SET_RATE_PARENT,
820 },
821 },
822 };
823
824 static const struct freq_tbl clk_tbl_gfx2d[] = {
825 F_MN( 27000000, P_PXO, 1, 0),
826 F_MN( 48000000, P_PLL8, 1, 8),
827 F_MN( 54857000, P_PLL8, 1, 7),
828 F_MN( 64000000, P_PLL8, 1, 6),
829 F_MN( 76800000, P_PLL8, 1, 5),
830 F_MN( 96000000, P_PLL8, 1, 4),
831 F_MN(128000000, P_PLL8, 1, 3),
832 F_MN(145455000, P_PLL2, 2, 11),
833 F_MN(160000000, P_PLL2, 1, 5),
834 F_MN(177778000, P_PLL2, 2, 9),
835 F_MN(200000000, P_PLL2, 1, 4),
836 F_MN(228571000, P_PLL2, 2, 7),
837 { }
838 };
839
840 static struct clk_dyn_rcg gfx2d0_src = {
841 .ns_reg[0] = 0x0070,
842 .ns_reg[1] = 0x0070,
843 .md_reg[0] = 0x0064,
844 .md_reg[1] = 0x0068,
845 .bank_reg = 0x0060,
846 .mn[0] = {
847 .mnctr_en_bit = 8,
848 .mnctr_reset_bit = 25,
849 .mnctr_mode_shift = 9,
850 .n_val_shift = 20,
851 .m_val_shift = 4,
852 .width = 4,
853 },
854 .mn[1] = {
855 .mnctr_en_bit = 5,
856 .mnctr_reset_bit = 24,
857 .mnctr_mode_shift = 6,
858 .n_val_shift = 16,
859 .m_val_shift = 4,
860 .width = 4,
861 },
862 .s[0] = {
863 .src_sel_shift = 3,
864 .parent_map = mmcc_pxo_pll8_pll2_map,
865 },
866 .s[1] = {
867 .src_sel_shift = 0,
868 .parent_map = mmcc_pxo_pll8_pll2_map,
869 },
870 .mux_sel_bit = 11,
871 .freq_tbl = clk_tbl_gfx2d,
872 .clkr = {
873 .enable_reg = 0x0060,
874 .enable_mask = BIT(2),
875 .hw.init = &(struct clk_init_data){
876 .name = "gfx2d0_src",
877 .parent_data = mmcc_pxo_pll8_pll2,
878 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
879 .ops = &clk_dyn_rcg_ops,
880 },
881 },
882 };
883
884 static struct clk_branch gfx2d0_clk = {
885 .halt_reg = 0x01c8,
886 .halt_bit = 9,
887 .clkr = {
888 .enable_reg = 0x0060,
889 .enable_mask = BIT(0),
890 .hw.init = &(struct clk_init_data){
891 .name = "gfx2d0_clk",
892 .parent_hws = (const struct clk_hw*[]){
893 &gfx2d0_src.clkr.hw
894 },
895 .num_parents = 1,
896 .ops = &clk_branch_ops,
897 .flags = CLK_SET_RATE_PARENT,
898 },
899 },
900 };
901
902 static struct clk_dyn_rcg gfx2d1_src = {
903 .ns_reg[0] = 0x007c,
904 .ns_reg[1] = 0x007c,
905 .md_reg[0] = 0x0078,
906 .md_reg[1] = 0x006c,
907 .bank_reg = 0x0074,
908 .mn[0] = {
909 .mnctr_en_bit = 8,
910 .mnctr_reset_bit = 25,
911 .mnctr_mode_shift = 9,
912 .n_val_shift = 20,
913 .m_val_shift = 4,
914 .width = 4,
915 },
916 .mn[1] = {
917 .mnctr_en_bit = 5,
918 .mnctr_reset_bit = 24,
919 .mnctr_mode_shift = 6,
920 .n_val_shift = 16,
921 .m_val_shift = 4,
922 .width = 4,
923 },
924 .s[0] = {
925 .src_sel_shift = 3,
926 .parent_map = mmcc_pxo_pll8_pll2_map,
927 },
928 .s[1] = {
929 .src_sel_shift = 0,
930 .parent_map = mmcc_pxo_pll8_pll2_map,
931 },
932 .mux_sel_bit = 11,
933 .freq_tbl = clk_tbl_gfx2d,
934 .clkr = {
935 .enable_reg = 0x0074,
936 .enable_mask = BIT(2),
937 .hw.init = &(struct clk_init_data){
938 .name = "gfx2d1_src",
939 .parent_data = mmcc_pxo_pll8_pll2,
940 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
941 .ops = &clk_dyn_rcg_ops,
942 },
943 },
944 };
945
946 static struct clk_branch gfx2d1_clk = {
947 .halt_reg = 0x01c8,
948 .halt_bit = 14,
949 .clkr = {
950 .enable_reg = 0x0074,
951 .enable_mask = BIT(0),
952 .hw.init = &(struct clk_init_data){
953 .name = "gfx2d1_clk",
954 .parent_hws = (const struct clk_hw*[]){
955 &gfx2d1_src.clkr.hw
956 },
957 .num_parents = 1,
958 .ops = &clk_branch_ops,
959 .flags = CLK_SET_RATE_PARENT,
960 },
961 },
962 };
963
964 static const struct freq_tbl clk_tbl_gfx3d[] = {
965 F_MN( 27000000, P_PXO, 1, 0),
966 F_MN( 48000000, P_PLL8, 1, 8),
967 F_MN( 54857000, P_PLL8, 1, 7),
968 F_MN( 64000000, P_PLL8, 1, 6),
969 F_MN( 76800000, P_PLL8, 1, 5),
970 F_MN( 96000000, P_PLL8, 1, 4),
971 F_MN(128000000, P_PLL8, 1, 3),
972 F_MN(145455000, P_PLL2, 2, 11),
973 F_MN(160000000, P_PLL2, 1, 5),
974 F_MN(177778000, P_PLL2, 2, 9),
975 F_MN(200000000, P_PLL2, 1, 4),
976 F_MN(228571000, P_PLL2, 2, 7),
977 F_MN(266667000, P_PLL2, 1, 3),
978 F_MN(300000000, P_PLL3, 1, 4),
979 F_MN(320000000, P_PLL2, 2, 5),
980 F_MN(400000000, P_PLL2, 1, 2),
981 { }
982 };
983
984 static const struct freq_tbl clk_tbl_gfx3d_8064[] = {
985 F_MN( 27000000, P_PXO, 0, 0),
986 F_MN( 48000000, P_PLL8, 1, 8),
987 F_MN( 54857000, P_PLL8, 1, 7),
988 F_MN( 64000000, P_PLL8, 1, 6),
989 F_MN( 76800000, P_PLL8, 1, 5),
990 F_MN( 96000000, P_PLL8, 1, 4),
991 F_MN(128000000, P_PLL8, 1, 3),
992 F_MN(145455000, P_PLL2, 2, 11),
993 F_MN(160000000, P_PLL2, 1, 5),
994 F_MN(177778000, P_PLL2, 2, 9),
995 F_MN(192000000, P_PLL8, 1, 2),
996 F_MN(200000000, P_PLL2, 1, 4),
997 F_MN(228571000, P_PLL2, 2, 7),
998 F_MN(266667000, P_PLL2, 1, 3),
999 F_MN(320000000, P_PLL2, 2, 5),
1000 F_MN(400000000, P_PLL2, 1, 2),
1001 F_MN(450000000, P_PLL15, 1, 2),
1002 { }
1003 };
1004
1005 static struct clk_dyn_rcg gfx3d_src = {
1006 .ns_reg[0] = 0x008c,
1007 .ns_reg[1] = 0x008c,
1008 .md_reg[0] = 0x0084,
1009 .md_reg[1] = 0x0088,
1010 .bank_reg = 0x0080,
1011 .mn[0] = {
1012 .mnctr_en_bit = 8,
1013 .mnctr_reset_bit = 25,
1014 .mnctr_mode_shift = 9,
1015 .n_val_shift = 18,
1016 .m_val_shift = 4,
1017 .width = 4,
1018 },
1019 .mn[1] = {
1020 .mnctr_en_bit = 5,
1021 .mnctr_reset_bit = 24,
1022 .mnctr_mode_shift = 6,
1023 .n_val_shift = 14,
1024 .m_val_shift = 4,
1025 .width = 4,
1026 },
1027 .s[0] = {
1028 .src_sel_shift = 3,
1029 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
1030 },
1031 .s[1] = {
1032 .src_sel_shift = 0,
1033 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
1034 },
1035 .mux_sel_bit = 11,
1036 .freq_tbl = clk_tbl_gfx3d,
1037 .clkr = {
1038 .enable_reg = 0x0080,
1039 .enable_mask = BIT(2),
1040 .hw.init = &(struct clk_init_data){
1041 .name = "gfx3d_src",
1042 .parent_data = mmcc_pxo_pll8_pll2_pll3,
1043 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3),
1044 .ops = &clk_dyn_rcg_ops,
1045 },
1046 },
1047 };
1048
1049 static const struct clk_init_data gfx3d_8064_init = {
1050 .name = "gfx3d_src",
1051 .parent_data = mmcc_pxo_pll8_pll2_pll15,
1052 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15),
1053 .ops = &clk_dyn_rcg_ops,
1054 };
1055
1056 static struct clk_branch gfx3d_clk = {
1057 .halt_reg = 0x01c8,
1058 .halt_bit = 4,
1059 .clkr = {
1060 .enable_reg = 0x0080,
1061 .enable_mask = BIT(0),
1062 .hw.init = &(struct clk_init_data){
1063 .name = "gfx3d_clk",
1064 .parent_hws = (const struct clk_hw*[]){
1065 &gfx3d_src.clkr.hw
1066 },
1067 .num_parents = 1,
1068 .ops = &clk_branch_ops,
1069 .flags = CLK_SET_RATE_PARENT,
1070 },
1071 },
1072 };
1073
1074 static const struct freq_tbl clk_tbl_vcap[] = {
1075 F_MN( 27000000, P_PXO, 0, 0),
1076 F_MN( 54860000, P_PLL8, 1, 7),
1077 F_MN( 64000000, P_PLL8, 1, 6),
1078 F_MN( 76800000, P_PLL8, 1, 5),
1079 F_MN(128000000, P_PLL8, 1, 3),
1080 F_MN(160000000, P_PLL2, 1, 5),
1081 F_MN(200000000, P_PLL2, 1, 4),
1082 { }
1083 };
1084
1085 static struct clk_dyn_rcg vcap_src = {
1086 .ns_reg[0] = 0x021c,
1087 .ns_reg[1] = 0x021c,
1088 .md_reg[0] = 0x01ec,
1089 .md_reg[1] = 0x0218,
1090 .bank_reg = 0x0178,
1091 .mn[0] = {
1092 .mnctr_en_bit = 8,
1093 .mnctr_reset_bit = 23,
1094 .mnctr_mode_shift = 9,
1095 .n_val_shift = 18,
1096 .m_val_shift = 4,
1097 .width = 4,
1098 },
1099 .mn[1] = {
1100 .mnctr_en_bit = 5,
1101 .mnctr_reset_bit = 22,
1102 .mnctr_mode_shift = 6,
1103 .n_val_shift = 14,
1104 .m_val_shift = 4,
1105 .width = 4,
1106 },
1107 .s[0] = {
1108 .src_sel_shift = 3,
1109 .parent_map = mmcc_pxo_pll8_pll2_map,
1110 },
1111 .s[1] = {
1112 .src_sel_shift = 0,
1113 .parent_map = mmcc_pxo_pll8_pll2_map,
1114 },
1115 .mux_sel_bit = 11,
1116 .freq_tbl = clk_tbl_vcap,
1117 .clkr = {
1118 .enable_reg = 0x0178,
1119 .enable_mask = BIT(2),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "vcap_src",
1122 .parent_data = mmcc_pxo_pll8_pll2,
1123 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1124 .ops = &clk_dyn_rcg_ops,
1125 },
1126 },
1127 };
1128
1129 static struct clk_branch vcap_clk = {
1130 .halt_reg = 0x0240,
1131 .halt_bit = 15,
1132 .clkr = {
1133 .enable_reg = 0x0178,
1134 .enable_mask = BIT(0),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "vcap_clk",
1137 .parent_hws = (const struct clk_hw*[]){
1138 &vcap_src.clkr.hw
1139 },
1140 .num_parents = 1,
1141 .ops = &clk_branch_ops,
1142 .flags = CLK_SET_RATE_PARENT,
1143 },
1144 },
1145 };
1146
1147 static struct clk_branch vcap_npl_clk = {
1148 .halt_reg = 0x0240,
1149 .halt_bit = 25,
1150 .clkr = {
1151 .enable_reg = 0x0178,
1152 .enable_mask = BIT(13),
1153 .hw.init = &(struct clk_init_data){
1154 .name = "vcap_npl_clk",
1155 .parent_hws = (const struct clk_hw*[]){
1156 &vcap_src.clkr.hw
1157 },
1158 .num_parents = 1,
1159 .ops = &clk_branch_ops,
1160 .flags = CLK_SET_RATE_PARENT,
1161 },
1162 },
1163 };
1164
1165 static const struct freq_tbl clk_tbl_ijpeg[] = {
1166 { 27000000, P_PXO, 1, 0, 0 },
1167 { 36570000, P_PLL8, 1, 2, 21 },
1168 { 54860000, P_PLL8, 7, 0, 0 },
1169 { 96000000, P_PLL8, 4, 0, 0 },
1170 { 109710000, P_PLL8, 1, 2, 7 },
1171 { 128000000, P_PLL8, 3, 0, 0 },
1172 { 153600000, P_PLL8, 1, 2, 5 },
1173 { 200000000, P_PLL2, 4, 0, 0 },
1174 { 228571000, P_PLL2, 1, 2, 7 },
1175 { 266667000, P_PLL2, 1, 1, 3 },
1176 { 320000000, P_PLL2, 1, 2, 5 },
1177 { }
1178 };
1179
1180 static struct clk_rcg ijpeg_src = {
1181 .ns_reg = 0x00a0,
1182 .md_reg = 0x009c,
1183 .mn = {
1184 .mnctr_en_bit = 5,
1185 .mnctr_reset_bit = 7,
1186 .mnctr_mode_shift = 6,
1187 .n_val_shift = 16,
1188 .m_val_shift = 8,
1189 .width = 8,
1190 },
1191 .p = {
1192 .pre_div_shift = 12,
1193 .pre_div_width = 2,
1194 },
1195 .s = {
1196 .src_sel_shift = 0,
1197 .parent_map = mmcc_pxo_pll8_pll2_map,
1198 },
1199 .freq_tbl = clk_tbl_ijpeg,
1200 .clkr = {
1201 .enable_reg = 0x0098,
1202 .enable_mask = BIT(2),
1203 .hw.init = &(struct clk_init_data){
1204 .name = "ijpeg_src",
1205 .parent_data = mmcc_pxo_pll8_pll2,
1206 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1207 .ops = &clk_rcg_ops,
1208 },
1209 },
1210 };
1211
1212 static struct clk_branch ijpeg_clk = {
1213 .halt_reg = 0x01c8,
1214 .halt_bit = 24,
1215 .clkr = {
1216 .enable_reg = 0x0098,
1217 .enable_mask = BIT(0),
1218 .hw.init = &(struct clk_init_data){
1219 .name = "ijpeg_clk",
1220 .parent_hws = (const struct clk_hw*[]){
1221 &ijpeg_src.clkr.hw
1222 },
1223 .num_parents = 1,
1224 .ops = &clk_branch_ops,
1225 .flags = CLK_SET_RATE_PARENT,
1226 },
1227 },
1228 };
1229
1230 static const struct freq_tbl clk_tbl_jpegd[] = {
1231 { 64000000, P_PLL8, 6 },
1232 { 76800000, P_PLL8, 5 },
1233 { 96000000, P_PLL8, 4 },
1234 { 160000000, P_PLL2, 5 },
1235 { 200000000, P_PLL2, 4 },
1236 { }
1237 };
1238
1239 static struct clk_rcg jpegd_src = {
1240 .ns_reg = 0x00ac,
1241 .p = {
1242 .pre_div_shift = 12,
1243 .pre_div_width = 4,
1244 },
1245 .s = {
1246 .src_sel_shift = 0,
1247 .parent_map = mmcc_pxo_pll8_pll2_map,
1248 },
1249 .freq_tbl = clk_tbl_jpegd,
1250 .clkr = {
1251 .enable_reg = 0x00a4,
1252 .enable_mask = BIT(2),
1253 .hw.init = &(struct clk_init_data){
1254 .name = "jpegd_src",
1255 .parent_data = mmcc_pxo_pll8_pll2,
1256 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1257 .ops = &clk_rcg_ops,
1258 },
1259 },
1260 };
1261
1262 static struct clk_branch jpegd_clk = {
1263 .halt_reg = 0x01c8,
1264 .halt_bit = 19,
1265 .clkr = {
1266 .enable_reg = 0x00a4,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data){
1269 .name = "jpegd_clk",
1270 .parent_hws = (const struct clk_hw*[]){
1271 &jpegd_src.clkr.hw
1272 },
1273 .num_parents = 1,
1274 .ops = &clk_branch_ops,
1275 .flags = CLK_SET_RATE_PARENT,
1276 },
1277 },
1278 };
1279
1280 static const struct freq_tbl clk_tbl_mdp[] = {
1281 { 9600000, P_PLL8, 1, 1, 40 },
1282 { 13710000, P_PLL8, 1, 1, 28 },
1283 { 27000000, P_PXO, 1, 0, 0 },
1284 { 29540000, P_PLL8, 1, 1, 13 },
1285 { 34910000, P_PLL8, 1, 1, 11 },
1286 { 38400000, P_PLL8, 1, 1, 10 },
1287 { 59080000, P_PLL8, 1, 2, 13 },
1288 { 76800000, P_PLL8, 1, 1, 5 },
1289 { 85330000, P_PLL8, 1, 2, 9 },
1290 { 96000000, P_PLL8, 1, 1, 4 },
1291 { 128000000, P_PLL8, 1, 1, 3 },
1292 { 160000000, P_PLL2, 1, 1, 5 },
1293 { 177780000, P_PLL2, 1, 2, 9 },
1294 { 200000000, P_PLL2, 1, 1, 4 },
1295 { 228571000, P_PLL2, 1, 2, 7 },
1296 { 266667000, P_PLL2, 1, 1, 3 },
1297 { }
1298 };
1299
1300 static struct clk_dyn_rcg mdp_src = {
1301 .ns_reg[0] = 0x00d0,
1302 .ns_reg[1] = 0x00d0,
1303 .md_reg[0] = 0x00c4,
1304 .md_reg[1] = 0x00c8,
1305 .bank_reg = 0x00c0,
1306 .mn[0] = {
1307 .mnctr_en_bit = 8,
1308 .mnctr_reset_bit = 31,
1309 .mnctr_mode_shift = 9,
1310 .n_val_shift = 22,
1311 .m_val_shift = 8,
1312 .width = 8,
1313 },
1314 .mn[1] = {
1315 .mnctr_en_bit = 5,
1316 .mnctr_reset_bit = 30,
1317 .mnctr_mode_shift = 6,
1318 .n_val_shift = 14,
1319 .m_val_shift = 8,
1320 .width = 8,
1321 },
1322 .s[0] = {
1323 .src_sel_shift = 3,
1324 .parent_map = mmcc_pxo_pll8_pll2_map,
1325 },
1326 .s[1] = {
1327 .src_sel_shift = 0,
1328 .parent_map = mmcc_pxo_pll8_pll2_map,
1329 },
1330 .mux_sel_bit = 11,
1331 .freq_tbl = clk_tbl_mdp,
1332 .clkr = {
1333 .enable_reg = 0x00c0,
1334 .enable_mask = BIT(2),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "mdp_src",
1337 .parent_data = mmcc_pxo_pll8_pll2,
1338 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1339 .ops = &clk_dyn_rcg_ops,
1340 },
1341 },
1342 };
1343
1344 static struct clk_branch mdp_clk = {
1345 .halt_reg = 0x01d0,
1346 .halt_bit = 10,
1347 .clkr = {
1348 .enable_reg = 0x00c0,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "mdp_clk",
1352 .parent_hws = (const struct clk_hw*[]){
1353 &mdp_src.clkr.hw
1354 },
1355 .num_parents = 1,
1356 .ops = &clk_branch_ops,
1357 .flags = CLK_SET_RATE_PARENT,
1358 },
1359 },
1360 };
1361
1362 static struct clk_branch mdp_lut_clk = {
1363 .halt_reg = 0x01e8,
1364 .halt_bit = 13,
1365 .clkr = {
1366 .enable_reg = 0x016c,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data){
1369 .parent_hws = (const struct clk_hw*[]){
1370 &mdp_src.clkr.hw
1371 },
1372 .num_parents = 1,
1373 .name = "mdp_lut_clk",
1374 .ops = &clk_branch_ops,
1375 .flags = CLK_SET_RATE_PARENT,
1376 },
1377 },
1378 };
1379
1380 static struct clk_branch mdp_vsync_clk = {
1381 .halt_reg = 0x01cc,
1382 .halt_bit = 22,
1383 .clkr = {
1384 .enable_reg = 0x0058,
1385 .enable_mask = BIT(6),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "mdp_vsync_clk",
1388 .parent_data = (const struct clk_parent_data[]){
1389 { .fw_name = "pxo", .name = "pxo_board" },
1390 },
1391 .num_parents = 1,
1392 .ops = &clk_branch_ops
1393 },
1394 },
1395 };
1396
1397 static const struct freq_tbl clk_tbl_rot[] = {
1398 { 27000000, P_PXO, 1 },
1399 { 29540000, P_PLL8, 13 },
1400 { 32000000, P_PLL8, 12 },
1401 { 38400000, P_PLL8, 10 },
1402 { 48000000, P_PLL8, 8 },
1403 { 54860000, P_PLL8, 7 },
1404 { 64000000, P_PLL8, 6 },
1405 { 76800000, P_PLL8, 5 },
1406 { 96000000, P_PLL8, 4 },
1407 { 100000000, P_PLL2, 8 },
1408 { 114290000, P_PLL2, 7 },
1409 { 133330000, P_PLL2, 6 },
1410 { 160000000, P_PLL2, 5 },
1411 { 200000000, P_PLL2, 4 },
1412 { }
1413 };
1414
1415 static struct clk_dyn_rcg rot_src = {
1416 .ns_reg[0] = 0x00e8,
1417 .ns_reg[1] = 0x00e8,
1418 .bank_reg = 0x00e8,
1419 .p[0] = {
1420 .pre_div_shift = 22,
1421 .pre_div_width = 4,
1422 },
1423 .p[1] = {
1424 .pre_div_shift = 26,
1425 .pre_div_width = 4,
1426 },
1427 .s[0] = {
1428 .src_sel_shift = 16,
1429 .parent_map = mmcc_pxo_pll8_pll2_map,
1430 },
1431 .s[1] = {
1432 .src_sel_shift = 19,
1433 .parent_map = mmcc_pxo_pll8_pll2_map,
1434 },
1435 .mux_sel_bit = 30,
1436 .freq_tbl = clk_tbl_rot,
1437 .clkr = {
1438 .enable_reg = 0x00e0,
1439 .enable_mask = BIT(2),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "rot_src",
1442 .parent_data = mmcc_pxo_pll8_pll2,
1443 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1444 .ops = &clk_dyn_rcg_ops,
1445 },
1446 },
1447 };
1448
1449 static struct clk_branch rot_clk = {
1450 .halt_reg = 0x01d0,
1451 .halt_bit = 15,
1452 .clkr = {
1453 .enable_reg = 0x00e0,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "rot_clk",
1457 .parent_hws = (const struct clk_hw*[]){
1458 &rot_src.clkr.hw
1459 },
1460 .num_parents = 1,
1461 .ops = &clk_branch_ops,
1462 .flags = CLK_SET_RATE_PARENT,
1463 },
1464 },
1465 };
1466
1467 static const struct parent_map mmcc_pxo_hdmi_map[] = {
1468 { P_PXO, 0 },
1469 { P_HDMI_PLL, 3 }
1470 };
1471
1472 static const struct clk_parent_data mmcc_pxo_hdmi[] = {
1473 { .fw_name = "pxo", .name = "pxo_board" },
1474 { .fw_name = "hdmipll", .name = "hdmi_pll" },
1475 };
1476
1477 static const struct freq_tbl clk_tbl_tv[] = {
1478 { .src = P_HDMI_PLL, .pre_div = 1 },
1479 { }
1480 };
1481
1482 static struct clk_rcg tv_src = {
1483 .ns_reg = 0x00f4,
1484 .md_reg = 0x00f0,
1485 .mn = {
1486 .mnctr_en_bit = 5,
1487 .mnctr_reset_bit = 7,
1488 .mnctr_mode_shift = 6,
1489 .n_val_shift = 16,
1490 .m_val_shift = 8,
1491 .width = 8,
1492 },
1493 .p = {
1494 .pre_div_shift = 14,
1495 .pre_div_width = 2,
1496 },
1497 .s = {
1498 .src_sel_shift = 0,
1499 .parent_map = mmcc_pxo_hdmi_map,
1500 },
1501 .freq_tbl = clk_tbl_tv,
1502 .clkr = {
1503 .enable_reg = 0x00ec,
1504 .enable_mask = BIT(2),
1505 .hw.init = &(struct clk_init_data){
1506 .name = "tv_src",
1507 .parent_data = mmcc_pxo_hdmi,
1508 .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi),
1509 .ops = &clk_rcg_bypass_ops,
1510 .flags = CLK_SET_RATE_PARENT,
1511 },
1512 },
1513 };
1514
1515 static struct clk_branch tv_enc_clk = {
1516 .halt_reg = 0x01d4,
1517 .halt_bit = 9,
1518 .clkr = {
1519 .enable_reg = 0x00ec,
1520 .enable_mask = BIT(8),
1521 .hw.init = &(struct clk_init_data){
1522 .parent_hws = (const struct clk_hw*[]){
1523 &tv_src.clkr.hw,
1524 },
1525 .num_parents = 1,
1526 .name = "tv_enc_clk",
1527 .ops = &clk_branch_ops,
1528 .flags = CLK_SET_RATE_PARENT,
1529 },
1530 },
1531 };
1532
1533 static struct clk_branch tv_dac_clk = {
1534 .halt_reg = 0x01d4,
1535 .halt_bit = 10,
1536 .clkr = {
1537 .enable_reg = 0x00ec,
1538 .enable_mask = BIT(10),
1539 .hw.init = &(struct clk_init_data){
1540 .parent_hws = (const struct clk_hw*[]){
1541 &tv_src.clkr.hw,
1542 },
1543 .num_parents = 1,
1544 .name = "tv_dac_clk",
1545 .ops = &clk_branch_ops,
1546 .flags = CLK_SET_RATE_PARENT,
1547 },
1548 },
1549 };
1550
1551 static struct clk_branch mdp_tv_clk = {
1552 .halt_reg = 0x01d4,
1553 .halt_bit = 12,
1554 .clkr = {
1555 .enable_reg = 0x00ec,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .parent_hws = (const struct clk_hw*[]){
1559 &tv_src.clkr.hw,
1560 },
1561 .num_parents = 1,
1562 .name = "mdp_tv_clk",
1563 .ops = &clk_branch_ops,
1564 .flags = CLK_SET_RATE_PARENT,
1565 },
1566 },
1567 };
1568
1569 static struct clk_branch hdmi_tv_clk = {
1570 .halt_reg = 0x01d4,
1571 .halt_bit = 11,
1572 .clkr = {
1573 .enable_reg = 0x00ec,
1574 .enable_mask = BIT(12),
1575 .hw.init = &(struct clk_init_data){
1576 .parent_hws = (const struct clk_hw*[]){
1577 &tv_src.clkr.hw,
1578 },
1579 .num_parents = 1,
1580 .name = "hdmi_tv_clk",
1581 .ops = &clk_branch_ops,
1582 .flags = CLK_SET_RATE_PARENT,
1583 },
1584 },
1585 };
1586
1587 static struct clk_branch rgb_tv_clk = {
1588 .halt_reg = 0x0240,
1589 .halt_bit = 27,
1590 .clkr = {
1591 .enable_reg = 0x0124,
1592 .enable_mask = BIT(14),
1593 .hw.init = &(struct clk_init_data){
1594 .parent_hws = (const struct clk_hw*[]){
1595 &tv_src.clkr.hw,
1596 },
1597 .num_parents = 1,
1598 .name = "rgb_tv_clk",
1599 .ops = &clk_branch_ops,
1600 .flags = CLK_SET_RATE_PARENT,
1601 },
1602 },
1603 };
1604
1605 static struct clk_branch npl_tv_clk = {
1606 .halt_reg = 0x0240,
1607 .halt_bit = 26,
1608 .clkr = {
1609 .enable_reg = 0x0124,
1610 .enable_mask = BIT(16),
1611 .hw.init = &(struct clk_init_data){
1612 .parent_hws = (const struct clk_hw*[]){
1613 &tv_src.clkr.hw,
1614 },
1615 .num_parents = 1,
1616 .name = "npl_tv_clk",
1617 .ops = &clk_branch_ops,
1618 .flags = CLK_SET_RATE_PARENT,
1619 },
1620 },
1621 };
1622
1623 static struct clk_branch hdmi_app_clk = {
1624 .halt_reg = 0x01cc,
1625 .halt_bit = 25,
1626 .clkr = {
1627 .enable_reg = 0x005c,
1628 .enable_mask = BIT(11),
1629 .hw.init = &(struct clk_init_data){
1630 .parent_data = (const struct clk_parent_data[]){
1631 { .fw_name = "pxo", .name = "pxo_board" },
1632 },
1633 .num_parents = 1,
1634 .name = "hdmi_app_clk",
1635 .ops = &clk_branch_ops,
1636 },
1637 },
1638 };
1639
1640 static const struct freq_tbl clk_tbl_vcodec[] = {
1641 F_MN( 27000000, P_PXO, 1, 0),
1642 F_MN( 32000000, P_PLL8, 1, 12),
1643 F_MN( 48000000, P_PLL8, 1, 8),
1644 F_MN( 54860000, P_PLL8, 1, 7),
1645 F_MN( 96000000, P_PLL8, 1, 4),
1646 F_MN(133330000, P_PLL2, 1, 6),
1647 F_MN(200000000, P_PLL2, 1, 4),
1648 F_MN(228570000, P_PLL2, 2, 7),
1649 F_MN(266670000, P_PLL2, 1, 3),
1650 { }
1651 };
1652
1653 static struct clk_dyn_rcg vcodec_src = {
1654 .ns_reg[0] = 0x0100,
1655 .ns_reg[1] = 0x0100,
1656 .md_reg[0] = 0x00fc,
1657 .md_reg[1] = 0x0128,
1658 .bank_reg = 0x00f8,
1659 .mn[0] = {
1660 .mnctr_en_bit = 5,
1661 .mnctr_reset_bit = 31,
1662 .mnctr_mode_shift = 6,
1663 .n_val_shift = 11,
1664 .m_val_shift = 8,
1665 .width = 8,
1666 },
1667 .mn[1] = {
1668 .mnctr_en_bit = 10,
1669 .mnctr_reset_bit = 30,
1670 .mnctr_mode_shift = 11,
1671 .n_val_shift = 19,
1672 .m_val_shift = 8,
1673 .width = 8,
1674 },
1675 .s[0] = {
1676 .src_sel_shift = 27,
1677 .parent_map = mmcc_pxo_pll8_pll2_map,
1678 },
1679 .s[1] = {
1680 .src_sel_shift = 0,
1681 .parent_map = mmcc_pxo_pll8_pll2_map,
1682 },
1683 .mux_sel_bit = 13,
1684 .freq_tbl = clk_tbl_vcodec,
1685 .clkr = {
1686 .enable_reg = 0x00f8,
1687 .enable_mask = BIT(2),
1688 .hw.init = &(struct clk_init_data){
1689 .name = "vcodec_src",
1690 .parent_data = mmcc_pxo_pll8_pll2,
1691 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1692 .ops = &clk_dyn_rcg_ops,
1693 },
1694 },
1695 };
1696
1697 static struct clk_branch vcodec_clk = {
1698 .halt_reg = 0x01d0,
1699 .halt_bit = 29,
1700 .clkr = {
1701 .enable_reg = 0x00f8,
1702 .enable_mask = BIT(0),
1703 .hw.init = &(struct clk_init_data){
1704 .name = "vcodec_clk",
1705 .parent_hws = (const struct clk_hw*[]){
1706 &vcodec_src.clkr.hw
1707 },
1708 .num_parents = 1,
1709 .ops = &clk_branch_ops,
1710 .flags = CLK_SET_RATE_PARENT,
1711 },
1712 },
1713 };
1714
1715 static const struct freq_tbl clk_tbl_vpe[] = {
1716 { 27000000, P_PXO, 1 },
1717 { 34909000, P_PLL8, 11 },
1718 { 38400000, P_PLL8, 10 },
1719 { 64000000, P_PLL8, 6 },
1720 { 76800000, P_PLL8, 5 },
1721 { 96000000, P_PLL8, 4 },
1722 { 100000000, P_PLL2, 8 },
1723 { 160000000, P_PLL2, 5 },
1724 { }
1725 };
1726
1727 static struct clk_rcg vpe_src = {
1728 .ns_reg = 0x0118,
1729 .p = {
1730 .pre_div_shift = 12,
1731 .pre_div_width = 4,
1732 },
1733 .s = {
1734 .src_sel_shift = 0,
1735 .parent_map = mmcc_pxo_pll8_pll2_map,
1736 },
1737 .freq_tbl = clk_tbl_vpe,
1738 .clkr = {
1739 .enable_reg = 0x0110,
1740 .enable_mask = BIT(2),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "vpe_src",
1743 .parent_data = mmcc_pxo_pll8_pll2,
1744 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1745 .ops = &clk_rcg_ops,
1746 },
1747 },
1748 };
1749
1750 static struct clk_branch vpe_clk = {
1751 .halt_reg = 0x01c8,
1752 .halt_bit = 28,
1753 .clkr = {
1754 .enable_reg = 0x0110,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "vpe_clk",
1758 .parent_hws = (const struct clk_hw*[]){
1759 &vpe_src.clkr.hw
1760 },
1761 .num_parents = 1,
1762 .ops = &clk_branch_ops,
1763 .flags = CLK_SET_RATE_PARENT,
1764 },
1765 },
1766 };
1767
1768 static const struct freq_tbl clk_tbl_vfe[] = {
1769 { 13960000, P_PLL8, 1, 2, 55 },
1770 { 27000000, P_PXO, 1, 0, 0 },
1771 { 36570000, P_PLL8, 1, 2, 21 },
1772 { 38400000, P_PLL8, 2, 1, 5 },
1773 { 45180000, P_PLL8, 1, 2, 17 },
1774 { 48000000, P_PLL8, 2, 1, 4 },
1775 { 54860000, P_PLL8, 1, 1, 7 },
1776 { 64000000, P_PLL8, 2, 1, 3 },
1777 { 76800000, P_PLL8, 1, 1, 5 },
1778 { 96000000, P_PLL8, 2, 1, 2 },
1779 { 109710000, P_PLL8, 1, 2, 7 },
1780 { 128000000, P_PLL8, 1, 1, 3 },
1781 { 153600000, P_PLL8, 1, 2, 5 },
1782 { 200000000, P_PLL2, 2, 1, 2 },
1783 { 228570000, P_PLL2, 1, 2, 7 },
1784 { 266667000, P_PLL2, 1, 1, 3 },
1785 { 320000000, P_PLL2, 1, 2, 5 },
1786 { }
1787 };
1788
1789 static struct clk_rcg vfe_src = {
1790 .ns_reg = 0x0108,
1791 .mn = {
1792 .mnctr_en_bit = 5,
1793 .mnctr_reset_bit = 7,
1794 .mnctr_mode_shift = 6,
1795 .n_val_shift = 16,
1796 .m_val_shift = 8,
1797 .width = 8,
1798 },
1799 .p = {
1800 .pre_div_shift = 10,
1801 .pre_div_width = 1,
1802 },
1803 .s = {
1804 .src_sel_shift = 0,
1805 .parent_map = mmcc_pxo_pll8_pll2_map,
1806 },
1807 .freq_tbl = clk_tbl_vfe,
1808 .clkr = {
1809 .enable_reg = 0x0104,
1810 .enable_mask = BIT(2),
1811 .hw.init = &(struct clk_init_data){
1812 .name = "vfe_src",
1813 .parent_data = mmcc_pxo_pll8_pll2,
1814 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1815 .ops = &clk_rcg_ops,
1816 },
1817 },
1818 };
1819
1820 static struct clk_branch vfe_clk = {
1821 .halt_reg = 0x01cc,
1822 .halt_bit = 6,
1823 .clkr = {
1824 .enable_reg = 0x0104,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data){
1827 .name = "vfe_clk",
1828 .parent_hws = (const struct clk_hw*[]){
1829 &vfe_src.clkr.hw
1830 },
1831 .num_parents = 1,
1832 .ops = &clk_branch_ops,
1833 .flags = CLK_SET_RATE_PARENT,
1834 },
1835 },
1836 };
1837
1838 static struct clk_branch vfe_csi_clk = {
1839 .halt_reg = 0x01cc,
1840 .halt_bit = 8,
1841 .clkr = {
1842 .enable_reg = 0x0104,
1843 .enable_mask = BIT(12),
1844 .hw.init = &(struct clk_init_data){
1845 .parent_hws = (const struct clk_hw*[]){
1846 &vfe_src.clkr.hw
1847 },
1848 .num_parents = 1,
1849 .name = "vfe_csi_clk",
1850 .ops = &clk_branch_ops,
1851 .flags = CLK_SET_RATE_PARENT,
1852 },
1853 },
1854 };
1855
1856 static struct clk_branch gmem_axi_clk = {
1857 .halt_reg = 0x01d8,
1858 .halt_bit = 6,
1859 .clkr = {
1860 .enable_reg = 0x0018,
1861 .enable_mask = BIT(24),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "gmem_axi_clk",
1864 .ops = &clk_branch_ops,
1865 },
1866 },
1867 };
1868
1869 static struct clk_branch ijpeg_axi_clk = {
1870 .hwcg_reg = 0x0018,
1871 .hwcg_bit = 11,
1872 .halt_reg = 0x01d8,
1873 .halt_bit = 4,
1874 .clkr = {
1875 .enable_reg = 0x0018,
1876 .enable_mask = BIT(21),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "ijpeg_axi_clk",
1879 .ops = &clk_branch_ops,
1880 },
1881 },
1882 };
1883
1884 static struct clk_branch mmss_imem_axi_clk = {
1885 .hwcg_reg = 0x0018,
1886 .hwcg_bit = 15,
1887 .halt_reg = 0x01d8,
1888 .halt_bit = 7,
1889 .clkr = {
1890 .enable_reg = 0x0018,
1891 .enable_mask = BIT(22),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "mmss_imem_axi_clk",
1894 .ops = &clk_branch_ops,
1895 },
1896 },
1897 };
1898
1899 static struct clk_branch jpegd_axi_clk = {
1900 .halt_reg = 0x01d8,
1901 .halt_bit = 5,
1902 .clkr = {
1903 .enable_reg = 0x0018,
1904 .enable_mask = BIT(25),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "jpegd_axi_clk",
1907 .ops = &clk_branch_ops,
1908 },
1909 },
1910 };
1911
1912 static struct clk_branch vcodec_axi_b_clk = {
1913 .hwcg_reg = 0x0114,
1914 .hwcg_bit = 22,
1915 .halt_reg = 0x01e8,
1916 .halt_bit = 25,
1917 .clkr = {
1918 .enable_reg = 0x0114,
1919 .enable_mask = BIT(23),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "vcodec_axi_b_clk",
1922 .ops = &clk_branch_ops,
1923 },
1924 },
1925 };
1926
1927 static struct clk_branch vcodec_axi_a_clk = {
1928 .hwcg_reg = 0x0114,
1929 .hwcg_bit = 24,
1930 .halt_reg = 0x01e8,
1931 .halt_bit = 26,
1932 .clkr = {
1933 .enable_reg = 0x0114,
1934 .enable_mask = BIT(25),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "vcodec_axi_a_clk",
1937 .ops = &clk_branch_ops,
1938 },
1939 },
1940 };
1941
1942 static struct clk_branch vcodec_axi_clk = {
1943 .hwcg_reg = 0x0018,
1944 .hwcg_bit = 13,
1945 .halt_reg = 0x01d8,
1946 .halt_bit = 3,
1947 .clkr = {
1948 .enable_reg = 0x0018,
1949 .enable_mask = BIT(19),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "vcodec_axi_clk",
1952 .ops = &clk_branch_ops,
1953 },
1954 },
1955 };
1956
1957 static struct clk_branch vfe_axi_clk = {
1958 .halt_reg = 0x01d8,
1959 .halt_bit = 0,
1960 .clkr = {
1961 .enable_reg = 0x0018,
1962 .enable_mask = BIT(18),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "vfe_axi_clk",
1965 .ops = &clk_branch_ops,
1966 },
1967 },
1968 };
1969
1970 static struct clk_branch mdp_axi_clk = {
1971 .hwcg_reg = 0x0018,
1972 .hwcg_bit = 16,
1973 .halt_reg = 0x01d8,
1974 .halt_bit = 8,
1975 .clkr = {
1976 .enable_reg = 0x0018,
1977 .enable_mask = BIT(23),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "mdp_axi_clk",
1980 .ops = &clk_branch_ops,
1981 },
1982 },
1983 };
1984
1985 static struct clk_branch rot_axi_clk = {
1986 .hwcg_reg = 0x0020,
1987 .hwcg_bit = 25,
1988 .halt_reg = 0x01d8,
1989 .halt_bit = 2,
1990 .clkr = {
1991 .enable_reg = 0x0020,
1992 .enable_mask = BIT(24),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "rot_axi_clk",
1995 .ops = &clk_branch_ops,
1996 },
1997 },
1998 };
1999
2000 static struct clk_branch vcap_axi_clk = {
2001 .halt_reg = 0x0240,
2002 .halt_bit = 20,
2003 .hwcg_reg = 0x0244,
2004 .hwcg_bit = 11,
2005 .clkr = {
2006 .enable_reg = 0x0244,
2007 .enable_mask = BIT(12),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "vcap_axi_clk",
2010 .ops = &clk_branch_ops,
2011 },
2012 },
2013 };
2014
2015 static struct clk_branch vpe_axi_clk = {
2016 .hwcg_reg = 0x0020,
2017 .hwcg_bit = 27,
2018 .halt_reg = 0x01d8,
2019 .halt_bit = 1,
2020 .clkr = {
2021 .enable_reg = 0x0020,
2022 .enable_mask = BIT(26),
2023 .hw.init = &(struct clk_init_data){
2024 .name = "vpe_axi_clk",
2025 .ops = &clk_branch_ops,
2026 },
2027 },
2028 };
2029
2030 static struct clk_branch gfx3d_axi_clk = {
2031 .hwcg_reg = 0x0244,
2032 .hwcg_bit = 24,
2033 .halt_reg = 0x0240,
2034 .halt_bit = 30,
2035 .clkr = {
2036 .enable_reg = 0x0244,
2037 .enable_mask = BIT(25),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gfx3d_axi_clk",
2040 .ops = &clk_branch_ops,
2041 },
2042 },
2043 };
2044
2045 static struct clk_branch amp_ahb_clk = {
2046 .halt_reg = 0x01dc,
2047 .halt_bit = 18,
2048 .clkr = {
2049 .enable_reg = 0x0008,
2050 .enable_mask = BIT(24),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "amp_ahb_clk",
2053 .ops = &clk_branch_ops,
2054 },
2055 },
2056 };
2057
2058 static struct clk_branch csi_ahb_clk = {
2059 .halt_reg = 0x01dc,
2060 .halt_bit = 16,
2061 .clkr = {
2062 .enable_reg = 0x0008,
2063 .enable_mask = BIT(7),
2064 .hw.init = &(struct clk_init_data){
2065 .name = "csi_ahb_clk",
2066 .ops = &clk_branch_ops,
2067 },
2068 },
2069 };
2070
2071 static struct clk_branch dsi_m_ahb_clk = {
2072 .halt_reg = 0x01dc,
2073 .halt_bit = 19,
2074 .clkr = {
2075 .enable_reg = 0x0008,
2076 .enable_mask = BIT(9),
2077 .hw.init = &(struct clk_init_data){
2078 .name = "dsi_m_ahb_clk",
2079 .ops = &clk_branch_ops,
2080 },
2081 },
2082 };
2083
2084 static struct clk_branch dsi_s_ahb_clk = {
2085 .hwcg_reg = 0x0038,
2086 .hwcg_bit = 20,
2087 .halt_reg = 0x01dc,
2088 .halt_bit = 21,
2089 .clkr = {
2090 .enable_reg = 0x0008,
2091 .enable_mask = BIT(18),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "dsi_s_ahb_clk",
2094 .ops = &clk_branch_ops,
2095 },
2096 },
2097 };
2098
2099 static struct clk_branch dsi2_m_ahb_clk = {
2100 .halt_reg = 0x01d8,
2101 .halt_bit = 18,
2102 .clkr = {
2103 .enable_reg = 0x0008,
2104 .enable_mask = BIT(17),
2105 .hw.init = &(struct clk_init_data){
2106 .name = "dsi2_m_ahb_clk",
2107 .ops = &clk_branch_ops,
2108 },
2109 },
2110 };
2111
2112 static struct clk_branch dsi2_s_ahb_clk = {
2113 .hwcg_reg = 0x0038,
2114 .hwcg_bit = 15,
2115 .halt_reg = 0x01dc,
2116 .halt_bit = 20,
2117 .clkr = {
2118 .enable_reg = 0x0008,
2119 .enable_mask = BIT(22),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "dsi2_s_ahb_clk",
2122 .ops = &clk_branch_ops,
2123 },
2124 },
2125 };
2126
2127 static struct clk_rcg dsi1_src = {
2128 .ns_reg = 0x0054,
2129 .md_reg = 0x0050,
2130 .mn = {
2131 .mnctr_en_bit = 5,
2132 .mnctr_reset_bit = 7,
2133 .mnctr_mode_shift = 6,
2134 .n_val_shift = 24,
2135 .m_val_shift = 8,
2136 .width = 8,
2137 },
2138 .p = {
2139 .pre_div_shift = 14,
2140 .pre_div_width = 2,
2141 },
2142 .s = {
2143 .src_sel_shift = 0,
2144 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2145 },
2146 .clkr = {
2147 .enable_reg = 0x004c,
2148 .enable_mask = BIT(2),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "dsi1_src",
2151 .parent_data = mmcc_pxo_dsi2_dsi1,
2152 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2153 .ops = &clk_rcg_bypass2_ops,
2154 .flags = CLK_SET_RATE_PARENT,
2155 },
2156 },
2157 };
2158
2159 static struct clk_branch dsi1_clk = {
2160 .halt_reg = 0x01d0,
2161 .halt_bit = 2,
2162 .clkr = {
2163 .enable_reg = 0x004c,
2164 .enable_mask = BIT(0),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "dsi1_clk",
2167 .parent_hws = (const struct clk_hw*[]){
2168 &dsi1_src.clkr.hw
2169 },
2170 .num_parents = 1,
2171 .ops = &clk_branch_ops,
2172 .flags = CLK_SET_RATE_PARENT,
2173 },
2174 },
2175 };
2176
2177 static struct clk_rcg dsi2_src = {
2178 .ns_reg = 0x012c,
2179 .md_reg = 0x00a8,
2180 .mn = {
2181 .mnctr_en_bit = 5,
2182 .mnctr_reset_bit = 7,
2183 .mnctr_mode_shift = 6,
2184 .n_val_shift = 24,
2185 .m_val_shift = 8,
2186 .width = 8,
2187 },
2188 .p = {
2189 .pre_div_shift = 14,
2190 .pre_div_width = 2,
2191 },
2192 .s = {
2193 .src_sel_shift = 0,
2194 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2195 },
2196 .clkr = {
2197 .enable_reg = 0x003c,
2198 .enable_mask = BIT(2),
2199 .hw.init = &(struct clk_init_data){
2200 .name = "dsi2_src",
2201 .parent_data = mmcc_pxo_dsi2_dsi1,
2202 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2203 .ops = &clk_rcg_bypass2_ops,
2204 .flags = CLK_SET_RATE_PARENT,
2205 },
2206 },
2207 };
2208
2209 static struct clk_branch dsi2_clk = {
2210 .halt_reg = 0x01d0,
2211 .halt_bit = 20,
2212 .clkr = {
2213 .enable_reg = 0x003c,
2214 .enable_mask = BIT(0),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "dsi2_clk",
2217 .parent_hws = (const struct clk_hw*[]){
2218 &dsi2_src.clkr.hw
2219 },
2220 .num_parents = 1,
2221 .ops = &clk_branch_ops,
2222 .flags = CLK_SET_RATE_PARENT,
2223 },
2224 },
2225 };
2226
2227 static struct clk_rcg dsi1_byte_src = {
2228 .ns_reg = 0x00b0,
2229 .p = {
2230 .pre_div_shift = 12,
2231 .pre_div_width = 4,
2232 },
2233 .s = {
2234 .src_sel_shift = 0,
2235 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2236 },
2237 .clkr = {
2238 .enable_reg = 0x0090,
2239 .enable_mask = BIT(2),
2240 .hw.init = &(struct clk_init_data){
2241 .name = "dsi1_byte_src",
2242 .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2243 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2244 .ops = &clk_rcg_bypass2_ops,
2245 .flags = CLK_SET_RATE_PARENT,
2246 },
2247 },
2248 };
2249
2250 static struct clk_branch dsi1_byte_clk = {
2251 .halt_reg = 0x01cc,
2252 .halt_bit = 21,
2253 .clkr = {
2254 .enable_reg = 0x0090,
2255 .enable_mask = BIT(0),
2256 .hw.init = &(struct clk_init_data){
2257 .name = "dsi1_byte_clk",
2258 .parent_hws = (const struct clk_hw*[]){
2259 &dsi1_byte_src.clkr.hw
2260 },
2261 .num_parents = 1,
2262 .ops = &clk_branch_ops,
2263 .flags = CLK_SET_RATE_PARENT,
2264 },
2265 },
2266 };
2267
2268 static struct clk_rcg dsi2_byte_src = {
2269 .ns_reg = 0x012c,
2270 .p = {
2271 .pre_div_shift = 12,
2272 .pre_div_width = 4,
2273 },
2274 .s = {
2275 .src_sel_shift = 0,
2276 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2277 },
2278 .clkr = {
2279 .enable_reg = 0x0130,
2280 .enable_mask = BIT(2),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "dsi2_byte_src",
2283 .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2284 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2285 .ops = &clk_rcg_bypass2_ops,
2286 .flags = CLK_SET_RATE_PARENT,
2287 },
2288 },
2289 };
2290
2291 static struct clk_branch dsi2_byte_clk = {
2292 .halt_reg = 0x01cc,
2293 .halt_bit = 20,
2294 .clkr = {
2295 .enable_reg = 0x00b4,
2296 .enable_mask = BIT(0),
2297 .hw.init = &(struct clk_init_data){
2298 .name = "dsi2_byte_clk",
2299 .parent_hws = (const struct clk_hw*[]){
2300 &dsi2_byte_src.clkr.hw
2301 },
2302 .num_parents = 1,
2303 .ops = &clk_branch_ops,
2304 .flags = CLK_SET_RATE_PARENT,
2305 },
2306 },
2307 };
2308
2309 static struct clk_rcg dsi1_esc_src = {
2310 .ns_reg = 0x0011c,
2311 .p = {
2312 .pre_div_shift = 12,
2313 .pre_div_width = 4,
2314 },
2315 .s = {
2316 .src_sel_shift = 0,
2317 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2318 },
2319 .clkr = {
2320 .enable_reg = 0x00cc,
2321 .enable_mask = BIT(2),
2322 .hw.init = &(struct clk_init_data){
2323 .name = "dsi1_esc_src",
2324 .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2325 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2326 .ops = &clk_rcg_esc_ops,
2327 },
2328 },
2329 };
2330
2331 static struct clk_branch dsi1_esc_clk = {
2332 .halt_reg = 0x01e8,
2333 .halt_bit = 1,
2334 .clkr = {
2335 .enable_reg = 0x00cc,
2336 .enable_mask = BIT(0),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "dsi1_esc_clk",
2339 .parent_hws = (const struct clk_hw*[]){
2340 &dsi1_esc_src.clkr.hw
2341 },
2342 .num_parents = 1,
2343 .ops = &clk_branch_ops,
2344 .flags = CLK_SET_RATE_PARENT,
2345 },
2346 },
2347 };
2348
2349 static struct clk_rcg dsi2_esc_src = {
2350 .ns_reg = 0x0150,
2351 .p = {
2352 .pre_div_shift = 12,
2353 .pre_div_width = 4,
2354 },
2355 .s = {
2356 .src_sel_shift = 0,
2357 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2358 },
2359 .clkr = {
2360 .enable_reg = 0x013c,
2361 .enable_mask = BIT(2),
2362 .hw.init = &(struct clk_init_data){
2363 .name = "dsi2_esc_src",
2364 .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2365 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2366 .ops = &clk_rcg_esc_ops,
2367 },
2368 },
2369 };
2370
2371 static struct clk_branch dsi2_esc_clk = {
2372 .halt_reg = 0x01e8,
2373 .halt_bit = 3,
2374 .clkr = {
2375 .enable_reg = 0x013c,
2376 .enable_mask = BIT(0),
2377 .hw.init = &(struct clk_init_data){
2378 .name = "dsi2_esc_clk",
2379 .parent_hws = (const struct clk_hw*[]){
2380 &dsi2_esc_src.clkr.hw
2381 },
2382 .num_parents = 1,
2383 .ops = &clk_branch_ops,
2384 .flags = CLK_SET_RATE_PARENT,
2385 },
2386 },
2387 };
2388
2389 static struct clk_rcg dsi1_pixel_src = {
2390 .ns_reg = 0x0138,
2391 .md_reg = 0x0134,
2392 .mn = {
2393 .mnctr_en_bit = 5,
2394 .mnctr_reset_bit = 7,
2395 .mnctr_mode_shift = 6,
2396 .n_val_shift = 16,
2397 .m_val_shift = 8,
2398 .width = 8,
2399 },
2400 .p = {
2401 .pre_div_shift = 12,
2402 .pre_div_width = 4,
2403 },
2404 .s = {
2405 .src_sel_shift = 0,
2406 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2407 },
2408 .clkr = {
2409 .enable_reg = 0x0130,
2410 .enable_mask = BIT(2),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "dsi1_pixel_src",
2413 .parent_data = mmcc_pxo_dsi2_dsi1,
2414 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2415 .ops = &clk_rcg_pixel_ops,
2416 },
2417 },
2418 };
2419
2420 static struct clk_branch dsi1_pixel_clk = {
2421 .halt_reg = 0x01d0,
2422 .halt_bit = 6,
2423 .clkr = {
2424 .enable_reg = 0x0130,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "mdp_pclk1_clk",
2428 .parent_hws = (const struct clk_hw*[]){
2429 &dsi1_pixel_src.clkr.hw
2430 },
2431 .num_parents = 1,
2432 .ops = &clk_branch_ops,
2433 .flags = CLK_SET_RATE_PARENT,
2434 },
2435 },
2436 };
2437
2438 static struct clk_rcg dsi2_pixel_src = {
2439 .ns_reg = 0x00e4,
2440 .md_reg = 0x00b8,
2441 .mn = {
2442 .mnctr_en_bit = 5,
2443 .mnctr_reset_bit = 7,
2444 .mnctr_mode_shift = 6,
2445 .n_val_shift = 16,
2446 .m_val_shift = 8,
2447 .width = 8,
2448 },
2449 .p = {
2450 .pre_div_shift = 12,
2451 .pre_div_width = 4,
2452 },
2453 .s = {
2454 .src_sel_shift = 0,
2455 .parent_map = mmcc_pxo_dsi2_dsi1_lvds_map,
2456 },
2457 .clkr = {
2458 .enable_reg = 0x0094,
2459 .enable_mask = BIT(2),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "dsi2_pixel_src",
2462 .parent_data = mmcc_pxo_dsi2_dsi1_lvds,
2463 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1_lvds),
2464 .ops = &clk_rcg_pixel_ops,
2465 },
2466 },
2467 };
2468
2469 static struct clk_branch dsi2_pixel_lvds_src = {
2470 .clkr = {
2471 .enable_reg = 0x0094,
2472 .enable_mask = BIT(0),
2473 .hw.init = &(struct clk_init_data){
2474 .name = "dsi2_pixel_lvds_src",
2475 .parent_hws = (const struct clk_hw*[]){
2476 &dsi2_pixel_src.clkr.hw
2477 },
2478 .num_parents = 1,
2479 .ops = &clk_branch_simple_ops,
2480 .flags = CLK_SET_RATE_PARENT,
2481 },
2482 },
2483 };
2484
2485 static struct clk_branch dsi2_pixel_clk = {
2486 .halt_reg = 0x01d0,
2487 .halt_bit = 19,
2488 .clkr = {
2489 .enable_reg = 0x0094,
2490 .enable_mask = 0,
2491 .hw.init = &(struct clk_init_data){
2492 .name = "mdp_pclk2_clk",
2493 .parent_hws = (const struct clk_hw*[]){
2494 &dsi2_pixel_src.clkr.hw
2495 },
2496 .num_parents = 1,
2497 .ops = &clk_branch_ops,
2498 .flags = CLK_SET_RATE_PARENT,
2499 },
2500 },
2501 };
2502
2503 static struct clk_branch lvds_clk = {
2504 .halt_reg = 0x024c,
2505 .halt_bit = 6,
2506 .clkr = {
2507 .enable_reg = 0x0264,
2508 .enable_mask = BIT(1),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "mdp_lvds_clk",
2511 .parent_hws = (const struct clk_hw*[]){
2512 &dsi2_pixel_lvds_src.clkr.hw
2513 },
2514 .num_parents = 1,
2515 .ops = &clk_branch_ops,
2516 .flags = CLK_SET_RATE_PARENT,
2517 },
2518 },
2519 };
2520
2521 static struct clk_branch gfx2d0_ahb_clk = {
2522 .hwcg_reg = 0x0038,
2523 .hwcg_bit = 28,
2524 .halt_reg = 0x01dc,
2525 .halt_bit = 2,
2526 .clkr = {
2527 .enable_reg = 0x0008,
2528 .enable_mask = BIT(19),
2529 .hw.init = &(struct clk_init_data){
2530 .name = "gfx2d0_ahb_clk",
2531 .ops = &clk_branch_ops,
2532 },
2533 },
2534 };
2535
2536 static struct clk_branch gfx2d1_ahb_clk = {
2537 .hwcg_reg = 0x0038,
2538 .hwcg_bit = 29,
2539 .halt_reg = 0x01dc,
2540 .halt_bit = 3,
2541 .clkr = {
2542 .enable_reg = 0x0008,
2543 .enable_mask = BIT(2),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "gfx2d1_ahb_clk",
2546 .ops = &clk_branch_ops,
2547 },
2548 },
2549 };
2550
2551 static struct clk_branch gfx3d_ahb_clk = {
2552 .hwcg_reg = 0x0038,
2553 .hwcg_bit = 27,
2554 .halt_reg = 0x01dc,
2555 .halt_bit = 4,
2556 .clkr = {
2557 .enable_reg = 0x0008,
2558 .enable_mask = BIT(3),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "gfx3d_ahb_clk",
2561 .ops = &clk_branch_ops,
2562 },
2563 },
2564 };
2565
2566 static struct clk_branch hdmi_m_ahb_clk = {
2567 .hwcg_reg = 0x0038,
2568 .hwcg_bit = 21,
2569 .halt_reg = 0x01dc,
2570 .halt_bit = 5,
2571 .clkr = {
2572 .enable_reg = 0x0008,
2573 .enable_mask = BIT(14),
2574 .hw.init = &(struct clk_init_data){
2575 .name = "hdmi_m_ahb_clk",
2576 .ops = &clk_branch_ops,
2577 },
2578 },
2579 };
2580
2581 static struct clk_branch hdmi_s_ahb_clk = {
2582 .hwcg_reg = 0x0038,
2583 .hwcg_bit = 22,
2584 .halt_reg = 0x01dc,
2585 .halt_bit = 6,
2586 .clkr = {
2587 .enable_reg = 0x0008,
2588 .enable_mask = BIT(4),
2589 .hw.init = &(struct clk_init_data){
2590 .name = "hdmi_s_ahb_clk",
2591 .ops = &clk_branch_ops,
2592 },
2593 },
2594 };
2595
2596 static struct clk_branch ijpeg_ahb_clk = {
2597 .halt_reg = 0x01dc,
2598 .halt_bit = 9,
2599 .clkr = {
2600 .enable_reg = 0x0008,
2601 .enable_mask = BIT(5),
2602 .hw.init = &(struct clk_init_data){
2603 .name = "ijpeg_ahb_clk",
2604 .ops = &clk_branch_ops,
2605 },
2606 },
2607 };
2608
2609 static struct clk_branch mmss_imem_ahb_clk = {
2610 .hwcg_reg = 0x0038,
2611 .hwcg_bit = 12,
2612 .halt_reg = 0x01dc,
2613 .halt_bit = 10,
2614 .clkr = {
2615 .enable_reg = 0x0008,
2616 .enable_mask = BIT(6),
2617 .hw.init = &(struct clk_init_data){
2618 .name = "mmss_imem_ahb_clk",
2619 .ops = &clk_branch_ops,
2620 },
2621 },
2622 };
2623
2624 static struct clk_branch jpegd_ahb_clk = {
2625 .halt_reg = 0x01dc,
2626 .halt_bit = 7,
2627 .clkr = {
2628 .enable_reg = 0x0008,
2629 .enable_mask = BIT(21),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "jpegd_ahb_clk",
2632 .ops = &clk_branch_ops,
2633 },
2634 },
2635 };
2636
2637 static struct clk_branch mdp_ahb_clk = {
2638 .halt_reg = 0x01dc,
2639 .halt_bit = 11,
2640 .clkr = {
2641 .enable_reg = 0x0008,
2642 .enable_mask = BIT(10),
2643 .hw.init = &(struct clk_init_data){
2644 .name = "mdp_ahb_clk",
2645 .ops = &clk_branch_ops,
2646 },
2647 },
2648 };
2649
2650 static struct clk_branch rot_ahb_clk = {
2651 .halt_reg = 0x01dc,
2652 .halt_bit = 13,
2653 .clkr = {
2654 .enable_reg = 0x0008,
2655 .enable_mask = BIT(12),
2656 .hw.init = &(struct clk_init_data){
2657 .name = "rot_ahb_clk",
2658 .ops = &clk_branch_ops,
2659 },
2660 },
2661 };
2662
2663 static struct clk_branch smmu_ahb_clk = {
2664 .hwcg_reg = 0x0008,
2665 .hwcg_bit = 26,
2666 .halt_reg = 0x01dc,
2667 .halt_bit = 22,
2668 .clkr = {
2669 .enable_reg = 0x0008,
2670 .enable_mask = BIT(15),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "smmu_ahb_clk",
2673 .ops = &clk_branch_ops,
2674 },
2675 },
2676 };
2677
2678 static struct clk_branch tv_enc_ahb_clk = {
2679 .halt_reg = 0x01dc,
2680 .halt_bit = 23,
2681 .clkr = {
2682 .enable_reg = 0x0008,
2683 .enable_mask = BIT(25),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "tv_enc_ahb_clk",
2686 .ops = &clk_branch_ops,
2687 },
2688 },
2689 };
2690
2691 static struct clk_branch vcap_ahb_clk = {
2692 .halt_reg = 0x0240,
2693 .halt_bit = 23,
2694 .clkr = {
2695 .enable_reg = 0x0248,
2696 .enable_mask = BIT(1),
2697 .hw.init = &(struct clk_init_data){
2698 .name = "vcap_ahb_clk",
2699 .ops = &clk_branch_ops,
2700 },
2701 },
2702 };
2703
2704 static struct clk_branch vcodec_ahb_clk = {
2705 .hwcg_reg = 0x0038,
2706 .hwcg_bit = 26,
2707 .halt_reg = 0x01dc,
2708 .halt_bit = 12,
2709 .clkr = {
2710 .enable_reg = 0x0008,
2711 .enable_mask = BIT(11),
2712 .hw.init = &(struct clk_init_data){
2713 .name = "vcodec_ahb_clk",
2714 .ops = &clk_branch_ops,
2715 },
2716 },
2717 };
2718
2719 static struct clk_branch vfe_ahb_clk = {
2720 .halt_reg = 0x01dc,
2721 .halt_bit = 14,
2722 .clkr = {
2723 .enable_reg = 0x0008,
2724 .enable_mask = BIT(13),
2725 .hw.init = &(struct clk_init_data){
2726 .name = "vfe_ahb_clk",
2727 .ops = &clk_branch_ops,
2728 },
2729 },
2730 };
2731
2732 static struct clk_branch vpe_ahb_clk = {
2733 .halt_reg = 0x01dc,
2734 .halt_bit = 15,
2735 .clkr = {
2736 .enable_reg = 0x0008,
2737 .enable_mask = BIT(16),
2738 .hw.init = &(struct clk_init_data){
2739 .name = "vpe_ahb_clk",
2740 .ops = &clk_branch_ops,
2741 },
2742 },
2743 };
2744
2745 static struct clk_regmap *mmcc_msm8960_clks[] = {
2746 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2747 [AMP_AHB_CLK] = &_ahb_clk.clkr,
2748 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2749 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2750 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2751 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2752 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2753 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2754 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2755 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2756 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2757 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2758 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2759 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2760 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2761 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2762 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2763 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2764 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2765 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2766 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2767 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2768 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2769 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2770 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2771 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2772 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2773 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2774 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2775 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2776 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2777 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2778 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2779 [CSI0_SRC] = &csi0_src.clkr,
2780 [CSI0_CLK] = &csi0_clk.clkr,
2781 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2782 [CSI1_SRC] = &csi1_src.clkr,
2783 [CSI1_CLK] = &csi1_clk.clkr,
2784 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2785 [CSI2_SRC] = &csi2_src.clkr,
2786 [CSI2_CLK] = &csi2_clk.clkr,
2787 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2788 [DSI_SRC] = &dsi1_src.clkr,
2789 [DSI_CLK] = &dsi1_clk.clkr,
2790 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2791 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2792 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2793 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2794 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2795 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2796 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2797 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2798 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2799 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2800 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2801 [GFX3D_SRC] = &gfx3d_src.clkr,
2802 [GFX3D_CLK] = &gfx3d_clk.clkr,
2803 [IJPEG_SRC] = &ijpeg_src.clkr,
2804 [IJPEG_CLK] = &ijpeg_clk.clkr,
2805 [JPEGD_SRC] = &jpegd_src.clkr,
2806 [JPEGD_CLK] = &jpegd_clk.clkr,
2807 [MDP_SRC] = &mdp_src.clkr,
2808 [MDP_CLK] = &mdp_clk.clkr,
2809 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2810 [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2811 [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2812 [DSI2_SRC] = &dsi2_src.clkr,
2813 [DSI2_CLK] = &dsi2_clk.clkr,
2814 [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2815 [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2816 [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2817 [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2818 [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2819 [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2820 [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
2821 [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
2822 [ROT_SRC] = &rot_src.clkr,
2823 [ROT_CLK] = &rot_clk.clkr,
2824 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2825 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2826 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2827 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2828 [TV_SRC] = &tv_src.clkr,
2829 [VCODEC_SRC] = &vcodec_src.clkr,
2830 [VCODEC_CLK] = &vcodec_clk.clkr,
2831 [VFE_SRC] = &vfe_src.clkr,
2832 [VFE_CLK] = &vfe_clk.clkr,
2833 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2834 [VPE_SRC] = &vpe_src.clkr,
2835 [VPE_CLK] = &vpe_clk.clkr,
2836 [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
2837 [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
2838 [CAMCLK0_SRC] = &camclk0_src.clkr,
2839 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2840 [CAMCLK1_SRC] = &camclk1_src.clkr,
2841 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2842 [CAMCLK2_SRC] = &camclk2_src.clkr,
2843 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2844 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2845 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2846 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2847 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2848 [PLL2] = &pll2.clkr,
2849 [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr,
2850 [LVDS_CLK] = &lvds_clk.clkr,
2851 };
2852
2853 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2854 [VPE_AXI_RESET] = { 0x0208, 15 },
2855 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2856 [MPD_AXI_RESET] = { 0x0208, 13 },
2857 [VFE_AXI_RESET] = { 0x0208, 9 },
2858 [SP_AXI_RESET] = { 0x0208, 8 },
2859 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2860 [ROT_AXI_RESET] = { 0x0208, 6 },
2861 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2862 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2863 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2864 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2865 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2866 [FAB_S0_AXI_RESET] = { 0x0208 },
2867 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2868 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2869 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2870 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2871 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2872 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2873 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2874 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2875 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2876 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2877 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2878 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2879 [APU_AHB_RESET] = { 0x020c, 18 },
2880 [CSI_AHB_RESET] = { 0x020c, 17 },
2881 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2882 [VPE_AHB_RESET] = { 0x020c, 14 },
2883 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2884 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2885 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2886 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2887 [HDMI_AHB_RESET] = { 0x020c, 9 },
2888 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2889 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2890 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2891 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2892 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2893 [MDP_AHB_RESET] = { 0x020c, 3 },
2894 [ROT_AHB_RESET] = { 0x020c, 2 },
2895 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2896 [VFE_AHB_RESET] = { 0x020c, 0 },
2897 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2898 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2899 [CSIPHY2_RESET] = { 0x0210, 29 },
2900 [CSI_PIX1_RESET] = { 0x0210, 28 },
2901 [CSIPHY0_RESET] = { 0x0210, 27 },
2902 [CSIPHY1_RESET] = { 0x0210, 26 },
2903 [DSI2_RESET] = { 0x0210, 25 },
2904 [VFE_CSI_RESET] = { 0x0210, 24 },
2905 [MDP_RESET] = { 0x0210, 21 },
2906 [AMP_RESET] = { 0x0210, 20 },
2907 [JPEGD_RESET] = { 0x0210, 19 },
2908 [CSI1_RESET] = { 0x0210, 18 },
2909 [VPE_RESET] = { 0x0210, 17 },
2910 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2911 [VFE_RESET] = { 0x0210, 15 },
2912 [GFX2D0_RESET] = { 0x0210, 14 },
2913 [GFX2D1_RESET] = { 0x0210, 13 },
2914 [GFX3D_RESET] = { 0x0210, 12 },
2915 [HDMI_RESET] = { 0x0210, 11 },
2916 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2917 [IJPEG_RESET] = { 0x0210, 9 },
2918 [CSI0_RESET] = { 0x0210, 8 },
2919 [DSI_RESET] = { 0x0210, 7 },
2920 [VCODEC_RESET] = { 0x0210, 6 },
2921 [MDP_TV_RESET] = { 0x0210, 4 },
2922 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2923 [ROT_RESET] = { 0x0210, 2 },
2924 [TV_HDMI_RESET] = { 0x0210, 1 },
2925 [TV_ENC_RESET] = { 0x0210 },
2926 [CSI2_RESET] = { 0x0214, 2 },
2927 [CSI_RDI1_RESET] = { 0x0214, 1 },
2928 [CSI_RDI2_RESET] = { 0x0214 },
2929 };
2930
2931 static struct clk_regmap *mmcc_apq8064_clks[] = {
2932 [AMP_AHB_CLK] = &_ahb_clk.clkr,
2933 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2934 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2935 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2936 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2937 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2938 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2939 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2940 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2941 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2942 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2943 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2944 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2945 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2946 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2947 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2948 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2949 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2950 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2951 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2952 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2953 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2954 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2955 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2956 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2957 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2958 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2959 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2960 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2961 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2962 [CSI0_SRC] = &csi0_src.clkr,
2963 [CSI0_CLK] = &csi0_clk.clkr,
2964 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2965 [CSI1_SRC] = &csi1_src.clkr,
2966 [CSI1_CLK] = &csi1_clk.clkr,
2967 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2968 [CSI2_SRC] = &csi2_src.clkr,
2969 [CSI2_CLK] = &csi2_clk.clkr,
2970 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2971 [DSI_SRC] = &dsi1_src.clkr,
2972 [DSI_CLK] = &dsi1_clk.clkr,
2973 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2974 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2975 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2976 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2977 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2978 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2979 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2980 [GFX3D_SRC] = &gfx3d_src.clkr,
2981 [GFX3D_CLK] = &gfx3d_clk.clkr,
2982 [IJPEG_SRC] = &ijpeg_src.clkr,
2983 [IJPEG_CLK] = &ijpeg_clk.clkr,
2984 [JPEGD_SRC] = &jpegd_src.clkr,
2985 [JPEGD_CLK] = &jpegd_clk.clkr,
2986 [MDP_SRC] = &mdp_src.clkr,
2987 [MDP_CLK] = &mdp_clk.clkr,
2988 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2989 [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2990 [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2991 [DSI2_SRC] = &dsi2_src.clkr,
2992 [DSI2_CLK] = &dsi2_clk.clkr,
2993 [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2994 [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2995 [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2996 [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2997 [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2998 [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2999 [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
3000 [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
3001 [ROT_SRC] = &rot_src.clkr,
3002 [ROT_CLK] = &rot_clk.clkr,
3003 [TV_DAC_CLK] = &tv_dac_clk.clkr,
3004 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
3005 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
3006 [TV_SRC] = &tv_src.clkr,
3007 [VCODEC_SRC] = &vcodec_src.clkr,
3008 [VCODEC_CLK] = &vcodec_clk.clkr,
3009 [VFE_SRC] = &vfe_src.clkr,
3010 [VFE_CLK] = &vfe_clk.clkr,
3011 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
3012 [VPE_SRC] = &vpe_src.clkr,
3013 [VPE_CLK] = &vpe_clk.clkr,
3014 [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
3015 [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
3016 [CAMCLK0_SRC] = &camclk0_src.clkr,
3017 [CAMCLK0_CLK] = &camclk0_clk.clkr,
3018 [CAMCLK1_SRC] = &camclk1_src.clkr,
3019 [CAMCLK1_CLK] = &camclk1_clk.clkr,
3020 [CAMCLK2_SRC] = &camclk2_src.clkr,
3021 [CAMCLK2_CLK] = &camclk2_clk.clkr,
3022 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
3023 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
3024 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
3025 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
3026 [PLL2] = &pll2.clkr,
3027 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
3028 [NPL_TV_CLK] = &npl_tv_clk.clkr,
3029 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
3030 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
3031 [VCAP_SRC] = &vcap_src.clkr,
3032 [VCAP_CLK] = &vcap_clk.clkr,
3033 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
3034 [PLL15] = &pll15.clkr,
3035 [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr,
3036 [LVDS_CLK] = &lvds_clk.clkr,
3037 };
3038
3039 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
3040 [GFX3D_AXI_RESET] = { 0x0208, 17 },
3041 [VCAP_AXI_RESET] = { 0x0208, 16 },
3042 [VPE_AXI_RESET] = { 0x0208, 15 },
3043 [IJPEG_AXI_RESET] = { 0x0208, 14 },
3044 [MPD_AXI_RESET] = { 0x0208, 13 },
3045 [VFE_AXI_RESET] = { 0x0208, 9 },
3046 [SP_AXI_RESET] = { 0x0208, 8 },
3047 [VCODEC_AXI_RESET] = { 0x0208, 7 },
3048 [ROT_AXI_RESET] = { 0x0208, 6 },
3049 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
3050 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
3051 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
3052 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
3053 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
3054 [FAB_S0_AXI_RESET] = { 0x0208 },
3055 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
3056 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
3057 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
3058 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
3059 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
3060 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
3061 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
3062 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
3063 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
3064 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
3065 [APU_AHB_RESET] = { 0x020c, 18 },
3066 [CSI_AHB_RESET] = { 0x020c, 17 },
3067 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
3068 [VPE_AHB_RESET] = { 0x020c, 14 },
3069 [FABRIC_AHB_RESET] = { 0x020c, 13 },
3070 [GFX3D_AHB_RESET] = { 0x020c, 10 },
3071 [HDMI_AHB_RESET] = { 0x020c, 9 },
3072 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
3073 [IJPEG_AHB_RESET] = { 0x020c, 7 },
3074 [DSI_M_AHB_RESET] = { 0x020c, 6 },
3075 [DSI_S_AHB_RESET] = { 0x020c, 5 },
3076 [JPEGD_AHB_RESET] = { 0x020c, 4 },
3077 [MDP_AHB_RESET] = { 0x020c, 3 },
3078 [ROT_AHB_RESET] = { 0x020c, 2 },
3079 [VCODEC_AHB_RESET] = { 0x020c, 1 },
3080 [VFE_AHB_RESET] = { 0x020c, 0 },
3081 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
3082 [VCAP_AHB_RESET] = { 0x0200, 2 },
3083 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
3084 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
3085 [CSIPHY2_RESET] = { 0x0210, 31 },
3086 [CSI_PIX1_RESET] = { 0x0210, 30 },
3087 [CSIPHY0_RESET] = { 0x0210, 29 },
3088 [CSIPHY1_RESET] = { 0x0210, 28 },
3089 [CSI_RDI_RESET] = { 0x0210, 27 },
3090 [CSI_PIX_RESET] = { 0x0210, 26 },
3091 [DSI2_RESET] = { 0x0210, 25 },
3092 [VFE_CSI_RESET] = { 0x0210, 24 },
3093 [MDP_RESET] = { 0x0210, 21 },
3094 [AMP_RESET] = { 0x0210, 20 },
3095 [JPEGD_RESET] = { 0x0210, 19 },
3096 [CSI1_RESET] = { 0x0210, 18 },
3097 [VPE_RESET] = { 0x0210, 17 },
3098 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
3099 [VFE_RESET] = { 0x0210, 15 },
3100 [GFX3D_RESET] = { 0x0210, 12 },
3101 [HDMI_RESET] = { 0x0210, 11 },
3102 [MMSS_IMEM_RESET] = { 0x0210, 10 },
3103 [IJPEG_RESET] = { 0x0210, 9 },
3104 [CSI0_RESET] = { 0x0210, 8 },
3105 [DSI_RESET] = { 0x0210, 7 },
3106 [VCODEC_RESET] = { 0x0210, 6 },
3107 [MDP_TV_RESET] = { 0x0210, 4 },
3108 [MDP_VSYNC_RESET] = { 0x0210, 3 },
3109 [ROT_RESET] = { 0x0210, 2 },
3110 [TV_HDMI_RESET] = { 0x0210, 1 },
3111 [VCAP_NPL_RESET] = { 0x0214, 4 },
3112 [VCAP_RESET] = { 0x0214, 3 },
3113 [CSI2_RESET] = { 0x0214, 2 },
3114 [CSI_RDI1_RESET] = { 0x0214, 1 },
3115 [CSI_RDI2_RESET] = { 0x0214 },
3116 };
3117
3118 static const struct regmap_config mmcc_msm8960_regmap_config = {
3119 .reg_bits = 32,
3120 .reg_stride = 4,
3121 .val_bits = 32,
3122 .max_register = 0x334,
3123 .fast_io = true,
3124 };
3125
3126 static const struct regmap_config mmcc_apq8064_regmap_config = {
3127 .reg_bits = 32,
3128 .reg_stride = 4,
3129 .val_bits = 32,
3130 .max_register = 0x350,
3131 .fast_io = true,
3132 };
3133
3134 static const struct qcom_cc_desc mmcc_msm8960_desc = {
3135 .config = &mmcc_msm8960_regmap_config,
3136 .clks = mmcc_msm8960_clks,
3137 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
3138 .resets = mmcc_msm8960_resets,
3139 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
3140 };
3141
3142 static const struct qcom_cc_desc mmcc_apq8064_desc = {
3143 .config = &mmcc_apq8064_regmap_config,
3144 .clks = mmcc_apq8064_clks,
3145 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
3146 .resets = mmcc_apq8064_resets,
3147 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
3148 };
3149
3150 static const struct of_device_id mmcc_msm8960_match_table[] = {
3151 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
3152 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
3153 { }
3154 };
3155 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
3156
mmcc_msm8960_probe(struct platform_device * pdev)3157 static int mmcc_msm8960_probe(struct platform_device *pdev)
3158 {
3159 struct regmap *regmap;
3160 struct device *dev = &pdev->dev;
3161 const struct qcom_cc_desc *desc = device_get_match_data(dev);
3162
3163 if (desc == &mmcc_apq8064_desc) {
3164 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
3165 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
3166 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3167 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3168 }
3169
3170 regmap = qcom_cc_map(pdev, desc);
3171 if (IS_ERR(regmap))
3172 return PTR_ERR(regmap);
3173
3174 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
3175
3176 return qcom_cc_really_probe(&pdev->dev, desc, regmap);
3177 }
3178
3179 static struct platform_driver mmcc_msm8960_driver = {
3180 .probe = mmcc_msm8960_probe,
3181 .driver = {
3182 .name = "mmcc-msm8960",
3183 .of_match_table = mmcc_msm8960_match_table,
3184 },
3185 };
3186
3187 module_platform_driver(mmcc_msm8960_driver);
3188
3189 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
3190 MODULE_LICENSE("GPL v2");
3191 MODULE_ALIAS("platform:mmcc-msm8960");
3192