1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_clock.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16
17 #include <dt-bindings/clock/qcom,lpass-sc7280.h>
18 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
19
20 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
22 #include "clk-rcg.h"
23 #include "clk-regmap.h"
24 #include "clk-regmap-divider.h"
25 #include "clk-regmap-mux.h"
26 #include "common.h"
27 #include "gdsc.h"
28 #include "reset.h"
29
30 enum {
31 P_BI_TCXO,
32 P_LPASS_AON_CC_PLL_OUT_EVEN,
33 P_LPASS_AON_CC_PLL_OUT_MAIN,
34 P_LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC,
35 P_LPASS_AON_CC_PLL_OUT_ODD,
36 P_LPASS_AUDIO_CC_PLL_OUT_AUX,
37 P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC,
38 P_LPASS_AUDIO_CC_PLL_MAIN_DIV_CLK,
39 };
40
41 static const struct pll_vco zonda_vco[] = {
42 { 595200000UL, 3600000000UL, 0 },
43 };
44
45 static struct clk_branch lpass_q6ss_ahbm_clk = {
46 .halt_reg = 0x901c,
47 .halt_check = BRANCH_HALT,
48 .clkr = {
49 .enable_reg = 0x901c,
50 .enable_mask = BIT(0),
51 .hw.init = &(struct clk_init_data){
52 .name = "lpass_q6ss_ahbm_clk",
53 .ops = &clk_branch2_ops,
54 },
55 },
56 };
57
58 static struct clk_branch lpass_q6ss_ahbs_clk = {
59 .halt_reg = 0x9020,
60 .halt_check = BRANCH_HALT_VOTED,
61 .clkr = {
62 .enable_reg = 0x9020,
63 .enable_mask = BIT(0),
64 .hw.init = &(struct clk_init_data){
65 .name = "lpass_q6ss_ahbs_clk",
66 .ops = &clk_branch2_ops,
67 },
68 },
69 };
70
71 /* 1128.96MHz configuration */
72 static const struct alpha_pll_config lpass_audio_cc_pll_config = {
73 .l = 0x3a,
74 .alpha = 0xcccc,
75 .config_ctl_val = 0x08200920,
76 .config_ctl_hi_val = 0x05002001,
77 .config_ctl_hi1_val = 0x00000000,
78 .user_ctl_val = 0x03000101,
79 };
80
81 static struct clk_alpha_pll lpass_audio_cc_pll = {
82 .offset = 0x0,
83 .vco_table = zonda_vco,
84 .num_vco = ARRAY_SIZE(zonda_vco),
85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
86 .clkr = {
87 .hw.init = &(const struct clk_init_data){
88 .name = "lpass_audio_cc_pll",
89 .parent_data = &(const struct clk_parent_data){
90 .index = 0,
91 },
92 .num_parents = 1,
93 .ops = &clk_alpha_pll_zonda_ops,
94 },
95 },
96 };
97
98 static const struct clk_div_table post_div_table_lpass_audio_cc_pll_out_aux2[] = {
99 { 0x1, 2 },
100 { }
101 };
102
103 static struct clk_alpha_pll_postdiv lpass_audio_cc_pll_out_aux2 = {
104 .offset = 0x0,
105 .post_div_shift = 8,
106 .post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
107 .num_post_div = ARRAY_SIZE(post_div_table_lpass_audio_cc_pll_out_aux2),
108 .width = 2,
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
110 .clkr.hw.init = &(const struct clk_init_data){
111 .name = "lpass_audio_cc_pll_out_aux2",
112 .parent_hws = (const struct clk_hw*[]){
113 &lpass_audio_cc_pll.clkr.hw,
114 },
115 .num_parents = 1,
116 .ops = &clk_alpha_pll_postdiv_zonda_ops,
117 },
118 };
119
120 static const struct pll_vco lucid_vco[] = {
121 { 249600000, 2000000000, 0 },
122 };
123
124 /* 614.4 MHz configuration */
125 static const struct alpha_pll_config lpass_aon_cc_pll_config = {
126 .l = 0x20,
127 .alpha = 0x0,
128 .config_ctl_val = 0x20485699,
129 .config_ctl_hi_val = 0x00002261,
130 .config_ctl_hi1_val = 0x329A299C,
131 .user_ctl_val = 0x00005100,
132 .user_ctl_hi_val = 0x00000805,
133 .user_ctl_hi1_val = 0x00000000,
134 };
135
136 static struct clk_alpha_pll lpass_aon_cc_pll = {
137 .offset = 0x0,
138 .vco_table = lucid_vco,
139 .num_vco = ARRAY_SIZE(lucid_vco),
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
141 .clkr = {
142 .hw.init = &(const struct clk_init_data){
143 .name = "lpass_aon_cc_pll",
144 .parent_data = &(const struct clk_parent_data){
145 .index = 0,
146 },
147 .num_parents = 1,
148 .ops = &clk_alpha_pll_lucid_ops,
149 },
150 },
151 };
152
153 static const struct clk_div_table post_div_table_lpass_aon_cc_pll_out_even[] = {
154 { 0x1, 2 },
155 { }
156 };
157
158 static struct clk_alpha_pll_postdiv lpass_aon_cc_pll_out_even = {
159 .offset = 0x0,
160 .post_div_shift = 8,
161 .post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
162 .num_post_div = ARRAY_SIZE(post_div_table_lpass_aon_cc_pll_out_even),
163 .width = 4,
164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
165 .clkr.hw.init = &(const struct clk_init_data){
166 .name = "lpass_aon_cc_pll_out_even",
167 .parent_hws = (const struct clk_hw*[]){
168 &lpass_aon_cc_pll.clkr.hw,
169 },
170 .num_parents = 1,
171 .ops = &clk_alpha_pll_postdiv_lucid_ops,
172 },
173 };
174
175 static const struct clk_div_table post_div_table_lpass_aon_cc_pll_out_odd[] = {
176 { 0x5, 5 },
177 { }
178 };
179
180 static struct clk_alpha_pll_postdiv lpass_aon_cc_pll_out_odd = {
181 .offset = 0x0,
182 .post_div_shift = 12,
183 .post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
184 .num_post_div = ARRAY_SIZE(post_div_table_lpass_aon_cc_pll_out_odd),
185 .width = 4,
186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
187 .clkr.hw.init = &(const struct clk_init_data){
188 .name = "lpass_aon_cc_pll_out_odd",
189 .parent_hws = (const struct clk_hw*[]){
190 &lpass_aon_cc_pll.clkr.hw,
191 },
192 .num_parents = 1,
193 .ops = &clk_alpha_pll_postdiv_lucid_ops,
194 },
195 };
196
197 static const struct parent_map lpass_audio_cc_parent_map_0[] = {
198 { P_BI_TCXO, 0 },
199 { P_LPASS_AUDIO_CC_PLL_OUT_AUX, 3 },
200 { P_LPASS_AON_CC_PLL_OUT_ODD, 5 },
201 { P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 6 },
202 };
203
204 static struct clk_regmap_div lpass_audio_cc_pll_out_aux2_div_clk_src;
205 static struct clk_regmap_div lpass_audio_cc_pll_out_main_div_clk_src;
206
207 static const struct clk_parent_data lpass_audio_cc_parent_data_0[] = {
208 { .index = 0 },
209 { .hw = &lpass_audio_cc_pll.clkr.hw },
210 { .hw = &lpass_aon_cc_pll_out_odd.clkr.hw },
211 { .hw = &lpass_audio_cc_pll_out_aux2_div_clk_src.clkr.hw },
212 };
213
214 static const struct parent_map lpass_aon_cc_parent_map_0[] = {
215 { P_BI_TCXO, 0 },
216 { P_LPASS_AON_CC_PLL_OUT_EVEN, 4 },
217 };
218
219 static const struct clk_parent_data lpass_aon_cc_parent_data_0[] = {
220 { .index = 0 },
221 { .hw = &lpass_aon_cc_pll_out_even.clkr.hw },
222 };
223
224 static const struct parent_map lpass_aon_cc_parent_map_1[] = {
225 { P_BI_TCXO, 0 },
226 { P_LPASS_AON_CC_PLL_OUT_ODD, 1 },
227 { P_LPASS_AUDIO_CC_PLL_MAIN_DIV_CLK, 6 },
228 };
229
230 static const struct clk_parent_data lpass_aon_cc_parent_data_1[] = {
231 { .index = 0 },
232 { .hw = &lpass_aon_cc_pll_out_odd.clkr.hw },
233 { .hw = &lpass_audio_cc_pll_out_main_div_clk_src.clkr.hw },
234 };
235
236 static const struct freq_tbl ftbl_lpass_aon_cc_main_rcg_clk_src[] = {
237 F(38400000, P_LPASS_AON_CC_PLL_OUT_EVEN, 8, 0, 0),
238 F(76800000, P_LPASS_AON_CC_PLL_OUT_EVEN, 4, 0, 0),
239 F(153600000, P_LPASS_AON_CC_PLL_OUT_EVEN, 2, 0, 0),
240 { }
241 };
242
243 static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
244 .cmd_rcgr = 0x1000,
245 .mnd_width = 0,
246 .hid_width = 5,
247 .parent_map = lpass_aon_cc_parent_map_0,
248 .freq_tbl = ftbl_lpass_aon_cc_main_rcg_clk_src,
249 .clkr.hw.init = &(const struct clk_init_data){
250 .name = "lpass_aon_cc_main_rcg_clk_src",
251 .parent_data = lpass_aon_cc_parent_data_0,
252 .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
253 .flags = CLK_OPS_PARENT_ENABLE,
254 .ops = &clk_rcg2_shared_ops,
255 },
256 };
257
258 static const struct freq_tbl ftbl_lpass_aon_cc_tx_mclk_rcg_clk_src[] = {
259 F(19200000, P_BI_TCXO, 1, 0, 0),
260 F(24576000, P_LPASS_AON_CC_PLL_OUT_ODD, 5, 0, 0),
261 { }
262 };
263
264 static struct clk_rcg2 lpass_aon_cc_tx_mclk_rcg_clk_src = {
265 .cmd_rcgr = 0x13004,
266 .mnd_width = 0,
267 .hid_width = 5,
268 .parent_map = lpass_aon_cc_parent_map_1,
269 .freq_tbl = ftbl_lpass_aon_cc_tx_mclk_rcg_clk_src,
270 .clkr.hw.init = &(const struct clk_init_data){
271 .name = "lpass_aon_cc_tx_mclk_rcg_clk_src",
272 .parent_data = lpass_aon_cc_parent_data_1,
273 .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_1),
274 .ops = &clk_rcg2_ops,
275 },
276 };
277
278 static struct clk_regmap_div lpass_audio_cc_pll_out_aux2_div_clk_src = {
279 .reg = 0x48,
280 .shift = 0,
281 .width = 4,
282 .clkr.hw.init = &(const struct clk_init_data) {
283 .name = "lpass_audio_cc_pll_out_aux2_div_clk_src",
284 .parent_hws = (const struct clk_hw*[]){
285 &lpass_audio_cc_pll_out_aux2.clkr.hw,
286 },
287 .num_parents = 1,
288 .flags = CLK_SET_RATE_PARENT,
289 .ops = &clk_regmap_div_ro_ops,
290 },
291 };
292
293 static struct clk_regmap_div lpass_audio_cc_pll_out_main_div_clk_src = {
294 .reg = 0x3c,
295 .shift = 0,
296 .width = 4,
297 .clkr.hw.init = &(const struct clk_init_data) {
298 .name = "lpass_audio_cc_pll_out_main_div_clk_src",
299 .parent_hws = (const struct clk_hw*[]){
300 &lpass_audio_cc_pll.clkr.hw,
301 },
302 .num_parents = 1,
303 .flags = CLK_SET_RATE_PARENT,
304 .ops = &clk_regmap_div_ro_ops,
305 },
306 };
307
308 static struct clk_regmap_div lpass_aon_cc_cdiv_tx_mclk_div_clk_src = {
309 .reg = 0x13010,
310 .shift = 0,
311 .width = 4,
312 .clkr.hw.init = &(const struct clk_init_data) {
313 .name = "lpass_aon_cc_cdiv_tx_mclk_div_clk_src",
314 .parent_hws = (const struct clk_hw*[]){
315 &lpass_aon_cc_tx_mclk_rcg_clk_src.clkr.hw,
316 },
317 .num_parents = 1,
318 .flags = CLK_SET_RATE_PARENT,
319 .ops = &clk_regmap_div_ro_ops,
320 },
321 };
322
323 static struct clk_regmap_div lpass_aon_cc_pll_out_main_cdiv_div_clk_src = {
324 .reg = 0x80,
325 .shift = 0,
326 .width = 4,
327 .clkr.hw.init = &(const struct clk_init_data) {
328 .name = "lpass_aon_cc_pll_out_main_cdiv_div_clk_src",
329 .parent_hws = (const struct clk_hw*[]){
330 &lpass_aon_cc_pll.clkr.hw,
331 },
332 .num_parents = 1,
333 .flags = CLK_SET_RATE_PARENT,
334 .ops = &clk_regmap_div_ro_ops,
335 },
336 };
337
338 static const struct freq_tbl ftbl_lpass_audio_cc_ext_mclk0_clk_src[] = {
339 F(256000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 32),
340 F(352800, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 32),
341 F(512000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 16),
342 F(705600, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 16),
343 F(768000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 16),
344 F(1024000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 8),
345 F(1411200, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 8),
346 F(1536000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 8),
347 F(2048000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 4),
348 F(2822400, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 4),
349 F(3072000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 4),
350 F(4096000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 2),
351 F(5644800, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 2),
352 F(6144000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 2),
353 F(8192000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 0, 0),
354 F(9600000, P_BI_TCXO, 2, 0, 0),
355 F(11289600, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 0, 0),
356 F(12288000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 0, 0),
357 F(19200000, P_BI_TCXO, 1, 0, 0),
358 F(22579200, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 5, 0, 0),
359 F(24576000, P_LPASS_AON_CC_PLL_OUT_ODD, 5, 0, 0),
360 { }
361 };
362
363 static struct clk_rcg2 lpass_audio_cc_ext_mclk0_clk_src = {
364 .cmd_rcgr = 0x20004,
365 .mnd_width = 8,
366 .hid_width = 5,
367 .parent_map = lpass_audio_cc_parent_map_0,
368 .freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
369 .clkr.hw.init = &(const struct clk_init_data){
370 .name = "lpass_audio_cc_ext_mclk0_clk_src",
371 .parent_data = lpass_audio_cc_parent_data_0,
372 .num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
373 .ops = &clk_rcg2_ops,
374 },
375 };
376
377 static struct clk_rcg2 lpass_audio_cc_ext_mclk1_clk_src = {
378 .cmd_rcgr = 0x21004,
379 .mnd_width = 8,
380 .hid_width = 5,
381 .parent_map = lpass_audio_cc_parent_map_0,
382 .freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
383 .clkr.hw.init = &(const struct clk_init_data){
384 .name = "lpass_audio_cc_ext_mclk1_clk_src",
385 .parent_data = lpass_audio_cc_parent_data_0,
386 .num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
387 .ops = &clk_rcg2_ops,
388 },
389 };
390
391 static struct clk_rcg2 lpass_audio_cc_rx_mclk_clk_src = {
392 .cmd_rcgr = 0x24004,
393 .mnd_width = 8,
394 .hid_width = 5,
395 .parent_map = lpass_audio_cc_parent_map_0,
396 .freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
397 .clkr.hw.init = &(const struct clk_init_data){
398 .name = "lpass_audio_cc_rx_mclk_clk_src",
399 .parent_data = lpass_audio_cc_parent_data_0,
400 .num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
401 .ops = &clk_rcg2_ops,
402 },
403 };
404
405 static struct clk_regmap_div lpass_audio_cc_cdiv_rx_mclk_div_clk_src = {
406 .reg = 0x240d0,
407 .shift = 0,
408 .width = 4,
409 .clkr.hw.init = &(const struct clk_init_data) {
410 .name = "lpass_audio_cc_cdiv_rx_mclk_div_clk_src",
411 .parent_hws = (const struct clk_hw*[]){
412 &lpass_audio_cc_rx_mclk_clk_src.clkr.hw,
413 },
414 .num_parents = 1,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_regmap_div_ro_ops,
417 },
418 };
419
420 static struct clk_branch lpass_aon_cc_audio_hm_h_clk;
421
422 static struct clk_branch lpass_audio_cc_codec_mem0_clk = {
423 .halt_reg = 0x1e004,
424 .halt_check = BRANCH_HALT,
425 .clkr = {
426 .enable_reg = 0x1e004,
427 .enable_mask = BIT(0),
428 .hw.init = &(const struct clk_init_data){
429 .name = "lpass_audio_cc_codec_mem0_clk",
430 .parent_hws = (const struct clk_hw*[]){
431 &lpass_aon_cc_audio_hm_h_clk.clkr.hw,
432 },
433 .num_parents = 1,
434 .flags = CLK_SET_RATE_PARENT,
435 .ops = &clk_branch2_ops,
436 },
437 },
438 };
439
440 static struct clk_branch lpass_audio_cc_codec_mem1_clk = {
441 .halt_reg = 0x1e008,
442 .halt_check = BRANCH_HALT,
443 .clkr = {
444 .enable_reg = 0x1e008,
445 .enable_mask = BIT(0),
446 .hw.init = &(const struct clk_init_data){
447 .name = "lpass_audio_cc_codec_mem1_clk",
448 .parent_hws = (const struct clk_hw*[]){
449 &lpass_aon_cc_audio_hm_h_clk.clkr.hw,
450 },
451 .num_parents = 1,
452 .flags = CLK_SET_RATE_PARENT,
453 .ops = &clk_branch2_ops,
454 },
455 },
456 };
457
458 static struct clk_branch lpass_audio_cc_codec_mem2_clk = {
459 .halt_reg = 0x1e00c,
460 .halt_check = BRANCH_HALT,
461 .clkr = {
462 .enable_reg = 0x1e00c,
463 .enable_mask = BIT(0),
464 .hw.init = &(const struct clk_init_data){
465 .name = "lpass_audio_cc_codec_mem2_clk",
466 .parent_hws = (const struct clk_hw*[]){
467 &lpass_aon_cc_audio_hm_h_clk.clkr.hw,
468 },
469 .num_parents = 1,
470 .flags = CLK_SET_RATE_PARENT,
471 .ops = &clk_branch2_ops,
472 },
473 },
474 };
475
476 static struct clk_branch lpass_audio_cc_codec_mem_clk = {
477 .halt_reg = 0x1e000,
478 .halt_check = BRANCH_HALT,
479 .clkr = {
480 .enable_reg = 0x1e000,
481 .enable_mask = BIT(0),
482 .hw.init = &(const struct clk_init_data){
483 .name = "lpass_audio_cc_codec_mem_clk",
484 .parent_hws = (const struct clk_hw*[]){
485 &lpass_aon_cc_audio_hm_h_clk.clkr.hw,
486 },
487 .num_parents = 1,
488 .flags = CLK_SET_RATE_PARENT,
489 .ops = &clk_branch2_ops,
490 },
491 },
492 };
493
494 static struct clk_branch lpass_audio_cc_ext_mclk0_clk = {
495 .halt_reg = 0x20018,
496 .halt_check = BRANCH_HALT,
497 .clkr = {
498 .enable_reg = 0x20018,
499 .enable_mask = BIT(0),
500 .hw.init = &(const struct clk_init_data){
501 .name = "lpass_audio_cc_ext_mclk0_clk",
502 .parent_hws = (const struct clk_hw*[]){
503 &lpass_audio_cc_ext_mclk0_clk_src.clkr.hw,
504 },
505 .num_parents = 1,
506 .flags = CLK_SET_RATE_PARENT,
507 .ops = &clk_branch2_ops,
508 },
509 },
510 };
511
512 static struct clk_branch lpass_audio_cc_ext_mclk1_clk = {
513 .halt_reg = 0x21018,
514 .halt_check = BRANCH_HALT,
515 .clkr = {
516 .enable_reg = 0x21018,
517 .enable_mask = BIT(0),
518 .hw.init = &(const struct clk_init_data){
519 .name = "lpass_audio_cc_ext_mclk1_clk",
520 .parent_hws = (const struct clk_hw*[]){
521 &lpass_audio_cc_ext_mclk1_clk_src.clkr.hw,
522 },
523 .num_parents = 1,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_branch2_ops,
526 },
527 },
528 };
529
530 static struct clk_branch lpass_audio_cc_rx_mclk_2x_clk = {
531 .halt_reg = 0x240cc,
532 .halt_check = BRANCH_HALT,
533 .clkr = {
534 .enable_reg = 0x240cc,
535 .enable_mask = BIT(0),
536 .hw.init = &(const struct clk_init_data){
537 .name = "lpass_audio_cc_rx_mclk_2x_clk",
538 .parent_hws = (const struct clk_hw*[]){
539 &lpass_audio_cc_rx_mclk_clk_src.clkr.hw,
540 },
541 .num_parents = 1,
542 .flags = CLK_SET_RATE_PARENT,
543 .ops = &clk_branch2_ops,
544 },
545 },
546 };
547
548 static struct clk_branch lpass_audio_cc_rx_mclk_clk = {
549 .halt_reg = 0x240d4,
550 .halt_check = BRANCH_HALT,
551 .clkr = {
552 .enable_reg = 0x240d4,
553 .enable_mask = BIT(0),
554 .hw.init = &(const struct clk_init_data){
555 .name = "lpass_audio_cc_rx_mclk_clk",
556 .parent_hws = (const struct clk_hw*[]){
557 &lpass_audio_cc_cdiv_rx_mclk_div_clk_src.clkr.hw,
558 },
559 .num_parents = 1,
560 .flags = CLK_SET_RATE_PARENT,
561 .ops = &clk_branch2_ops,
562 },
563 },
564 };
565
566 static struct clk_branch lpass_aon_cc_audio_hm_h_clk = {
567 .halt_reg = 0x9014,
568 .halt_check = BRANCH_HALT,
569 .clkr = {
570 .enable_reg = 0x9014,
571 .enable_mask = BIT(0),
572 .hw.init = &(const struct clk_init_data){
573 .name = "lpass_aon_cc_audio_hm_h_clk",
574 .parent_hws = (const struct clk_hw*[]){
575 &lpass_aon_cc_main_rcg_clk_src.clkr.hw,
576 },
577 .num_parents = 1,
578 .flags = CLK_SET_RATE_PARENT,
579 .ops = &clk_branch2_aon_ops,
580 },
581 },
582 };
583
584 static struct clk_branch lpass_aon_cc_va_mem0_clk = {
585 .halt_reg = 0x9028,
586 .halt_check = BRANCH_HALT,
587 .clkr = {
588 .enable_reg = 0x9028,
589 .enable_mask = BIT(0),
590 .hw.init = &(const struct clk_init_data){
591 .name = "lpass_aon_cc_va_mem0_clk",
592 .parent_hws = (const struct clk_hw*[]){
593 &lpass_aon_cc_main_rcg_clk_src.clkr.hw,
594 },
595 .num_parents = 1,
596 .flags = CLK_SET_RATE_PARENT,
597 .ops = &clk_branch2_ops,
598 },
599 },
600 };
601
602 static struct clk_branch lpass_aon_cc_tx_mclk_2x_clk = {
603 .halt_reg = 0x1300c,
604 .halt_check = BRANCH_HALT,
605 .clkr = {
606 .enable_reg = 0x1300c,
607 .enable_mask = BIT(0),
608 .hw.init = &(const struct clk_init_data){
609 .name = "lpass_aon_cc_tx_mclk_2x_clk",
610 .parent_hws = (const struct clk_hw*[]){
611 &lpass_aon_cc_tx_mclk_rcg_clk_src.clkr.hw,
612 },
613 .num_parents = 1,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_branch2_ops,
616 },
617 },
618 };
619
620 static struct clk_branch lpass_aon_cc_tx_mclk_clk = {
621 .halt_reg = 0x13014,
622 .halt_check = BRANCH_HALT,
623 .clkr = {
624 .enable_reg = 0x13014,
625 .enable_mask = BIT(0),
626 .hw.init = &(const struct clk_init_data){
627 .name = "lpass_aon_cc_tx_mclk_clk",
628 .parent_hws = (const struct clk_hw*[]){
629 &lpass_aon_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
630 },
631 .num_parents = 1,
632 .flags = CLK_SET_RATE_PARENT,
633 .ops = &clk_branch2_ops,
634 },
635 },
636 };
637
638 static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = {
639 .gdscr = 0x9090,
640 .pd = {
641 .name = "lpass_aon_cc_lpass_audio_hm_gdsc",
642 },
643 .pwrsts = PWRSTS_OFF_ON,
644 .flags = RETAIN_FF_ENABLE,
645 };
646
647 static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
648 [LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
649 [LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
650 };
651
652 static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] = {
653 [LPASS_AON_CC_AUDIO_HM_H_CLK] = &lpass_aon_cc_audio_hm_h_clk.clkr,
654 [LPASS_AON_CC_VA_MEM0_CLK] = &lpass_aon_cc_va_mem0_clk.clkr,
655 [LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &lpass_aon_cc_cdiv_tx_mclk_div_clk_src.clkr,
656 [LPASS_AON_CC_MAIN_RCG_CLK_SRC] = &lpass_aon_cc_main_rcg_clk_src.clkr,
657 [LPASS_AON_CC_PLL] = &lpass_aon_cc_pll.clkr,
658 [LPASS_AON_CC_PLL_OUT_EVEN] = &lpass_aon_cc_pll_out_even.clkr,
659 [LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC] =
660 &lpass_aon_cc_pll_out_main_cdiv_div_clk_src.clkr,
661 [LPASS_AON_CC_PLL_OUT_ODD] = &lpass_aon_cc_pll_out_odd.clkr,
662 [LPASS_AON_CC_TX_MCLK_2X_CLK] = &lpass_aon_cc_tx_mclk_2x_clk.clkr,
663 [LPASS_AON_CC_TX_MCLK_CLK] = &lpass_aon_cc_tx_mclk_clk.clkr,
664 [LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC] = &lpass_aon_cc_tx_mclk_rcg_clk_src.clkr,
665 };
666
667 static struct gdsc *lpass_aon_cc_sc7280_gdscs[] = {
668 [LPASS_AON_CC_LPASS_AUDIO_HM_GDSC] = &lpass_aon_cc_lpass_audio_hm_gdsc,
669 };
670
671 static struct clk_regmap *lpass_audio_cc_sc7280_clocks[] = {
672 [LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC] = &lpass_audio_cc_cdiv_rx_mclk_div_clk_src.clkr,
673 [LPASS_AUDIO_CC_CODEC_MEM0_CLK] = &lpass_audio_cc_codec_mem0_clk.clkr,
674 [LPASS_AUDIO_CC_CODEC_MEM1_CLK] = &lpass_audio_cc_codec_mem1_clk.clkr,
675 [LPASS_AUDIO_CC_CODEC_MEM2_CLK] = &lpass_audio_cc_codec_mem2_clk.clkr,
676 [LPASS_AUDIO_CC_CODEC_MEM_CLK] = &lpass_audio_cc_codec_mem_clk.clkr,
677 [LPASS_AUDIO_CC_EXT_MCLK0_CLK] = &lpass_audio_cc_ext_mclk0_clk.clkr,
678 [LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC] = &lpass_audio_cc_ext_mclk0_clk_src.clkr,
679 [LPASS_AUDIO_CC_EXT_MCLK1_CLK] = &lpass_audio_cc_ext_mclk1_clk.clkr,
680 [LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC] = &lpass_audio_cc_ext_mclk1_clk_src.clkr,
681 [LPASS_AUDIO_CC_PLL] = &lpass_audio_cc_pll.clkr,
682 [LPASS_AUDIO_CC_PLL_OUT_AUX2] = &lpass_audio_cc_pll_out_aux2.clkr,
683 [LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC] = &lpass_audio_cc_pll_out_aux2_div_clk_src.clkr,
684 [LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC] = &lpass_audio_cc_pll_out_main_div_clk_src.clkr,
685 [LPASS_AUDIO_CC_RX_MCLK_2X_CLK] = &lpass_audio_cc_rx_mclk_2x_clk.clkr,
686 [LPASS_AUDIO_CC_RX_MCLK_CLK] = &lpass_audio_cc_rx_mclk_clk.clkr,
687 [LPASS_AUDIO_CC_RX_MCLK_CLK_SRC] = &lpass_audio_cc_rx_mclk_clk_src.clkr,
688 };
689
690 static struct regmap_config lpass_audio_cc_sc7280_regmap_config = {
691 .reg_bits = 32,
692 .reg_stride = 4,
693 .val_bits = 32,
694 .fast_io = true,
695 };
696
697 static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
698 .config = &lpass_audio_cc_sc7280_regmap_config,
699 .clks = lpass_cc_sc7280_clocks,
700 .num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
701 .gdscs = lpass_aon_cc_sc7280_gdscs,
702 .num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
703 };
704
705 static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
706 .config = &lpass_audio_cc_sc7280_regmap_config,
707 .clks = lpass_audio_cc_sc7280_clocks,
708 .num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
709 };
710
711 static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
712 [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
713 [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
714 [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
715 };
716
717 static const struct regmap_config lpass_audio_cc_sc7280_reset_regmap_config = {
718 .name = "lpassaudio_cc_reset",
719 .reg_bits = 32,
720 .reg_stride = 4,
721 .val_bits = 32,
722 .fast_io = true,
723 .max_register = 0xc8,
724 };
725
726 static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
727 .config = &lpass_audio_cc_sc7280_reset_regmap_config,
728 .resets = lpass_audio_cc_sc7280_resets,
729 .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
730 };
731
732 static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
733 { .compatible = "qcom,qcm6490-lpassaudiocc", .data = &lpass_audio_cc_reset_sc7280_desc },
734 { .compatible = "qcom,sc7280-lpassaudiocc", .data = &lpass_audio_cc_sc7280_desc },
735 { }
736 };
737 MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table);
738
lpass_audio_setup_runtime_pm(struct platform_device * pdev)739 static int lpass_audio_setup_runtime_pm(struct platform_device *pdev)
740 {
741 int ret;
742
743 pm_runtime_use_autosuspend(&pdev->dev);
744 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
745 ret = devm_pm_runtime_enable(&pdev->dev);
746 if (ret)
747 return ret;
748
749 ret = devm_pm_clk_create(&pdev->dev);
750 if (ret)
751 return ret;
752
753 ret = pm_clk_add(&pdev->dev, "iface");
754 if (ret < 0)
755 dev_err(&pdev->dev, "failed to acquire iface clock\n");
756
757 return pm_runtime_resume_and_get(&pdev->dev);
758 }
759
lpass_audio_cc_sc7280_probe(struct platform_device * pdev)760 static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
761 {
762 const struct qcom_cc_desc *desc;
763 struct regmap *regmap;
764 int ret;
765
766 desc = device_get_match_data(&pdev->dev);
767
768 if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcm6490-lpassaudiocc"))
769 return qcom_cc_probe_by_index(pdev, 1, desc);
770
771 ret = lpass_audio_setup_runtime_pm(pdev);
772 if (ret)
773 return ret;
774
775 lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc";
776 lpass_audio_cc_sc7280_regmap_config.max_register = 0x2f000;
777
778 regmap = qcom_cc_map(pdev, desc);
779 if (IS_ERR(regmap)) {
780 ret = PTR_ERR(regmap);
781 goto exit;
782 }
783
784 clk_zonda_pll_configure(&lpass_audio_cc_pll, regmap, &lpass_audio_cc_pll_config);
785
786 /* PLL settings */
787 regmap_write(regmap, 0x4, 0x3b);
788 regmap_write(regmap, 0x8, 0xff05);
789
790 ret = qcom_cc_really_probe(&pdev->dev, desc, regmap);
791 if (ret) {
792 dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
793 goto exit;
794 }
795
796 ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
797 if (ret) {
798 dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
799 goto exit;
800 }
801
802 pm_runtime_mark_last_busy(&pdev->dev);
803 exit:
804 pm_runtime_put_autosuspend(&pdev->dev);
805
806 return ret;
807 }
808
809 static const struct dev_pm_ops lpass_audio_cc_pm_ops = {
810 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
811 };
812
813 static struct platform_driver lpass_audio_cc_sc7280_driver = {
814 .probe = lpass_audio_cc_sc7280_probe,
815 .driver = {
816 .name = "lpass_audio_cc-sc7280",
817 .of_match_table = lpass_audio_cc_sc7280_match_table,
818 .pm = &lpass_audio_cc_pm_ops,
819 },
820 };
821
822 static const struct qcom_cc_desc lpass_aon_cc_sc7280_desc = {
823 .config = &lpass_audio_cc_sc7280_regmap_config,
824 .clks = lpass_aon_cc_sc7280_clocks,
825 .num_clks = ARRAY_SIZE(lpass_aon_cc_sc7280_clocks),
826 .gdscs = lpass_aon_cc_sc7280_gdscs,
827 .num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
828 };
829
830 static const struct of_device_id lpass_aon_cc_sc7280_match_table[] = {
831 { .compatible = "qcom,sc7280-lpassaoncc" },
832 { }
833 };
834 MODULE_DEVICE_TABLE(of, lpass_aon_cc_sc7280_match_table);
835
lpass_aon_cc_sc7280_probe(struct platform_device * pdev)836 static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
837 {
838 const struct qcom_cc_desc *desc;
839 struct regmap *regmap;
840 int ret;
841
842 ret = lpass_audio_setup_runtime_pm(pdev);
843 if (ret)
844 return ret;
845
846 if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
847 lpass_audio_cc_sc7280_regmap_config.name = "cc";
848 desc = &lpass_cc_sc7280_desc;
849 ret = qcom_cc_probe(pdev, desc);
850 goto exit;
851 }
852
853 lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";
854 lpass_audio_cc_sc7280_regmap_config.max_register = 0xa0008;
855 desc = &lpass_aon_cc_sc7280_desc;
856
857 regmap = qcom_cc_map(pdev, desc);
858 if (IS_ERR(regmap)) {
859 ret = PTR_ERR(regmap);
860 goto exit;
861 }
862
863 clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config);
864
865 ret = qcom_cc_really_probe(&pdev->dev, &lpass_aon_cc_sc7280_desc, regmap);
866 if (ret) {
867 dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n");
868 goto exit;
869 }
870
871 pm_runtime_mark_last_busy(&pdev->dev);
872 exit:
873 pm_runtime_put_autosuspend(&pdev->dev);
874
875 return ret;
876 }
877
878 static struct platform_driver lpass_aon_cc_sc7280_driver = {
879 .probe = lpass_aon_cc_sc7280_probe,
880 .driver = {
881 .name = "lpass_aon_cc-sc7280",
882 .of_match_table = lpass_aon_cc_sc7280_match_table,
883 .pm = &lpass_audio_cc_pm_ops,
884 },
885 };
886
lpass_audio_cc_sc7280_init(void)887 static int __init lpass_audio_cc_sc7280_init(void)
888 {
889 int ret;
890
891 ret = platform_driver_register(&lpass_aon_cc_sc7280_driver);
892 if (ret)
893 return ret;
894
895 return platform_driver_register(&lpass_audio_cc_sc7280_driver);
896 }
897 subsys_initcall(lpass_audio_cc_sc7280_init);
898
lpass_audio_cc_sc7280_exit(void)899 static void __exit lpass_audio_cc_sc7280_exit(void)
900 {
901 platform_driver_unregister(&lpass_audio_cc_sc7280_driver);
902 platform_driver_unregister(&lpass_aon_cc_sc7280_driver);
903 }
904 module_exit(lpass_audio_cc_sc7280_exit);
905
906 MODULE_DESCRIPTION("QTI LPASS_AUDIO_CC SC7280 Driver");
907 MODULE_LICENSE("GPL v2");
908