1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Copyright (c) 2023 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/interconnect-clk.h>
8 #include <linux/interconnect-provider.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14
15 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
16 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
17 #include <dt-bindings/interconnect/qcom,ipq9574.h>
18
19 #include "clk-alpha-pll.h"
20 #include "clk-branch.h"
21 #include "clk-rcg.h"
22 #include "clk-regmap.h"
23 #include "clk-regmap-divider.h"
24 #include "clk-regmap-mux.h"
25 #include "clk-regmap-phy-mux.h"
26 #include "common.h"
27 #include "reset.h"
28
29 /* Need to match the order of clocks in DT binding */
30 enum {
31 DT_XO,
32 DT_SLEEP_CLK,
33 DT_BIAS_PLL_UBI_NC_CLK,
34 DT_PCIE30_PHY0_PIPE_CLK,
35 DT_PCIE30_PHY1_PIPE_CLK,
36 DT_PCIE30_PHY2_PIPE_CLK,
37 DT_PCIE30_PHY3_PIPE_CLK,
38 DT_USB3PHY_0_CC_PIPE_CLK,
39 };
40
41 enum {
42 P_XO,
43 P_PCIE30_PHY0_PIPE,
44 P_PCIE30_PHY1_PIPE,
45 P_PCIE30_PHY2_PIPE,
46 P_PCIE30_PHY3_PIPE,
47 P_USB3PHY_0_PIPE,
48 P_GPLL0,
49 P_GPLL0_DIV2,
50 P_GPLL0_OUT_AUX,
51 P_GPLL2,
52 P_GPLL4,
53 P_PI_SLEEP,
54 P_BIAS_PLL_UBI_NC_CLK,
55 };
56
57 static const struct parent_map gcc_xo_map[] = {
58 { P_XO, 0 },
59 };
60
61 static const struct clk_parent_data gcc_xo_data[] = {
62 { .index = DT_XO },
63 };
64
65 static const struct clk_parent_data gcc_sleep_clk_data[] = {
66 { .index = DT_SLEEP_CLK },
67 };
68
69 static struct clk_alpha_pll gpll0_main = {
70 .offset = 0x20000,
71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
72 .clkr = {
73 .enable_reg = 0x0b000,
74 .enable_mask = BIT(0),
75 .hw.init = &(const struct clk_init_data) {
76 .name = "gpll0_main",
77 .parent_data = gcc_xo_data,
78 .num_parents = ARRAY_SIZE(gcc_xo_data),
79 .ops = &clk_alpha_pll_ops,
80 },
81 },
82 };
83
84 static struct clk_fixed_factor gpll0_out_main_div2 = {
85 .mult = 1,
86 .div = 2,
87 .hw.init = &(const struct clk_init_data) {
88 .name = "gpll0_out_main_div2",
89 .parent_hws = (const struct clk_hw *[]) {
90 &gpll0_main.clkr.hw
91 },
92 .num_parents = 1,
93 .ops = &clk_fixed_factor_ops,
94 },
95 };
96
97 static struct clk_alpha_pll_postdiv gpll0 = {
98 .offset = 0x20000,
99 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
100 .width = 4,
101 .clkr.hw.init = &(const struct clk_init_data) {
102 .name = "gpll0",
103 .parent_hws = (const struct clk_hw *[]) {
104 &gpll0_main.clkr.hw
105 },
106 .num_parents = 1,
107 .ops = &clk_alpha_pll_postdiv_ro_ops,
108 },
109 };
110
111 static struct clk_alpha_pll_postdiv gpll0_out_aux = {
112 .offset = 0x20000,
113 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
114 .width = 4,
115 .clkr.hw.init = &(const struct clk_init_data) {
116 .name = "gpll0_out_aux",
117 .parent_hws = (const struct clk_hw *[]) {
118 &gpll0_main.clkr.hw
119 },
120 .num_parents = 1,
121 .ops = &clk_alpha_pll_postdiv_ro_ops,
122 },
123 };
124
125 static struct clk_alpha_pll gpll4_main = {
126 .offset = 0x22000,
127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
128 .clkr = {
129 .enable_reg = 0x0b000,
130 .enable_mask = BIT(2),
131 .hw.init = &(const struct clk_init_data) {
132 .name = "gpll4_main",
133 .parent_data = gcc_xo_data,
134 .num_parents = ARRAY_SIZE(gcc_xo_data),
135 .ops = &clk_alpha_pll_ops,
136 },
137 },
138 };
139
140 static struct clk_alpha_pll_postdiv gpll4 = {
141 .offset = 0x22000,
142 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
143 .width = 4,
144 .clkr.hw.init = &(const struct clk_init_data) {
145 .name = "gpll4",
146 .parent_hws = (const struct clk_hw *[]) {
147 &gpll4_main.clkr.hw
148 },
149 .num_parents = 1,
150 .ops = &clk_alpha_pll_postdiv_ro_ops,
151 },
152 };
153
154 static struct clk_alpha_pll gpll2_main = {
155 .offset = 0x21000,
156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
157 .clkr = {
158 .enable_reg = 0x0b000,
159 .enable_mask = BIT(1),
160 .hw.init = &(const struct clk_init_data) {
161 .name = "gpll2_main",
162 .parent_data = gcc_xo_data,
163 .num_parents = ARRAY_SIZE(gcc_xo_data),
164 .ops = &clk_alpha_pll_ops,
165 },
166 },
167 };
168
169 static struct clk_alpha_pll_postdiv gpll2 = {
170 .offset = 0x21000,
171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
172 .width = 4,
173 .clkr.hw.init = &(const struct clk_init_data) {
174 .name = "gpll2",
175 .parent_hws = (const struct clk_hw *[]) {
176 &gpll2_main.clkr.hw
177 },
178 .num_parents = 1,
179 .ops = &clk_alpha_pll_postdiv_ro_ops,
180 },
181 };
182
183 static struct clk_branch gcc_sleep_clk_src = {
184 .halt_reg = 0x3400c,
185 .clkr = {
186 .enable_reg = 0x3400c,
187 .enable_mask = BIT(1),
188 .hw.init = &(const struct clk_init_data) {
189 .name = "gcc_sleep_clk_src",
190 .parent_data = gcc_sleep_clk_data,
191 .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
192 .flags = CLK_IS_CRITICAL,
193 .ops = &clk_branch2_ops,
194 },
195 },
196 };
197
198 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
199 { .index = DT_XO },
200 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll0_out_main_div2.hw },
202 };
203
204 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
205 { P_XO, 0 },
206 { P_GPLL0, 1 },
207 { P_GPLL0_DIV2, 4 },
208 };
209
210 static const struct clk_parent_data gcc_xo_gpll0[] = {
211 { .index = DT_XO },
212 { .hw = &gpll0.clkr.hw },
213 };
214
215 static const struct parent_map gcc_xo_gpll0_map[] = {
216 { P_XO, 0 },
217 { P_GPLL0, 1 },
218 };
219
220 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
221 { .index = DT_XO },
222 { .hw = &gpll0.clkr.hw },
223 { .hw = &gpll4.clkr.hw },
224 };
225
226 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
227 { P_XO, 0 },
228 { P_GPLL0, 1 },
229 { P_GPLL4, 2 },
230 };
231
232 static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
233 { .index = DT_XO },
234 { .hw = &gpll0.clkr.hw },
235 { .hw = &gpll0_out_main_div2.hw },
236 { .hw = &gpll0.clkr.hw },
237 };
238
239 static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
240 { P_XO, 0 },
241 { P_GPLL0, 1 },
242 { P_GPLL0_DIV2, 4 },
243 { P_GPLL0, 5 },
244 };
245
246 static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
247 { .index = DT_XO },
248 { .hw = &gpll0.clkr.hw },
249 { .hw = &gpll0_out_main_div2.hw },
250 { .index = DT_SLEEP_CLK },
251 };
252
253 static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
254 { P_XO, 0 },
255 { P_GPLL0, 1 },
256 { P_GPLL0_DIV2, 4 },
257 { P_PI_SLEEP, 6 },
258 };
259
260 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
261 { .index = DT_XO },
262 { .hw = &gpll0.clkr.hw },
263 { .index = DT_SLEEP_CLK },
264 };
265
266 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
267 { P_XO, 0 },
268 { P_GPLL0, 2 },
269 { P_PI_SLEEP, 6 },
270 };
271
272 static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
273 { .index = DT_XO },
274 { .hw = &gpll0.clkr.hw },
275 { .hw = &gpll4.clkr.hw },
276 { .index = DT_BIAS_PLL_UBI_NC_CLK },
277 };
278
279 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
280 { P_XO, 0 },
281 { P_GPLL0, 1 },
282 { P_GPLL4, 2 },
283 { P_BIAS_PLL_UBI_NC_CLK, 3 },
284 };
285
286 static const struct clk_parent_data
287 gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
288 { .index = DT_XO },
289 { .hw = &gpll0.clkr.hw },
290 { .hw = &gpll0.clkr.hw },
291 { .index = DT_SLEEP_CLK },
292 };
293
294 static const struct parent_map
295 gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
296 { P_XO, 0 },
297 { P_GPLL0, 1 },
298 { P_GPLL0_OUT_AUX, 2 },
299 { P_PI_SLEEP, 6 },
300 };
301
302 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
303 { .index = DT_XO },
304 { .hw = &gpll0.clkr.hw },
305 { .hw = &gpll0_out_main_div2.hw },
306 };
307
308 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
309 { P_XO, 0 },
310 { P_GPLL0, 1 },
311 { P_GPLL0_DIV2, 4 },
312 };
313
314 static const struct clk_parent_data
315 gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
316 { .index = DT_XO },
317 { .hw = &gpll4.clkr.hw },
318 { .hw = &gpll0.clkr.hw },
319 { .hw = &gpll0_out_main_div2.hw },
320 };
321
322 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
323 { P_XO, 0 },
324 { P_GPLL4, 1 },
325 { P_GPLL0, 3 },
326 { P_GPLL0_DIV2, 4 },
327 };
328
329 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
330 { .index = DT_USB3PHY_0_CC_PIPE_CLK },
331 { .index = DT_XO },
332 };
333
334 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
335 { P_USB3PHY_0_PIPE, 0 },
336 { P_XO, 2 },
337 };
338
339 static const struct clk_parent_data
340 gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
341 { .index = DT_XO },
342 { .hw = &gpll0.clkr.hw },
343 { .hw = &gpll2.clkr.hw },
344 { .hw = &gpll0_out_main_div2.hw },
345 };
346
347 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
348 { P_XO, 0 },
349 { P_GPLL0, 1 },
350 { P_GPLL2, 2 },
351 { P_GPLL0_DIV2, 4 },
352 };
353
354 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
355 { .index = DT_XO},
356 { .hw = &gpll0.clkr.hw },
357 { .hw = &gpll4.clkr.hw },
358 { .hw = &gpll0_out_main_div2.hw },
359 };
360
361 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
362 { P_XO, 0 },
363 { P_GPLL0, 1 },
364 { P_GPLL4, 2 },
365 { P_GPLL0_DIV2, 4 },
366 };
367
368 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
369 { .index = DT_XO },
370 { .hw = &gpll4.clkr.hw },
371 { .hw = &gpll0.clkr.hw },
372 { .hw = &gpll0_out_main_div2.hw },
373 };
374
375 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
376 { P_XO, 0 },
377 { P_GPLL4, 1 },
378 { P_GPLL0, 2 },
379 { P_GPLL0_DIV2, 4 },
380 };
381
382 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
383 { .index = DT_XO },
384 { .hw = &gpll0.clkr.hw },
385 { .hw = &gpll2.clkr.hw },
386 };
387
388 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
389 { P_XO, 0 },
390 { P_GPLL0, 1 },
391 { P_GPLL2, 2 },
392 };
393
394 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
395 { .index = DT_XO },
396 { .hw = &gpll0.clkr.hw },
397 { .hw = &gpll2.clkr.hw },
398 { .hw = &gpll4.clkr.hw },
399 { .index = DT_SLEEP_CLK },
400 };
401
402 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
403 { P_XO, 0 },
404 { P_GPLL0, 1 },
405 { P_GPLL2, 2 },
406 { P_GPLL4, 3 },
407 { P_PI_SLEEP, 6 },
408 };
409
410 static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
411 { .index = DT_XO },
412 { .hw = &gpll0.clkr.hw },
413 { .hw = &gpll0.clkr.hw },
414 { .hw = &gpll2.clkr.hw },
415 };
416
417 static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
418 { P_XO, 0 },
419 { P_GPLL0, 1 },
420 { P_GPLL0_OUT_AUX, 2 },
421 { P_GPLL2, 3 },
422 };
423
424 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
425 F(24000000, P_XO, 1, 0, 0),
426 F(50000000, P_GPLL0, 16, 0, 0),
427 F(100000000, P_GPLL0, 8, 0, 0),
428 { }
429 };
430
431 static struct clk_rcg2 apss_ahb_clk_src = {
432 .cmd_rcgr = 0x2400c,
433 .freq_tbl = ftbl_apss_ahb_clk_src,
434 .hid_width = 5,
435 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
436 .clkr.hw.init = &(const struct clk_init_data) {
437 .name = "apss_ahb_clk_src",
438 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
439 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
440 .ops = &clk_rcg2_ops,
441 },
442 };
443
444 static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
445 F(533000000, P_GPLL0, 1.5, 0, 0),
446 { }
447 };
448
449 static struct clk_rcg2 apss_axi_clk_src = {
450 .cmd_rcgr = 0x24004,
451 .freq_tbl = ftbl_apss_axi_clk_src,
452 .hid_width = 5,
453 .parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
454 .clkr.hw.init = &(const struct clk_init_data) {
455 .name = "apss_axi_clk_src",
456 .parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
457 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
458 .ops = &clk_rcg2_ops,
459 },
460 };
461
462 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
463 F(9600000, P_XO, 2.5, 0, 0),
464 F(24000000, P_XO, 1, 0, 0),
465 F(50000000, P_GPLL0, 16, 0, 0),
466 { }
467 };
468
469 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
470 .cmd_rcgr = 0x02018,
471 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
472 .hid_width = 5,
473 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
474 .clkr.hw.init = &(const struct clk_init_data) {
475 .name = "blsp1_qup1_i2c_apps_clk_src",
476 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
477 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
478 .ops = &clk_rcg2_ops,
479 },
480 };
481
482 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
483 F(960000, P_XO, 10, 2, 5),
484 F(4800000, P_XO, 5, 0, 0),
485 F(9600000, P_XO, 2, 4, 5),
486 F(16000000, P_GPLL0, 10, 1, 5),
487 F(24000000, P_XO, 1, 0, 0),
488 F(25000000, P_GPLL0, 16, 1, 2),
489 F(50000000, P_GPLL0, 16, 0, 0),
490 { }
491 };
492
493 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
494 .cmd_rcgr = 0x02004,
495 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
496 .mnd_width = 8,
497 .hid_width = 5,
498 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
499 .clkr.hw.init = &(const struct clk_init_data) {
500 .name = "blsp1_qup1_spi_apps_clk_src",
501 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
502 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
503 .ops = &clk_rcg2_ops,
504 },
505 };
506
507 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
508 .cmd_rcgr = 0x03018,
509 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
510 .hid_width = 5,
511 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
512 .clkr.hw.init = &(const struct clk_init_data) {
513 .name = "blsp1_qup2_i2c_apps_clk_src",
514 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
515 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
516 .ops = &clk_rcg2_ops,
517 },
518 };
519
520 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
521 .cmd_rcgr = 0x03004,
522 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
523 .mnd_width = 8,
524 .hid_width = 5,
525 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
526 .clkr.hw.init = &(const struct clk_init_data) {
527 .name = "blsp1_qup2_spi_apps_clk_src",
528 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
529 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
530 .ops = &clk_rcg2_ops,
531 },
532 };
533
534 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
535 .cmd_rcgr = 0x04018,
536 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
537 .hid_width = 5,
538 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
539 .clkr.hw.init = &(const struct clk_init_data) {
540 .name = "blsp1_qup3_i2c_apps_clk_src",
541 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
542 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
543 .ops = &clk_rcg2_ops,
544 },
545 };
546
547 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
548 .cmd_rcgr = 0x04004,
549 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
550 .mnd_width = 8,
551 .hid_width = 5,
552 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
553 .clkr.hw.init = &(const struct clk_init_data) {
554 .name = "blsp1_qup3_spi_apps_clk_src",
555 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
556 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
557 .ops = &clk_rcg2_ops,
558 },
559 };
560
561 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
562 .cmd_rcgr = 0x05018,
563 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
564 .hid_width = 5,
565 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
566 .clkr.hw.init = &(const struct clk_init_data) {
567 .name = "blsp1_qup4_i2c_apps_clk_src",
568 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
569 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
570 .ops = &clk_rcg2_ops,
571 },
572 };
573
574 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
575 .cmd_rcgr = 0x05004,
576 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
577 .mnd_width = 8,
578 .hid_width = 5,
579 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
580 .clkr.hw.init = &(const struct clk_init_data) {
581 .name = "blsp1_qup4_spi_apps_clk_src",
582 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
583 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
584 .ops = &clk_rcg2_ops,
585 },
586 };
587
588 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
589 .cmd_rcgr = 0x06018,
590 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
591 .hid_width = 5,
592 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
593 .clkr.hw.init = &(const struct clk_init_data) {
594 .name = "blsp1_qup5_i2c_apps_clk_src",
595 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
596 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
597 .ops = &clk_rcg2_ops,
598 },
599 };
600
601 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
602 .cmd_rcgr = 0x06004,
603 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
604 .mnd_width = 8,
605 .hid_width = 5,
606 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
607 .clkr.hw.init = &(const struct clk_init_data) {
608 .name = "blsp1_qup5_spi_apps_clk_src",
609 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
610 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
611 .ops = &clk_rcg2_ops,
612 },
613 };
614
615 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
616 .cmd_rcgr = 0x07018,
617 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
618 .hid_width = 5,
619 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
620 .clkr.hw.init = &(const struct clk_init_data) {
621 .name = "blsp1_qup6_i2c_apps_clk_src",
622 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
623 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
624 .ops = &clk_rcg2_ops,
625 },
626 };
627
628 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
629 .cmd_rcgr = 0x07004,
630 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
631 .mnd_width = 8,
632 .hid_width = 5,
633 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
634 .clkr.hw.init = &(const struct clk_init_data) {
635 .name = "blsp1_qup6_spi_apps_clk_src",
636 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
637 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
638 .ops = &clk_rcg2_ops,
639 },
640 };
641
642 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
643 F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
644 F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
645 F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
646 F(24000000, P_XO, 1, 0, 0),
647 F(25000000, P_GPLL0, 16, 1, 2),
648 F(32000000, P_GPLL0, 1, 1, 25),
649 F(40000000, P_GPLL0, 1, 1, 20),
650 F(46400000, P_GPLL0, 1, 29, 500),
651 F(48000000, P_GPLL0, 1, 3, 50),
652 F(51200000, P_GPLL0, 1, 8, 125),
653 F(56000000, P_GPLL0, 1, 7, 100),
654 F(58982400, P_GPLL0, 1, 1152, 15625),
655 F(60000000, P_GPLL0, 1, 3, 40),
656 F(64000000, P_GPLL0, 12.5, 0, 0),
657 { }
658 };
659
660 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
661 .cmd_rcgr = 0x0202c,
662 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
663 .mnd_width = 16,
664 .hid_width = 5,
665 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
666 .clkr.hw.init = &(const struct clk_init_data) {
667 .name = "blsp1_uart1_apps_clk_src",
668 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
669 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
670 .ops = &clk_rcg2_ops,
671 },
672 };
673
674 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
675 .cmd_rcgr = 0x0302c,
676 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
677 .mnd_width = 16,
678 .hid_width = 5,
679 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
680 .clkr.hw.init = &(const struct clk_init_data) {
681 .name = "blsp1_uart2_apps_clk_src",
682 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
683 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
684 .ops = &clk_rcg2_ops,
685 },
686 };
687
688 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
689 .cmd_rcgr = 0x0402c,
690 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
691 .mnd_width = 16,
692 .hid_width = 5,
693 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
694 .clkr.hw.init = &(const struct clk_init_data) {
695 .name = "blsp1_uart3_apps_clk_src",
696 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
697 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
698 .ops = &clk_rcg2_ops,
699 },
700 };
701
702 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
703 .cmd_rcgr = 0x0502c,
704 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
705 .mnd_width = 16,
706 .hid_width = 5,
707 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
708 .clkr.hw.init = &(const struct clk_init_data) {
709 .name = "blsp1_uart4_apps_clk_src",
710 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
711 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
712 .ops = &clk_rcg2_ops,
713 },
714 };
715
716 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
717 .cmd_rcgr = 0x0602c,
718 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
719 .mnd_width = 16,
720 .hid_width = 5,
721 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
722 .clkr.hw.init = &(const struct clk_init_data) {
723 .name = "blsp1_uart5_apps_clk_src",
724 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
725 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
726 .ops = &clk_rcg2_ops,
727 },
728 };
729
730 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
731 .cmd_rcgr = 0x0702c,
732 .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
733 .mnd_width = 16,
734 .hid_width = 5,
735 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
736 .clkr.hw.init = &(const struct clk_init_data) {
737 .name = "blsp1_uart6_apps_clk_src",
738 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
739 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
740 .ops = &clk_rcg2_ops,
741 },
742 };
743
744 static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
745 F(160000000, P_GPLL0, 5, 0, 0),
746 { }
747 };
748
749 static struct clk_rcg2 gcc_crypto_clk_src = {
750 .cmd_rcgr = 0x16004,
751 .freq_tbl = ftbl_gcc_crypto_clk_src,
752 .hid_width = 5,
753 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
754 .clkr.hw.init = &(const struct clk_init_data) {
755 .name = "gcc_crypto_clk_src",
756 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
757 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
758 .ops = &clk_rcg2_ops,
759 },
760 };
761
762 static struct clk_branch gcc_crypto_clk = {
763 .halt_reg = 0x1600c,
764 .halt_check = BRANCH_HALT_VOTED,
765 .clkr = {
766 .enable_reg = 0x0b004,
767 .enable_mask = BIT(14),
768 .hw.init = &(const struct clk_init_data) {
769 .name = "gcc_crypto_clk",
770 .parent_hws = (const struct clk_hw *[]) {
771 &gcc_crypto_clk_src.clkr.hw },
772 .num_parents = 1,
773 .flags = CLK_SET_RATE_PARENT,
774 .ops = &clk_branch2_ops,
775 },
776 },
777 };
778
779 static struct clk_branch gcc_apss_ahb_clk = {
780 .halt_reg = 0x24018,
781 .halt_check = BRANCH_HALT_VOTED,
782 .clkr = {
783 .enable_reg = 0x0b004,
784 .enable_mask = BIT(0),
785 .hw.init = &(const struct clk_init_data) {
786 .name = "gcc_apss_ahb_clk",
787 .parent_hws = (const struct clk_hw *[]) {
788 &apss_ahb_clk_src.clkr.hw
789 },
790 .num_parents = 1,
791 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
792 .ops = &clk_branch2_ops,
793 },
794 },
795 };
796
797 static struct clk_branch gcc_apss_axi_clk = {
798 .halt_reg = 0x2401c,
799 .halt_check = BRANCH_HALT_VOTED,
800 .clkr = {
801 .enable_reg = 0x0b004,
802 .enable_mask = BIT(1),
803 .hw.init = &(const struct clk_init_data) {
804 .name = "gcc_apss_axi_clk",
805 .parent_hws = (const struct clk_hw *[]) {
806 &apss_axi_clk_src.clkr.hw
807 },
808 .num_parents = 1,
809 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
810 .ops = &clk_branch2_ops,
811 },
812 },
813 };
814
815 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
816 .halt_reg = 0x2024,
817 .clkr = {
818 .enable_reg = 0x2024,
819 .enable_mask = BIT(0),
820 .hw.init = &(const struct clk_init_data) {
821 .name = "gcc_blsp1_qup1_i2c_apps_clk",
822 .parent_hws = (const struct clk_hw *[]) {
823 &blsp1_qup1_i2c_apps_clk_src.clkr.hw
824 },
825 .num_parents = 1,
826 .flags = CLK_SET_RATE_PARENT,
827 .ops = &clk_branch2_ops,
828 },
829 },
830 };
831
832 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
833 .halt_reg = 0x02020,
834 .clkr = {
835 .enable_reg = 0x02020,
836 .enable_mask = BIT(0),
837 .hw.init = &(const struct clk_init_data) {
838 .name = "gcc_blsp1_qup1_spi_apps_clk",
839 .parent_hws = (const struct clk_hw *[]) {
840 &blsp1_qup1_spi_apps_clk_src.clkr.hw
841 },
842 .num_parents = 1,
843 .flags = CLK_SET_RATE_PARENT,
844 .ops = &clk_branch2_ops,
845 },
846 },
847 };
848
849 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
850 .halt_reg = 0x03024,
851 .clkr = {
852 .enable_reg = 0x03024,
853 .enable_mask = BIT(0),
854 .hw.init = &(const struct clk_init_data) {
855 .name = "gcc_blsp1_qup2_i2c_apps_clk",
856 .parent_hws = (const struct clk_hw *[]) {
857 &blsp1_qup2_i2c_apps_clk_src.clkr.hw
858 },
859 .num_parents = 1,
860 .flags = CLK_SET_RATE_PARENT,
861 .ops = &clk_branch2_ops,
862 },
863 },
864 };
865
866 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
867 .halt_reg = 0x03020,
868 .clkr = {
869 .enable_reg = 0x03020,
870 .enable_mask = BIT(0),
871 .hw.init = &(const struct clk_init_data) {
872 .name = "gcc_blsp1_qup2_spi_apps_clk",
873 .parent_hws = (const struct clk_hw *[]) {
874 &blsp1_qup2_spi_apps_clk_src.clkr.hw
875 },
876 .num_parents = 1,
877 .flags = CLK_SET_RATE_PARENT,
878 .ops = &clk_branch2_ops,
879 },
880 },
881 };
882
883 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
884 .halt_reg = 0x04024,
885 .clkr = {
886 .enable_reg = 0x04024,
887 .enable_mask = BIT(0),
888 .hw.init = &(const struct clk_init_data) {
889 .name = "gcc_blsp1_qup3_i2c_apps_clk",
890 .parent_hws = (const struct clk_hw *[]) {
891 &blsp1_qup3_i2c_apps_clk_src.clkr.hw
892 },
893 .num_parents = 1,
894 .flags = CLK_SET_RATE_PARENT,
895 .ops = &clk_branch2_ops,
896 },
897 },
898 };
899
900 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
901 .halt_reg = 0x04020,
902 .clkr = {
903 .enable_reg = 0x04020,
904 .enable_mask = BIT(0),
905 .hw.init = &(const struct clk_init_data) {
906 .name = "gcc_blsp1_qup3_spi_apps_clk",
907 .parent_hws = (const struct clk_hw *[]) {
908 &blsp1_qup3_spi_apps_clk_src.clkr.hw
909 },
910 .num_parents = 1,
911 .flags = CLK_SET_RATE_PARENT,
912 .ops = &clk_branch2_ops,
913 },
914 },
915 };
916
917 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
918 .halt_reg = 0x05024,
919 .clkr = {
920 .enable_reg = 0x05024,
921 .enable_mask = BIT(0),
922 .hw.init = &(const struct clk_init_data) {
923 .name = "gcc_blsp1_qup4_i2c_apps_clk",
924 .parent_hws = (const struct clk_hw *[]) {
925 &blsp1_qup4_i2c_apps_clk_src.clkr.hw
926 },
927 .num_parents = 1,
928 .flags = CLK_SET_RATE_PARENT,
929 .ops = &clk_branch2_ops,
930 },
931 },
932 };
933
934 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
935 .halt_reg = 0x05020,
936 .clkr = {
937 .enable_reg = 0x05020,
938 .enable_mask = BIT(0),
939 .hw.init = &(const struct clk_init_data) {
940 .name = "gcc_blsp1_qup4_spi_apps_clk",
941 .parent_hws = (const struct clk_hw *[]) {
942 &blsp1_qup4_spi_apps_clk_src.clkr.hw
943 },
944 .num_parents = 1,
945 .flags = CLK_SET_RATE_PARENT,
946 .ops = &clk_branch2_ops,
947 },
948 },
949 };
950
951 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
952 .halt_reg = 0x06024,
953 .clkr = {
954 .enable_reg = 0x06024,
955 .enable_mask = BIT(0),
956 .hw.init = &(const struct clk_init_data) {
957 .name = "gcc_blsp1_qup5_i2c_apps_clk",
958 .parent_hws = (const struct clk_hw *[]) {
959 &blsp1_qup5_i2c_apps_clk_src.clkr.hw
960 },
961 .num_parents = 1,
962 .flags = CLK_SET_RATE_PARENT,
963 .ops = &clk_branch2_ops,
964 },
965 },
966 };
967
968 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
969 .halt_reg = 0x06020,
970 .clkr = {
971 .enable_reg = 0x06020,
972 .enable_mask = BIT(0),
973 .hw.init = &(const struct clk_init_data) {
974 .name = "gcc_blsp1_qup5_spi_apps_clk",
975 .parent_hws = (const struct clk_hw *[]) {
976 &blsp1_qup5_spi_apps_clk_src.clkr.hw
977 },
978 .num_parents = 1,
979 .flags = CLK_SET_RATE_PARENT,
980 .ops = &clk_branch2_ops,
981 },
982 },
983 };
984
985 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
986 .halt_reg = 0x07024,
987 .clkr = {
988 .enable_reg = 0x07024,
989 .enable_mask = BIT(0),
990 .hw.init = &(const struct clk_init_data) {
991 .name = "gcc_blsp1_qup6_i2c_apps_clk",
992 .parent_hws = (const struct clk_hw *[]) {
993 &blsp1_qup6_i2c_apps_clk_src.clkr.hw
994 },
995 .num_parents = 1,
996 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
997 .ops = &clk_branch2_ops,
998 },
999 },
1000 };
1001
1002 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1003 .halt_reg = 0x07020,
1004 .clkr = {
1005 .enable_reg = 0x07020,
1006 .enable_mask = BIT(0),
1007 .hw.init = &(const struct clk_init_data) {
1008 .name = "gcc_blsp1_qup6_spi_apps_clk",
1009 .parent_hws = (const struct clk_hw *[]) {
1010 &blsp1_qup6_spi_apps_clk_src.clkr.hw
1011 },
1012 .num_parents = 1,
1013 .flags = CLK_SET_RATE_PARENT,
1014 .ops = &clk_branch2_ops,
1015 },
1016 },
1017 };
1018
1019 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1020 .halt_reg = 0x02040,
1021 .clkr = {
1022 .enable_reg = 0x02040,
1023 .enable_mask = BIT(0),
1024 .hw.init = &(const struct clk_init_data) {
1025 .name = "gcc_blsp1_uart1_apps_clk",
1026 .parent_hws = (const struct clk_hw *[]) {
1027 &blsp1_uart1_apps_clk_src.clkr.hw
1028 },
1029 .num_parents = 1,
1030 .flags = CLK_SET_RATE_PARENT,
1031 .ops = &clk_branch2_ops,
1032 },
1033 },
1034 };
1035
1036 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1037 .halt_reg = 0x03040,
1038 .clkr = {
1039 .enable_reg = 0x03040,
1040 .enable_mask = BIT(0),
1041 .hw.init = &(const struct clk_init_data) {
1042 .name = "gcc_blsp1_uart2_apps_clk",
1043 .parent_hws = (const struct clk_hw *[]) {
1044 &blsp1_uart2_apps_clk_src.clkr.hw
1045 },
1046 .num_parents = 1,
1047 .flags = CLK_SET_RATE_PARENT,
1048 .ops = &clk_branch2_ops,
1049 },
1050 },
1051 };
1052
1053 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1054 .halt_reg = 0x04054,
1055 .clkr = {
1056 .enable_reg = 0x04054,
1057 .enable_mask = BIT(0),
1058 .hw.init = &(const struct clk_init_data) {
1059 .name = "gcc_blsp1_uart3_apps_clk",
1060 .parent_hws = (const struct clk_hw *[]) {
1061 &blsp1_uart3_apps_clk_src.clkr.hw
1062 },
1063 .num_parents = 1,
1064 .flags = CLK_SET_RATE_PARENT,
1065 .ops = &clk_branch2_ops,
1066 },
1067 },
1068 };
1069
1070 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1071 .halt_reg = 0x05040,
1072 .clkr = {
1073 .enable_reg = 0x05040,
1074 .enable_mask = BIT(0),
1075 .hw.init = &(const struct clk_init_data) {
1076 .name = "gcc_blsp1_uart4_apps_clk",
1077 .parent_hws = (const struct clk_hw *[]) {
1078 &blsp1_uart4_apps_clk_src.clkr.hw
1079 },
1080 .num_parents = 1,
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_branch2_ops,
1083 },
1084 },
1085 };
1086
1087 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1088 .halt_reg = 0x06040,
1089 .clkr = {
1090 .enable_reg = 0x06040,
1091 .enable_mask = BIT(0),
1092 .hw.init = &(const struct clk_init_data) {
1093 .name = "gcc_blsp1_uart5_apps_clk",
1094 .parent_hws = (const struct clk_hw *[]) {
1095 &blsp1_uart5_apps_clk_src.clkr.hw
1096 },
1097 .num_parents = 1,
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_branch2_ops,
1100 },
1101 },
1102 };
1103
1104 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1105 .halt_reg = 0x07040,
1106 .clkr = {
1107 .enable_reg = 0x07040,
1108 .enable_mask = BIT(0),
1109 .hw.init = &(const struct clk_init_data) {
1110 .name = "gcc_blsp1_uart6_apps_clk",
1111 .parent_hws = (const struct clk_hw *[]) {
1112 &blsp1_uart6_apps_clk_src.clkr.hw
1113 },
1114 .num_parents = 1,
1115 .flags = CLK_SET_RATE_PARENT,
1116 .ops = &clk_branch2_ops,
1117 },
1118 },
1119 };
1120
1121 static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
1122 F(240000000, P_GPLL4, 5, 0, 0),
1123 { }
1124 };
1125
1126 static struct clk_rcg2 pcie0_axi_m_clk_src = {
1127 .cmd_rcgr = 0x28018,
1128 .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1129 .hid_width = 5,
1130 .parent_map = gcc_xo_gpll0_gpll4_map,
1131 .clkr.hw.init = &(const struct clk_init_data) {
1132 .name = "pcie0_axi_m_clk_src",
1133 .parent_data = gcc_xo_gpll0_gpll4,
1134 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1135 .ops = &clk_rcg2_ops,
1136 },
1137 };
1138
1139 static struct clk_branch gcc_pcie0_axi_m_clk = {
1140 .halt_reg = 0x28038,
1141 .clkr = {
1142 .enable_reg = 0x28038,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(const struct clk_init_data) {
1145 .name = "gcc_pcie0_axi_m_clk",
1146 .parent_hws = (const struct clk_hw *[]) {
1147 &pcie0_axi_m_clk_src.clkr.hw
1148 },
1149 .num_parents = 1,
1150 .flags = CLK_SET_RATE_PARENT,
1151 .ops = &clk_branch2_ops,
1152 },
1153 },
1154 };
1155
1156 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1157 .halt_reg = 0x2e07c,
1158 .clkr = {
1159 .enable_reg = 0x2e07c,
1160 .enable_mask = BIT(0),
1161 .hw.init = &(const struct clk_init_data) {
1162 .name = "gcc_anoc_pcie0_1lane_m_clk",
1163 .parent_hws = (const struct clk_hw *[]) {
1164 &pcie0_axi_m_clk_src.clkr.hw
1165 },
1166 .num_parents = 1,
1167 .flags = CLK_SET_RATE_PARENT,
1168 .ops = &clk_branch2_ops,
1169 },
1170 },
1171 };
1172
1173 static struct clk_rcg2 pcie1_axi_m_clk_src = {
1174 .cmd_rcgr = 0x29018,
1175 .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1176 .hid_width = 5,
1177 .parent_map = gcc_xo_gpll0_gpll4_map,
1178 .clkr.hw.init = &(const struct clk_init_data) {
1179 .name = "pcie1_axi_m_clk_src",
1180 .parent_data = gcc_xo_gpll0_gpll4,
1181 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1182 .ops = &clk_rcg2_ops,
1183 },
1184 };
1185
1186 static struct clk_branch gcc_pcie1_axi_m_clk = {
1187 .halt_reg = 0x29038,
1188 .clkr = {
1189 .enable_reg = 0x29038,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(const struct clk_init_data) {
1192 .name = "gcc_pcie1_axi_m_clk",
1193 .parent_hws = (const struct clk_hw *[]) {
1194 &pcie1_axi_m_clk_src.clkr.hw
1195 },
1196 .num_parents = 1,
1197 .flags = CLK_SET_RATE_PARENT,
1198 .ops = &clk_branch2_ops,
1199 },
1200 },
1201 };
1202
1203 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1204 .halt_reg = 0x2e08c,
1205 .clkr = {
1206 .enable_reg = 0x2e08c,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(const struct clk_init_data) {
1209 .name = "gcc_anoc_pcie1_1lane_m_clk",
1210 .parent_hws = (const struct clk_hw *[]) {
1211 &pcie1_axi_m_clk_src.clkr.hw
1212 },
1213 .num_parents = 1,
1214 .flags = CLK_SET_RATE_PARENT,
1215 .ops = &clk_branch2_ops,
1216 },
1217 },
1218 };
1219
1220 static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
1221 F(342857143, P_GPLL4, 3.5, 0, 0),
1222 { }
1223 };
1224
1225 static struct clk_rcg2 pcie2_axi_m_clk_src = {
1226 .cmd_rcgr = 0x2a018,
1227 .freq_tbl = ftbl_pcie2_axi_m_clk_src,
1228 .hid_width = 5,
1229 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1230 .clkr.hw.init = &(const struct clk_init_data) {
1231 .name = "pcie2_axi_m_clk_src",
1232 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1233 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1234 .ops = &clk_rcg2_ops,
1235 },
1236 };
1237
1238 static struct clk_branch gcc_pcie2_axi_m_clk = {
1239 .halt_reg = 0x2a038,
1240 .clkr = {
1241 .enable_reg = 0x2a038,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(const struct clk_init_data) {
1244 .name = "gcc_pcie2_axi_m_clk",
1245 .parent_hws = (const struct clk_hw *[]) {
1246 &pcie2_axi_m_clk_src.clkr.hw
1247 },
1248 .num_parents = 1,
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1251 },
1252 },
1253 };
1254
1255 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1256 .halt_reg = 0x2e080,
1257 .clkr = {
1258 .enable_reg = 0x2e080,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(const struct clk_init_data) {
1261 .name = "gcc_anoc_pcie2_2lane_m_clk",
1262 .parent_hws = (const struct clk_hw *[]) {
1263 &pcie2_axi_m_clk_src.clkr.hw
1264 },
1265 .num_parents = 1,
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1268 },
1269 },
1270 };
1271
1272 static struct clk_rcg2 pcie3_axi_m_clk_src = {
1273 .cmd_rcgr = 0x2b018,
1274 .freq_tbl = ftbl_pcie2_axi_m_clk_src,
1275 .hid_width = 5,
1276 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1277 .clkr.hw.init = &(const struct clk_init_data) {
1278 .name = "pcie3_axi_m_clk_src",
1279 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1280 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1281 .ops = &clk_rcg2_ops,
1282 },
1283 };
1284
1285 static struct clk_branch gcc_pcie3_axi_m_clk = {
1286 .halt_reg = 0x2b038,
1287 .clkr = {
1288 .enable_reg = 0x2b038,
1289 .enable_mask = BIT(0),
1290 .hw.init = &(const struct clk_init_data) {
1291 .name = "gcc_pcie3_axi_m_clk",
1292 .parent_hws = (const struct clk_hw *[]) {
1293 &pcie3_axi_m_clk_src.clkr.hw
1294 },
1295 .num_parents = 1,
1296 .flags = CLK_SET_RATE_PARENT,
1297 .ops = &clk_branch2_ops,
1298 },
1299 },
1300 };
1301
1302 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1303 .halt_reg = 0x2e090,
1304 .clkr = {
1305 .enable_reg = 0x2e090,
1306 .enable_mask = BIT(0),
1307 .hw.init = &(const struct clk_init_data) {
1308 .name = "gcc_anoc_pcie3_2lane_m_clk",
1309 .parent_hws = (const struct clk_hw *[]) {
1310 &pcie3_axi_m_clk_src.clkr.hw
1311 },
1312 .num_parents = 1,
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_branch2_ops,
1315 },
1316 },
1317 };
1318
1319 static struct clk_rcg2 pcie0_axi_s_clk_src = {
1320 .cmd_rcgr = 0x28020,
1321 .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1322 .hid_width = 5,
1323 .parent_map = gcc_xo_gpll0_gpll4_map,
1324 .clkr.hw.init = &(const struct clk_init_data) {
1325 .name = "pcie0_axi_s_clk_src",
1326 .parent_data = gcc_xo_gpll0_gpll4,
1327 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1328 .ops = &clk_rcg2_ops,
1329 },
1330 };
1331
1332 static struct clk_branch gcc_pcie0_axi_s_clk = {
1333 .halt_reg = 0x2803c,
1334 .clkr = {
1335 .enable_reg = 0x2803c,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(const struct clk_init_data) {
1338 .name = "gcc_pcie0_axi_s_clk",
1339 .parent_hws = (const struct clk_hw *[]) {
1340 &pcie0_axi_s_clk_src.clkr.hw
1341 },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347 };
1348
1349 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1350 .halt_reg = 0x28040,
1351 .clkr = {
1352 .enable_reg = 0x28040,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(const struct clk_init_data) {
1355 .name = "gcc_pcie0_axi_s_bridge_clk",
1356 .parent_hws = (const struct clk_hw *[]) {
1357 &pcie0_axi_s_clk_src.clkr.hw
1358 },
1359 .num_parents = 1,
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1362 },
1363 },
1364 };
1365
1366 static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
1367 .halt_reg = 0x2e048,
1368 .clkr = {
1369 .enable_reg = 0x2e048,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(const struct clk_init_data) {
1372 .name = "gcc_snoc_pcie0_1lane_s_clk",
1373 .parent_hws = (const struct clk_hw *[]) {
1374 &pcie0_axi_s_clk_src.clkr.hw
1375 },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT,
1378 .ops = &clk_branch2_ops,
1379 },
1380 },
1381 };
1382
1383 static struct clk_rcg2 pcie1_axi_s_clk_src = {
1384 .cmd_rcgr = 0x29020,
1385 .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1386 .hid_width = 5,
1387 .parent_map = gcc_xo_gpll0_gpll4_map,
1388 .clkr.hw.init = &(const struct clk_init_data) {
1389 .name = "pcie1_axi_s_clk_src",
1390 .parent_data = gcc_xo_gpll0_gpll4,
1391 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1392 .ops = &clk_rcg2_ops,
1393 },
1394 };
1395
1396 static struct clk_branch gcc_pcie1_axi_s_clk = {
1397 .halt_reg = 0x2903c,
1398 .clkr = {
1399 .enable_reg = 0x2903c,
1400 .enable_mask = BIT(0),
1401 .hw.init = &(const struct clk_init_data) {
1402 .name = "gcc_pcie1_axi_s_clk",
1403 .parent_hws = (const struct clk_hw *[]) {
1404 &pcie1_axi_s_clk_src.clkr.hw
1405 },
1406 .num_parents = 1,
1407 .flags = CLK_SET_RATE_PARENT,
1408 .ops = &clk_branch2_ops,
1409 },
1410 },
1411 };
1412
1413 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1414 .halt_reg = 0x29040,
1415 .clkr = {
1416 .enable_reg = 0x29040,
1417 .enable_mask = BIT(0),
1418 .hw.init = &(const struct clk_init_data) {
1419 .name = "gcc_pcie1_axi_s_bridge_clk",
1420 .parent_hws = (const struct clk_hw *[]) {
1421 &pcie1_axi_s_clk_src.clkr.hw
1422 },
1423 .num_parents = 1,
1424 .flags = CLK_SET_RATE_PARENT,
1425 .ops = &clk_branch2_ops,
1426 },
1427 },
1428 };
1429
1430 static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
1431 .halt_reg = 0x2e04c,
1432 .clkr = {
1433 .enable_reg = 0x2e04c,
1434 .enable_mask = BIT(0),
1435 .hw.init = &(const struct clk_init_data) {
1436 .name = "gcc_snoc_pcie1_1lane_s_clk",
1437 .parent_hws = (const struct clk_hw *[]) {
1438 &pcie1_axi_s_clk_src.clkr.hw
1439 },
1440 .num_parents = 1,
1441 .flags = CLK_SET_RATE_PARENT,
1442 .ops = &clk_branch2_ops,
1443 },
1444 },
1445 };
1446
1447 static struct clk_rcg2 pcie2_axi_s_clk_src = {
1448 .cmd_rcgr = 0x2a020,
1449 .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1450 .hid_width = 5,
1451 .parent_map = gcc_xo_gpll0_gpll4_map,
1452 .clkr.hw.init = &(const struct clk_init_data) {
1453 .name = "pcie2_axi_s_clk_src",
1454 .parent_data = gcc_xo_gpll0_gpll4,
1455 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1456 .ops = &clk_rcg2_ops,
1457 },
1458 };
1459
1460 static struct clk_branch gcc_pcie2_axi_s_clk = {
1461 .halt_reg = 0x2a03c,
1462 .clkr = {
1463 .enable_reg = 0x2a03c,
1464 .enable_mask = BIT(0),
1465 .hw.init = &(const struct clk_init_data) {
1466 .name = "gcc_pcie2_axi_s_clk",
1467 .parent_hws = (const struct clk_hw *[]) {
1468 &pcie2_axi_s_clk_src.clkr.hw
1469 },
1470 .num_parents = 1,
1471 .flags = CLK_SET_RATE_PARENT,
1472 .ops = &clk_branch2_ops,
1473 },
1474 },
1475 };
1476
1477 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1478 .halt_reg = 0x2a040,
1479 .clkr = {
1480 .enable_reg = 0x2a040,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(const struct clk_init_data) {
1483 .name = "gcc_pcie2_axi_s_bridge_clk",
1484 .parent_hws = (const struct clk_hw *[]) {
1485 &pcie2_axi_s_clk_src.clkr.hw
1486 },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492 };
1493
1494 static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
1495 .halt_reg = 0x2e050,
1496 .clkr = {
1497 .enable_reg = 0x2e050,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(const struct clk_init_data) {
1500 .name = "gcc_snoc_pcie2_2lane_s_clk",
1501 .parent_hws = (const struct clk_hw *[]) {
1502 &pcie2_axi_s_clk_src.clkr.hw
1503 },
1504 .num_parents = 1,
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509 };
1510
1511 static struct clk_rcg2 pcie3_axi_s_clk_src = {
1512 .cmd_rcgr = 0x2b020,
1513 .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1514 .hid_width = 5,
1515 .parent_map = gcc_xo_gpll0_gpll4_map,
1516 .clkr.hw.init = &(const struct clk_init_data) {
1517 .name = "pcie3_axi_s_clk_src",
1518 .parent_data = gcc_xo_gpll0_gpll4,
1519 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1520 .ops = &clk_rcg2_ops,
1521 },
1522 };
1523
1524 static struct clk_branch gcc_pcie3_axi_s_clk = {
1525 .halt_reg = 0x2b03c,
1526 .clkr = {
1527 .enable_reg = 0x2b03c,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(const struct clk_init_data) {
1530 .name = "gcc_pcie3_axi_s_clk",
1531 .parent_hws = (const struct clk_hw *[]) {
1532 &pcie3_axi_s_clk_src.clkr.hw
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539 };
1540
1541 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1542 .halt_reg = 0x2b040,
1543 .clkr = {
1544 .enable_reg = 0x2b040,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(const struct clk_init_data) {
1547 .name = "gcc_pcie3_axi_s_bridge_clk",
1548 .parent_hws = (const struct clk_hw *[]) {
1549 &pcie3_axi_s_clk_src.clkr.hw
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556 };
1557
1558 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
1559 .halt_reg = 0x2e054,
1560 .clkr = {
1561 .enable_reg = 0x2e054,
1562 .enable_mask = BIT(0),
1563 .hw.init = &(const struct clk_init_data) {
1564 .name = "gcc_snoc_pcie3_2lane_s_clk",
1565 .parent_hws = (const struct clk_hw *[]) {
1566 &pcie3_axi_s_clk_src.clkr.hw
1567 },
1568 .num_parents = 1,
1569 .flags = CLK_SET_RATE_PARENT,
1570 .ops = &clk_branch2_ops,
1571 },
1572 },
1573 };
1574
1575 static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
1576 .reg = 0x28064,
1577 .clkr = {
1578 .hw.init = &(const struct clk_init_data) {
1579 .name = "pcie0_pipe_clk_src",
1580 .parent_data = &(const struct clk_parent_data) {
1581 .index = DT_PCIE30_PHY0_PIPE_CLK,
1582 },
1583 .num_parents = 1,
1584 .ops = &clk_regmap_phy_mux_ops,
1585 },
1586 },
1587 };
1588
1589 static struct clk_branch gcc_pcie0_pipe_clk = {
1590 .halt_reg = 0x28044,
1591 .halt_check = BRANCH_HALT_DELAY,
1592 .clkr = {
1593 .enable_reg = 0x28044,
1594 .enable_mask = BIT(0),
1595 .hw.init = &(const struct clk_init_data) {
1596 .name = "gcc_pcie0_pipe_clk",
1597 .parent_hws = (const struct clk_hw *[]) {
1598 &pcie0_pipe_clk_src.clkr.hw
1599 },
1600 .num_parents = 1,
1601 .flags = CLK_SET_RATE_PARENT,
1602 .ops = &clk_branch2_ops,
1603 },
1604 },
1605 };
1606
1607 static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
1608 .reg = 0x29064,
1609 .clkr = {
1610 .hw.init = &(const struct clk_init_data) {
1611 .name = "pcie1_pipe_clk_src",
1612 .parent_data = &(const struct clk_parent_data) {
1613 .index = DT_PCIE30_PHY1_PIPE_CLK,
1614 },
1615 .num_parents = 1,
1616 .ops = &clk_regmap_phy_mux_ops,
1617 },
1618 },
1619 };
1620
1621 static struct clk_branch gcc_pcie1_pipe_clk = {
1622 .halt_reg = 0x29044,
1623 .halt_check = BRANCH_HALT_DELAY,
1624 .clkr = {
1625 .enable_reg = 0x29044,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(const struct clk_init_data) {
1628 .name = "gcc_pcie1_pipe_clk",
1629 .parent_hws = (const struct clk_hw *[]) {
1630 &pcie1_pipe_clk_src.clkr.hw
1631 },
1632 .num_parents = 1,
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1635 },
1636 },
1637 };
1638
1639 static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
1640 .reg = 0x2a064,
1641 .clkr = {
1642 .hw.init = &(const struct clk_init_data) {
1643 .name = "pcie2_pipe_clk_src",
1644 .parent_data = &(const struct clk_parent_data) {
1645 .index = DT_PCIE30_PHY2_PIPE_CLK,
1646 },
1647 .num_parents = 1,
1648 .ops = &clk_regmap_phy_mux_ops,
1649 },
1650 },
1651 };
1652
1653 static struct clk_branch gcc_pcie2_pipe_clk = {
1654 .halt_reg = 0x2a044,
1655 .halt_check = BRANCH_HALT_DELAY,
1656 .clkr = {
1657 .enable_reg = 0x2a044,
1658 .enable_mask = BIT(0),
1659 .hw.init = &(const struct clk_init_data) {
1660 .name = "gcc_pcie2_pipe_clk",
1661 .parent_hws = (const struct clk_hw *[]) {
1662 &pcie2_pipe_clk_src.clkr.hw
1663 },
1664 .num_parents = 1,
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669 };
1670
1671 static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
1672 .reg = 0x2b064,
1673 .clkr = {
1674 .hw.init = &(const struct clk_init_data) {
1675 .name = "pcie3_pipe_clk_src",
1676 .parent_data = &(const struct clk_parent_data) {
1677 .index = DT_PCIE30_PHY3_PIPE_CLK,
1678 },
1679 .num_parents = 1,
1680 .ops = &clk_regmap_phy_mux_ops,
1681 },
1682 },
1683 };
1684
1685 static struct clk_branch gcc_pcie3_pipe_clk = {
1686 .halt_reg = 0x2b044,
1687 .halt_check = BRANCH_HALT_DELAY,
1688 .clkr = {
1689 .enable_reg = 0x2b044,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(const struct clk_init_data) {
1692 .name = "gcc_pcie3_pipe_clk",
1693 .parent_hws = (const struct clk_hw *[]) {
1694 &pcie3_pipe_clk_src.clkr.hw
1695 },
1696 .num_parents = 1,
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1699 },
1700 },
1701 };
1702
1703 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
1704 F(24000000, P_XO, 1, 0, 0),
1705 F(100000000, P_GPLL0, 8, 0, 0),
1706 { }
1707 };
1708
1709 static struct clk_rcg2 pcie0_rchng_clk_src = {
1710 .cmd_rcgr = 0x28028,
1711 .freq_tbl = ftbl_pcie_rchng_clk_src,
1712 .hid_width = 5,
1713 .parent_map = gcc_xo_gpll0_map,
1714 .clkr.hw.init = &(const struct clk_init_data) {
1715 .name = "pcie0_rchng_clk_src",
1716 .parent_data = gcc_xo_gpll0,
1717 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1718 .ops = &clk_rcg2_ops,
1719 },
1720 };
1721
1722 static struct clk_branch gcc_pcie0_rchng_clk = {
1723 .halt_reg = 0x28028,
1724 .clkr = {
1725 .enable_reg = 0x28028,
1726 .enable_mask = BIT(1),
1727 .hw.init = &(const struct clk_init_data) {
1728 .name = "gcc_pcie0_rchng_clk",
1729 .parent_hws = (const struct clk_hw *[]) {
1730 &pcie0_rchng_clk_src.clkr.hw
1731
1732 },
1733 .num_parents = 1,
1734 .flags = CLK_SET_RATE_PARENT,
1735 .ops = &clk_branch2_ops,
1736 },
1737 },
1738 };
1739
1740 static struct clk_rcg2 pcie1_rchng_clk_src = {
1741 .cmd_rcgr = 0x29028,
1742 .freq_tbl = ftbl_pcie_rchng_clk_src,
1743 .hid_width = 5,
1744 .parent_map = gcc_xo_gpll0_map,
1745 .clkr.hw.init = &(const struct clk_init_data) {
1746 .name = "pcie1_rchng_clk_src",
1747 .parent_data = gcc_xo_gpll0,
1748 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1749 .ops = &clk_rcg2_ops,
1750 },
1751 };
1752
1753 static struct clk_branch gcc_pcie1_rchng_clk = {
1754 .halt_reg = 0x29028,
1755 .clkr = {
1756 .enable_reg = 0x29028,
1757 .enable_mask = BIT(1),
1758 .hw.init = &(const struct clk_init_data) {
1759 .name = "gcc_pcie1_rchng_clk",
1760 .parent_hws = (const struct clk_hw *[]) {
1761 &pcie1_rchng_clk_src.clkr.hw
1762 },
1763 .num_parents = 1,
1764 .flags = CLK_SET_RATE_PARENT,
1765 .ops = &clk_branch2_ops,
1766 },
1767 },
1768 };
1769
1770 static struct clk_rcg2 pcie2_rchng_clk_src = {
1771 .cmd_rcgr = 0x2a028,
1772 .freq_tbl = ftbl_pcie_rchng_clk_src,
1773 .hid_width = 5,
1774 .parent_map = gcc_xo_gpll0_map,
1775 .clkr.hw.init = &(const struct clk_init_data) {
1776 .name = "pcie2_rchng_clk_src",
1777 .parent_data = gcc_xo_gpll0,
1778 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1779 .ops = &clk_rcg2_ops,
1780 },
1781 };
1782
1783 static struct clk_branch gcc_pcie2_rchng_clk = {
1784 .halt_reg = 0x2a028,
1785 .clkr = {
1786 .enable_reg = 0x2a028,
1787 .enable_mask = BIT(1),
1788 .hw.init = &(const struct clk_init_data) {
1789 .name = "gcc_pcie2_rchng_clk",
1790 .parent_hws = (const struct clk_hw *[]) {
1791 &pcie2_rchng_clk_src.clkr.hw
1792 },
1793 .num_parents = 1,
1794 .flags = CLK_SET_RATE_PARENT,
1795 .ops = &clk_branch2_ops,
1796 },
1797 },
1798 };
1799
1800 static struct clk_rcg2 pcie3_rchng_clk_src = {
1801 .cmd_rcgr = 0x2b028,
1802 .freq_tbl = ftbl_pcie_rchng_clk_src,
1803 .hid_width = 5,
1804 .parent_map = gcc_xo_gpll0_map,
1805 .clkr.hw.init = &(const struct clk_init_data) {
1806 .name = "pcie3_rchng_clk_src",
1807 .parent_data = gcc_xo_gpll0,
1808 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1809 .ops = &clk_rcg2_ops,
1810 },
1811 };
1812
1813 static struct clk_branch gcc_pcie3_rchng_clk = {
1814 .halt_reg = 0x2b028,
1815 .clkr = {
1816 .enable_reg = 0x2b028,
1817 .enable_mask = BIT(1),
1818 .hw.init = &(const struct clk_init_data) {
1819 .name = "gcc_pcie3_rchng_clk",
1820 .parent_hws = (const struct clk_hw *[]) {
1821 &pcie3_rchng_clk_src.clkr.hw
1822 },
1823 .num_parents = 1,
1824 .flags = CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1826 },
1827 },
1828 };
1829
1830 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1831 F(20000000, P_GPLL0, 10, 1, 4),
1832 { }
1833 };
1834
1835 static struct clk_rcg2 pcie_aux_clk_src = {
1836 .cmd_rcgr = 0x28004,
1837 .freq_tbl = ftbl_pcie_aux_clk_src,
1838 .mnd_width = 16,
1839 .hid_width = 5,
1840 .parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
1841 .clkr.hw.init = &(const struct clk_init_data) {
1842 .name = "pcie_aux_clk_src",
1843 .parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
1844 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
1845 .ops = &clk_rcg2_ops,
1846 },
1847 };
1848
1849 static struct clk_branch gcc_pcie0_aux_clk = {
1850 .halt_reg = 0x28034,
1851 .clkr = {
1852 .enable_reg = 0x28034,
1853 .enable_mask = BIT(0),
1854 .hw.init = &(const struct clk_init_data) {
1855 .name = "gcc_pcie0_aux_clk",
1856 .parent_hws = (const struct clk_hw *[]) {
1857 &pcie_aux_clk_src.clkr.hw
1858 },
1859 .num_parents = 1,
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1862 },
1863 },
1864 };
1865
1866 static struct clk_branch gcc_pcie1_aux_clk = {
1867 .halt_reg = 0x29034,
1868 .clkr = {
1869 .enable_reg = 0x29034,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(const struct clk_init_data) {
1872 .name = "gcc_pcie1_aux_clk",
1873 .parent_hws = (const struct clk_hw *[]) {
1874 &pcie_aux_clk_src.clkr.hw
1875 },
1876 .num_parents = 1,
1877 .flags = CLK_SET_RATE_PARENT,
1878 .ops = &clk_branch2_ops,
1879 },
1880 },
1881 };
1882
1883 static struct clk_branch gcc_pcie2_aux_clk = {
1884 .halt_reg = 0x2a034,
1885 .clkr = {
1886 .enable_reg = 0x2a034,
1887 .enable_mask = BIT(0),
1888 .hw.init = &(const struct clk_init_data) {
1889 .name = "gcc_pcie2_aux_clk",
1890 .parent_hws = (const struct clk_hw *[]) {
1891 &pcie_aux_clk_src.clkr.hw
1892 },
1893 .num_parents = 1,
1894 .flags = CLK_SET_RATE_PARENT,
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898 };
1899
1900 static struct clk_branch gcc_pcie3_aux_clk = {
1901 .halt_reg = 0x2b034,
1902 .clkr = {
1903 .enable_reg = 0x2b034,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(const struct clk_init_data) {
1906 .name = "gcc_pcie3_aux_clk",
1907 .parent_hws = (const struct clk_hw *[]) {
1908 &pcie_aux_clk_src.clkr.hw
1909 },
1910 .num_parents = 1,
1911 .flags = CLK_SET_RATE_PARENT,
1912 .ops = &clk_branch2_ops,
1913 },
1914 },
1915 };
1916
1917 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1918 F(24000000, P_XO, 1, 0, 0),
1919 { }
1920 };
1921
1922 static struct clk_rcg2 usb0_aux_clk_src = {
1923 .cmd_rcgr = 0x2c018,
1924 .freq_tbl = ftbl_usb_aux_clk_src,
1925 .mnd_width = 16,
1926 .hid_width = 5,
1927 .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1928 .clkr.hw.init = &(const struct clk_init_data) {
1929 .name = "usb0_aux_clk_src",
1930 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1931 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1932 .ops = &clk_rcg2_ops,
1933 },
1934 };
1935
1936 static struct clk_branch gcc_usb0_aux_clk = {
1937 .halt_reg = 0x2c048,
1938 .clkr = {
1939 .enable_reg = 0x2c048,
1940 .enable_mask = BIT(0),
1941 .hw.init = &(const struct clk_init_data) {
1942 .name = "gcc_usb0_aux_clk",
1943 .parent_hws = (const struct clk_hw *[]) {
1944 &usb0_aux_clk_src.clkr.hw
1945 },
1946 .num_parents = 1,
1947 .flags = CLK_SET_RATE_PARENT,
1948 .ops = &clk_branch2_ops,
1949 },
1950 },
1951 };
1952
1953 static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
1954 F(100000000, P_GPLL0, 8, 0, 0),
1955 F(200000000, P_GPLL0, 4, 0, 0),
1956 { }
1957 };
1958
1959 static struct clk_rcg2 usb0_master_clk_src = {
1960 .cmd_rcgr = 0x2c004,
1961 .freq_tbl = ftbl_usb0_master_clk_src,
1962 .mnd_width = 8,
1963 .hid_width = 5,
1964 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1965 .clkr.hw.init = &(const struct clk_init_data) {
1966 .name = "usb0_master_clk_src",
1967 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1968 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1969 .ops = &clk_rcg2_ops,
1970 },
1971 };
1972
1973 static struct clk_branch gcc_usb0_master_clk = {
1974 .halt_reg = 0x2c044,
1975 .clkr = {
1976 .enable_reg = 0x2c044,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(const struct clk_init_data) {
1979 .name = "gcc_usb0_master_clk",
1980 .parent_hws = (const struct clk_hw *[]) {
1981 &usb0_master_clk_src.clkr.hw
1982 },
1983 .num_parents = 1,
1984 .flags = CLK_SET_RATE_PARENT,
1985 .ops = &clk_branch2_ops,
1986 },
1987 },
1988 };
1989
1990 static struct clk_branch gcc_snoc_usb_clk = {
1991 .halt_reg = 0x2e058,
1992 .clkr = {
1993 .enable_reg = 0x2e058,
1994 .enable_mask = BIT(0),
1995 .hw.init = &(const struct clk_init_data) {
1996 .name = "gcc_snoc_usb_clk",
1997 .parent_hws = (const struct clk_hw *[]) {
1998 &usb0_master_clk_src.clkr.hw
1999 },
2000 .num_parents = 1,
2001 .flags = CLK_SET_RATE_PARENT,
2002 .ops = &clk_branch2_ops,
2003 },
2004 },
2005 };
2006
2007 static struct clk_branch gcc_anoc_usb_axi_clk = {
2008 .halt_reg = 0x2e084,
2009 .clkr = {
2010 .enable_reg = 0x2e084,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(const struct clk_init_data) {
2013 .name = "gcc_anoc_usb_axi_clk",
2014 .parent_hws = (const struct clk_hw *[]) {
2015 &usb0_master_clk_src.clkr.hw
2016 },
2017 .num_parents = 1,
2018 .flags = CLK_SET_RATE_PARENT,
2019 .ops = &clk_branch2_ops,
2020 },
2021 },
2022 };
2023
2024 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
2025 F(24000000, P_XO, 1, 0, 0),
2026 F(60000000, P_GPLL4, 10, 1, 2),
2027 { }
2028 };
2029
2030 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
2031 .cmd_rcgr = 0x2c02c,
2032 .freq_tbl = ftbl_usb0_mock_utmi_clk_src,
2033 .mnd_width = 8,
2034 .hid_width = 5,
2035 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
2036 .clkr.hw.init = &(const struct clk_init_data) {
2037 .name = "usb0_mock_utmi_clk_src",
2038 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
2039 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
2040 .ops = &clk_rcg2_ops,
2041 },
2042 };
2043
2044 static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
2045 .reg = 0x2c040,
2046 .shift = 0,
2047 .width = 2,
2048 .clkr.hw.init = &(const struct clk_init_data) {
2049 .name = "usb0_mock_utmi_div_clk_src",
2050 .parent_data = &(const struct clk_parent_data) {
2051 .hw = &usb0_mock_utmi_clk_src.clkr.hw,
2052 },
2053 .num_parents = 1,
2054 .flags = CLK_SET_RATE_PARENT,
2055 .ops = &clk_regmap_div_ro_ops,
2056 },
2057 };
2058
2059 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2060 .halt_reg = 0x2c04c,
2061 .clkr = {
2062 .enable_reg = 0x2c04c,
2063 .enable_mask = BIT(0),
2064 .hw.init = &(const struct clk_init_data) {
2065 .name = "gcc_usb0_mock_utmi_clk",
2066 .parent_hws = (const struct clk_hw *[]) {
2067 &usb0_mock_utmi_div_clk_src.clkr.hw
2068 },
2069 .num_parents = 1,
2070 .flags = CLK_SET_RATE_PARENT,
2071 .ops = &clk_branch2_ops,
2072 },
2073 },
2074 };
2075
2076 static struct clk_regmap_mux usb0_pipe_clk_src = {
2077 .reg = 0x2C074,
2078 .shift = 8,
2079 .width = 2,
2080 .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
2081 .clkr = {
2082 .hw.init = &(const struct clk_init_data) {
2083 .name = "usb0_pipe_clk_src",
2084 .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
2085 .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
2086 .flags = CLK_SET_RATE_PARENT,
2087 .ops = &clk_regmap_mux_closest_ops,
2088 },
2089 },
2090 };
2091
2092 static struct clk_branch gcc_usb0_pipe_clk = {
2093 .halt_reg = 0x2c054,
2094 .halt_check = BRANCH_HALT_DELAY,
2095 .clkr = {
2096 .enable_reg = 0x2c054,
2097 .enable_mask = BIT(0),
2098 .hw.init = &(const struct clk_init_data){
2099 .name = "gcc_usb0_pipe_clk",
2100 .parent_hws = (const struct clk_hw *[]) {
2101 &usb0_pipe_clk_src.clkr.hw
2102 },
2103 .num_parents = 1,
2104 .flags = CLK_SET_RATE_PARENT,
2105 .ops = &clk_branch2_ops,
2106 },
2107 },
2108 };
2109
2110 static struct clk_branch gcc_usb0_sleep_clk = {
2111 .halt_reg = 0x2c058,
2112 .clkr = {
2113 .enable_reg = 0x2c058,
2114 .enable_mask = BIT(0),
2115 .hw.init = &(const struct clk_init_data){
2116 .name = "gcc_usb0_sleep_clk",
2117 .parent_hws = (const struct clk_hw *[]) {
2118 &gcc_sleep_clk_src.clkr.hw
2119 },
2120 .num_parents = 1,
2121 .flags = CLK_SET_RATE_PARENT,
2122 .ops = &clk_branch2_ops,
2123 },
2124 },
2125 };
2126
2127 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
2128 F(144000, P_XO, 16, 12, 125),
2129 F(400000, P_XO, 12, 1, 5),
2130 F(24000000, P_GPLL2, 12, 1, 4),
2131 F(48000000, P_GPLL2, 12, 1, 2),
2132 F(96000000, P_GPLL2, 12, 0, 0),
2133 F(177777778, P_GPLL0, 4.5, 0, 0),
2134 F(192000000, P_GPLL2, 6, 0, 0),
2135 F(384000000, P_GPLL2, 3, 0, 0),
2136 F(400000000, P_GPLL0, 2, 0, 0),
2137 { }
2138 };
2139
2140 static struct clk_rcg2 sdcc1_apps_clk_src = {
2141 .cmd_rcgr = 0x33004,
2142 .freq_tbl = ftbl_sdcc_apps_clk_src,
2143 .mnd_width = 8,
2144 .hid_width = 5,
2145 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
2146 .clkr.hw.init = &(const struct clk_init_data) {
2147 .name = "sdcc1_apps_clk_src",
2148 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
2149 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
2150 .ops = &clk_rcg2_floor_ops,
2151 },
2152 };
2153
2154 static struct clk_branch gcc_sdcc1_apps_clk = {
2155 .halt_reg = 0x3302c,
2156 .clkr = {
2157 .enable_reg = 0x3302c,
2158 .enable_mask = BIT(0),
2159 .hw.init = &(const struct clk_init_data) {
2160 .name = "gcc_sdcc1_apps_clk",
2161 .parent_hws = (const struct clk_hw *[]) {
2162 &sdcc1_apps_clk_src.clkr.hw
2163 },
2164 .num_parents = 1,
2165 .flags = CLK_SET_RATE_PARENT,
2166 .ops = &clk_branch2_ops,
2167 },
2168 },
2169 };
2170
2171 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
2172 F(150000000, P_GPLL4, 8, 0, 0),
2173 F(300000000, P_GPLL4, 4, 0, 0),
2174 { }
2175 };
2176
2177 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
2178 .cmd_rcgr = 0x33018,
2179 .freq_tbl = ftbl_sdcc_ice_core_clk_src,
2180 .mnd_width = 8,
2181 .hid_width = 5,
2182 .parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
2183 .clkr.hw.init = &(const struct clk_init_data) {
2184 .name = "sdcc1_ice_core_clk_src",
2185 .parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
2186 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
2187 .ops = &clk_rcg2_ops,
2188 },
2189 };
2190
2191 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2192 .halt_reg = 0x33030,
2193 .clkr = {
2194 .enable_reg = 0x33030,
2195 .enable_mask = BIT(0),
2196 .hw.init = &(const struct clk_init_data) {
2197 .name = "gcc_sdcc1_ice_core_clk",
2198 .parent_hws = (const struct clk_hw *[]) {
2199 &sdcc1_ice_core_clk_src.clkr.hw
2200 },
2201 .num_parents = 1,
2202 .flags = CLK_SET_RATE_PARENT,
2203 .ops = &clk_branch2_ops,
2204 },
2205 },
2206 };
2207
2208 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
2209 F(24000000, P_XO, 1, 0, 0),
2210 F(50000000, P_GPLL0, 16, 0, 0),
2211 F(80000000, P_GPLL0, 10, 0, 0),
2212 F(100000000, P_GPLL0, 8, 0, 0),
2213 { }
2214 };
2215
2216 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
2217 .cmd_rcgr = 0x31004,
2218 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
2219 .hid_width = 5,
2220 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2221 .clkr.hw.init = &(const struct clk_init_data) {
2222 .name = "pcnoc_bfdcd_clk_src",
2223 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2224 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2225 .flags = CLK_IS_CRITICAL,
2226 .ops = &clk_rcg2_ops,
2227 },
2228 };
2229
2230 static struct clk_branch gcc_crypto_axi_clk = {
2231 .halt_reg = 0x16010,
2232 .halt_check = BRANCH_HALT_VOTED,
2233 .clkr = {
2234 .enable_reg = 0xb004,
2235 .enable_mask = BIT(15),
2236 .hw.init = &(const struct clk_init_data) {
2237 .name = "gcc_crypto_axi_clk",
2238 .parent_hws = (const struct clk_hw *[]) {
2239 &pcnoc_bfdcd_clk_src.clkr.hw },
2240 .num_parents = 1,
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2243 },
2244 },
2245 };
2246
2247 static struct clk_branch gcc_crypto_ahb_clk = {
2248 .halt_reg = 0x16014,
2249 .halt_check = BRANCH_HALT_VOTED,
2250 .clkr = {
2251 .enable_reg = 0xb004,
2252 .enable_mask = BIT(16),
2253 .hw.init = &(const struct clk_init_data) {
2254 .name = "gcc_crypto_ahb_clk",
2255 .parent_hws = (const struct clk_hw *[]) {
2256 &pcnoc_bfdcd_clk_src.clkr.hw },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262 };
2263
2264 static struct clk_branch gcc_nsscfg_clk = {
2265 .halt_reg = 0x1702c,
2266 .clkr = {
2267 .enable_reg = 0x1702c,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(const struct clk_init_data) {
2270 .name = "gcc_nsscfg_clk",
2271 .parent_hws = (const struct clk_hw *[]) {
2272 &pcnoc_bfdcd_clk_src.clkr.hw
2273 },
2274 .num_parents = 1,
2275 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops,
2277 },
2278 },
2279 };
2280
2281 static struct clk_branch gcc_nssnoc_nsscc_clk = {
2282 .halt_reg = 0x17030,
2283 .clkr = {
2284 .enable_reg = 0x17030,
2285 .enable_mask = BIT(0),
2286 .hw.init = &(const struct clk_init_data) {
2287 .name = "gcc_nssnoc_nsscc_clk",
2288 .parent_hws = (const struct clk_hw *[]) {
2289 &pcnoc_bfdcd_clk_src.clkr.hw
2290 },
2291 .num_parents = 1,
2292 .flags = CLK_SET_RATE_PARENT,
2293 .ops = &clk_branch2_ops,
2294 },
2295 },
2296 };
2297
2298 static struct clk_branch gcc_nsscc_clk = {
2299 .halt_reg = 0x17034,
2300 .clkr = {
2301 .enable_reg = 0x17034,
2302 .enable_mask = BIT(0),
2303 .hw.init = &(const struct clk_init_data) {
2304 .name = "gcc_nsscc_clk",
2305 .parent_hws = (const struct clk_hw *[]) {
2306 &pcnoc_bfdcd_clk_src.clkr.hw
2307 },
2308 .num_parents = 1,
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2311 },
2312 },
2313 };
2314
2315 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
2316 .halt_reg = 0x17080,
2317 .clkr = {
2318 .enable_reg = 0x17080,
2319 .enable_mask = BIT(0),
2320 .hw.init = &(const struct clk_init_data) {
2321 .name = "gcc_nssnoc_pcnoc_1_clk",
2322 .parent_hws = (const struct clk_hw *[]) {
2323 &pcnoc_bfdcd_clk_src.clkr.hw
2324 },
2325 .num_parents = 1,
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2328 },
2329 },
2330 };
2331
2332 static struct clk_branch gcc_qdss_dap_ahb_clk = {
2333 .halt_reg = 0x2d064,
2334 .clkr = {
2335 .enable_reg = 0x2d064,
2336 .enable_mask = BIT(0),
2337 .hw.init = &(const struct clk_init_data) {
2338 .name = "gcc_qdss_dap_ahb_clk",
2339 .parent_hws = (const struct clk_hw *[]) {
2340 &pcnoc_bfdcd_clk_src.clkr.hw
2341 },
2342 .num_parents = 1,
2343 .flags = CLK_SET_RATE_PARENT,
2344 .ops = &clk_branch2_ops,
2345 },
2346 },
2347 };
2348
2349 static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2350 .halt_reg = 0x2d068,
2351 .clkr = {
2352 .enable_reg = 0x2d068,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(const struct clk_init_data) {
2355 .name = "gcc_qdss_cfg_ahb_clk",
2356 .parent_hws = (const struct clk_hw *[]) {
2357 &pcnoc_bfdcd_clk_src.clkr.hw
2358 },
2359 .num_parents = 1,
2360 .flags = CLK_SET_RATE_PARENT,
2361 .ops = &clk_branch2_ops,
2362 },
2363 },
2364 };
2365
2366 static struct clk_branch gcc_qpic_ahb_clk = {
2367 .halt_reg = 0x32010,
2368 .clkr = {
2369 .enable_reg = 0x32010,
2370 .enable_mask = BIT(0),
2371 .hw.init = &(const struct clk_init_data) {
2372 .name = "gcc_qpic_ahb_clk",
2373 .parent_hws = (const struct clk_hw *[]) {
2374 &pcnoc_bfdcd_clk_src.clkr.hw
2375 },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381 };
2382
2383 static struct clk_branch gcc_qpic_clk = {
2384 .halt_reg = 0x32014,
2385 .clkr = {
2386 .enable_reg = 0x32014,
2387 .enable_mask = BIT(0),
2388 .hw.init = &(const struct clk_init_data) {
2389 .name = "gcc_qpic_clk",
2390 .parent_hws = (const struct clk_hw *[]) {
2391 &pcnoc_bfdcd_clk_src.clkr.hw
2392 },
2393 .num_parents = 1,
2394 .flags = CLK_SET_RATE_PARENT,
2395 .ops = &clk_branch2_ops,
2396 },
2397 },
2398 };
2399
2400 static struct clk_branch gcc_blsp1_ahb_clk = {
2401 .halt_reg = 0x01004,
2402 .halt_check = BRANCH_HALT_VOTED,
2403 .clkr = {
2404 .enable_reg = 0x0b004,
2405 .enable_mask = BIT(4),
2406 .hw.init = &(const struct clk_init_data) {
2407 .name = "gcc_blsp1_ahb_clk",
2408 .parent_hws = (const struct clk_hw *[]) {
2409 &pcnoc_bfdcd_clk_src.clkr.hw
2410 },
2411 .num_parents = 1,
2412 .flags = CLK_SET_RATE_PARENT,
2413 .ops = &clk_branch2_ops,
2414 },
2415 },
2416 };
2417
2418 static struct clk_branch gcc_mdio_ahb_clk = {
2419 .halt_reg = 0x17040,
2420 .clkr = {
2421 .enable_reg = 0x17040,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(const struct clk_init_data) {
2424 .name = "gcc_mdio_ahb_clk",
2425 .parent_hws = (const struct clk_hw *[]) {
2426 &pcnoc_bfdcd_clk_src.clkr.hw
2427 },
2428 .num_parents = 1,
2429 .flags = CLK_SET_RATE_PARENT,
2430 .ops = &clk_branch2_ops,
2431 },
2432 },
2433 };
2434
2435 static struct clk_branch gcc_prng_ahb_clk = {
2436 .halt_reg = 0x13024,
2437 .halt_check = BRANCH_HALT_VOTED,
2438 .clkr = {
2439 .enable_reg = 0x0b004,
2440 .enable_mask = BIT(10),
2441 .hw.init = &(const struct clk_init_data) {
2442 .name = "gcc_prng_ahb_clk",
2443 .parent_hws = (const struct clk_hw *[]) {
2444 &pcnoc_bfdcd_clk_src.clkr.hw
2445 },
2446 .num_parents = 1,
2447 .flags = CLK_SET_RATE_PARENT,
2448 .ops = &clk_branch2_ops,
2449 },
2450 },
2451 };
2452
2453 static struct clk_branch gcc_uniphy0_ahb_clk = {
2454 .halt_reg = 0x1704c,
2455 .clkr = {
2456 .enable_reg = 0x1704c,
2457 .enable_mask = BIT(0),
2458 .hw.init = &(const struct clk_init_data) {
2459 .name = "gcc_uniphy0_ahb_clk",
2460 .parent_hws = (const struct clk_hw *[]) {
2461 &pcnoc_bfdcd_clk_src.clkr.hw
2462 },
2463 .num_parents = 1,
2464 .flags = CLK_SET_RATE_PARENT,
2465 .ops = &clk_branch2_ops,
2466 },
2467 },
2468 };
2469
2470 static struct clk_branch gcc_uniphy1_ahb_clk = {
2471 .halt_reg = 0x1705c,
2472 .clkr = {
2473 .enable_reg = 0x1705c,
2474 .enable_mask = BIT(0),
2475 .hw.init = &(const struct clk_init_data) {
2476 .name = "gcc_uniphy1_ahb_clk",
2477 .parent_hws = (const struct clk_hw *[]) {
2478 &pcnoc_bfdcd_clk_src.clkr.hw
2479 },
2480 .num_parents = 1,
2481 .flags = CLK_SET_RATE_PARENT,
2482 .ops = &clk_branch2_ops,
2483 },
2484 },
2485 };
2486
2487 static struct clk_branch gcc_uniphy2_ahb_clk = {
2488 .halt_reg = 0x1706c,
2489 .clkr = {
2490 .enable_reg = 0x1706c,
2491 .enable_mask = BIT(0),
2492 .hw.init = &(const struct clk_init_data) {
2493 .name = "gcc_uniphy2_ahb_clk",
2494 .parent_hws = (const struct clk_hw *[]) {
2495 &pcnoc_bfdcd_clk_src.clkr.hw
2496 },
2497 .num_parents = 1,
2498 .flags = CLK_SET_RATE_PARENT,
2499 .ops = &clk_branch2_ops,
2500 },
2501 },
2502 };
2503
2504 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2505 .halt_reg = 0x3a004,
2506 .clkr = {
2507 .enable_reg = 0x3a004,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(const struct clk_init_data) {
2510 .name = "gcc_cmn_12gpll_ahb_clk",
2511 .parent_hws = (const struct clk_hw *[]) {
2512 &pcnoc_bfdcd_clk_src.clkr.hw
2513 },
2514 .num_parents = 1,
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2517 },
2518 },
2519 };
2520
2521 static struct clk_branch gcc_cmn_12gpll_apu_clk = {
2522 .halt_reg = 0x3a00c,
2523 .clkr = {
2524 .enable_reg = 0x3a00c,
2525 .enable_mask = BIT(0),
2526 .hw.init = &(const struct clk_init_data) {
2527 .name = "gcc_cmn_12gpll_apu_clk",
2528 .parent_hws = (const struct clk_hw *[]) {
2529 &pcnoc_bfdcd_clk_src.clkr.hw
2530 },
2531 .num_parents = 1,
2532 .flags = CLK_SET_RATE_PARENT,
2533 .ops = &clk_branch2_ops,
2534 },
2535 },
2536 };
2537
2538 static struct clk_branch gcc_pcie0_ahb_clk = {
2539 .halt_reg = 0x28030,
2540 .clkr = {
2541 .enable_reg = 0x28030,
2542 .enable_mask = BIT(0),
2543 .hw.init = &(const struct clk_init_data) {
2544 .name = "gcc_pcie0_ahb_clk",
2545 .parent_hws = (const struct clk_hw *[]) {
2546 &pcnoc_bfdcd_clk_src.clkr.hw
2547 },
2548 .num_parents = 1,
2549 .flags = CLK_SET_RATE_PARENT,
2550 .ops = &clk_branch2_ops,
2551 },
2552 },
2553 };
2554
2555 static struct clk_branch gcc_pcie1_ahb_clk = {
2556 .halt_reg = 0x29030,
2557 .clkr = {
2558 .enable_reg = 0x29030,
2559 .enable_mask = BIT(0),
2560 .hw.init = &(const struct clk_init_data) {
2561 .name = "gcc_pcie1_ahb_clk",
2562 .parent_hws = (const struct clk_hw *[]) {
2563 &pcnoc_bfdcd_clk_src.clkr.hw
2564 },
2565 .num_parents = 1,
2566 .flags = CLK_SET_RATE_PARENT,
2567 .ops = &clk_branch2_ops,
2568 },
2569 },
2570 };
2571
2572 static struct clk_branch gcc_pcie2_ahb_clk = {
2573 .halt_reg = 0x2a030,
2574 .clkr = {
2575 .enable_reg = 0x2a030,
2576 .enable_mask = BIT(0),
2577 .hw.init = &(const struct clk_init_data) {
2578 .name = "gcc_pcie2_ahb_clk",
2579 .parent_hws = (const struct clk_hw *[]) {
2580 &pcnoc_bfdcd_clk_src.clkr.hw
2581 },
2582 .num_parents = 1,
2583 .flags = CLK_SET_RATE_PARENT,
2584 .ops = &clk_branch2_ops,
2585 },
2586 },
2587 };
2588
2589 static struct clk_branch gcc_pcie3_ahb_clk = {
2590 .halt_reg = 0x2b030,
2591 .clkr = {
2592 .enable_reg = 0x2b030,
2593 .enable_mask = BIT(0),
2594 .hw.init = &(const struct clk_init_data) {
2595 .name = "gcc_pcie3_ahb_clk",
2596 .parent_hws = (const struct clk_hw *[]) {
2597 &pcnoc_bfdcd_clk_src.clkr.hw
2598 },
2599 .num_parents = 1,
2600 .flags = CLK_SET_RATE_PARENT,
2601 .ops = &clk_branch2_ops,
2602 },
2603 },
2604 };
2605
2606 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2607 .halt_reg = 0x2c05c,
2608 .clkr = {
2609 .enable_reg = 0x2c05c,
2610 .enable_mask = BIT(0),
2611 .hw.init = &(const struct clk_init_data) {
2612 .name = "gcc_usb0_phy_cfg_ahb_clk",
2613 .parent_hws = (const struct clk_hw *[]) {
2614 &pcnoc_bfdcd_clk_src.clkr.hw
2615 },
2616 .num_parents = 1,
2617 .flags = CLK_SET_RATE_PARENT,
2618 .ops = &clk_branch2_ops,
2619 },
2620 },
2621 };
2622
2623 static struct clk_branch gcc_sdcc1_ahb_clk = {
2624 .halt_reg = 0x33034,
2625 .clkr = {
2626 .enable_reg = 0x33034,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(const struct clk_init_data) {
2629 .name = "gcc_sdcc1_ahb_clk",
2630 .parent_hws = (const struct clk_hw *[]) {
2631 &pcnoc_bfdcd_clk_src.clkr.hw
2632 },
2633 .num_parents = 1,
2634 .flags = CLK_SET_RATE_PARENT,
2635 .ops = &clk_branch2_ops,
2636 },
2637 },
2638 };
2639
2640 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
2641 F(24000000, P_XO, 1, 0, 0),
2642 F(133333333, P_GPLL0, 6, 0, 0),
2643 F(200000000, P_GPLL0, 4, 0, 0),
2644 F(342850000, P_GPLL4, 3.5, 0, 0),
2645 { }
2646 };
2647
2648 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
2649 .cmd_rcgr = 0x2e004,
2650 .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
2651 .hid_width = 5,
2652 .parent_map = gcc_xo_gpll0_gpll4_map,
2653 .clkr.hw.init = &(const struct clk_init_data) {
2654 .name = "system_noc_bfdcd_clk_src",
2655 .parent_data = gcc_xo_gpll0_gpll4,
2656 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
2657 .flags = CLK_IS_CRITICAL,
2658 .ops = &clk_rcg2_ops,
2659 },
2660 };
2661
2662 static struct clk_branch gcc_nssnoc_snoc_clk = {
2663 .halt_reg = 0x17028,
2664 .clkr = {
2665 .enable_reg = 0x17028,
2666 .enable_mask = BIT(0),
2667 .hw.init = &(const struct clk_init_data) {
2668 .name = "gcc_nssnoc_snoc_clk",
2669 .parent_hws = (const struct clk_hw *[]) {
2670 &system_noc_bfdcd_clk_src.clkr.hw
2671 },
2672 .num_parents = 1,
2673 .flags = CLK_SET_RATE_PARENT,
2674 .ops = &clk_branch2_ops,
2675 },
2676 },
2677 };
2678
2679 static struct clk_branch gcc_nssnoc_snoc_1_clk = {
2680 .halt_reg = 0x1707c,
2681 .clkr = {
2682 .enable_reg = 0x1707c,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(const struct clk_init_data) {
2685 .name = "gcc_nssnoc_snoc_1_clk",
2686 .parent_hws = (const struct clk_hw *[]) {
2687 &system_noc_bfdcd_clk_src.clkr.hw
2688 },
2689 .num_parents = 1,
2690 .flags = CLK_SET_RATE_PARENT,
2691 .ops = &clk_branch2_ops,
2692 },
2693 },
2694 };
2695
2696 static struct clk_branch gcc_qdss_etr_usb_clk = {
2697 .halt_reg = 0x2d060,
2698 .clkr = {
2699 .enable_reg = 0x2d060,
2700 .enable_mask = BIT(0),
2701 .hw.init = &(const struct clk_init_data) {
2702 .name = "gcc_qdss_etr_usb_clk",
2703 .parent_hws = (const struct clk_hw *[]) {
2704 &system_noc_bfdcd_clk_src.clkr.hw
2705 },
2706 .num_parents = 1,
2707 .flags = CLK_SET_RATE_PARENT,
2708 .ops = &clk_branch2_ops,
2709 },
2710 },
2711 };
2712
2713 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2714 F(24000000, P_XO, 1, 0, 0),
2715 F(133333333, P_GPLL0, 6, 0, 0),
2716 { }
2717 };
2718
2719 static struct clk_rcg2 wcss_ahb_clk_src = {
2720 .cmd_rcgr = 0x25030,
2721 .freq_tbl = ftbl_wcss_ahb_clk_src,
2722 .hid_width = 5,
2723 .parent_map = gcc_xo_gpll0_map,
2724 .clkr.hw.init = &(const struct clk_init_data) {
2725 .name = "wcss_ahb_clk_src",
2726 .parent_data = gcc_xo_gpll0,
2727 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2728 .ops = &clk_rcg2_ops,
2729 },
2730 };
2731
2732 static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
2733 F(24000000, P_XO, 1, 0, 0),
2734 F(133333333, P_GPLL0, 6, 0, 0),
2735 F(266666667, P_GPLL0, 3, 0, 0),
2736 { }
2737 };
2738
2739 static struct clk_rcg2 wcss_axi_m_clk_src = {
2740 .cmd_rcgr = 0x25078,
2741 .freq_tbl = ftbl_wcss_axi_m_clk_src,
2742 .hid_width = 5,
2743 .parent_map = gcc_xo_gpll0_map,
2744 .clkr.hw.init = &(const struct clk_init_data) {
2745 .name = "wcss_axi_m_clk_src",
2746 .parent_data = gcc_xo_gpll0,
2747 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2748 .ops = &clk_rcg2_ops,
2749 },
2750 };
2751
2752 static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
2753 F(240000000, P_GPLL4, 5, 0, 0),
2754 { }
2755 };
2756
2757 static struct clk_rcg2 qdss_at_clk_src = {
2758 .cmd_rcgr = 0x2d004,
2759 .freq_tbl = ftbl_qdss_at_clk_src,
2760 .hid_width = 5,
2761 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2762 .clkr.hw.init = &(const struct clk_init_data) {
2763 .name = "qdss_at_clk_src",
2764 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2765 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2766 .ops = &clk_rcg2_ops,
2767 },
2768 };
2769
2770 static struct clk_branch gcc_nssnoc_atb_clk = {
2771 .halt_reg = 0x17014,
2772 .clkr = {
2773 .enable_reg = 0x17014,
2774 .enable_mask = BIT(0),
2775 .hw.init = &(const struct clk_init_data) {
2776 .name = "gcc_nssnoc_atb_clk",
2777 .parent_hws = (const struct clk_hw *[]) {
2778 &qdss_at_clk_src.clkr.hw
2779 },
2780 .num_parents = 1,
2781 .flags = CLK_SET_RATE_PARENT,
2782 .ops = &clk_branch2_ops,
2783 },
2784 },
2785 };
2786
2787 static struct clk_branch gcc_qdss_at_clk = {
2788 .halt_reg = 0x2d038,
2789 .clkr = {
2790 .enable_reg = 0x2d038,
2791 .enable_mask = BIT(0),
2792 .hw.init = &(const struct clk_init_data) {
2793 .name = "gcc_qdss_at_clk",
2794 .parent_hws = (const struct clk_hw *[]) {
2795 &qdss_at_clk_src.clkr.hw
2796 },
2797 .num_parents = 1,
2798 .flags = CLK_SET_RATE_PARENT,
2799 .ops = &clk_branch2_ops,
2800 },
2801 },
2802 };
2803
2804 static struct clk_branch gcc_sys_noc_at_clk = {
2805 .halt_reg = 0x2e038,
2806 .clkr = {
2807 .enable_reg = 0x2e038,
2808 .enable_mask = BIT(0),
2809 .hw.init = &(const struct clk_init_data) {
2810 .name = "gcc_sys_noc_at_clk",
2811 .parent_hws = (const struct clk_hw *[]) {
2812 &qdss_at_clk_src.clkr.hw
2813 },
2814 .num_parents = 1,
2815 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2816 .ops = &clk_branch2_ops,
2817 },
2818 },
2819 };
2820
2821 static struct clk_branch gcc_pcnoc_at_clk = {
2822 .halt_reg = 0x31024,
2823 .clkr = {
2824 .enable_reg = 0x31024,
2825 .enable_mask = BIT(0),
2826 .hw.init = &(const struct clk_init_data) {
2827 .name = "gcc_pcnoc_at_clk",
2828 .parent_hws = (const struct clk_hw *[]) {
2829 &qdss_at_clk_src.clkr.hw
2830 },
2831 .num_parents = 1,
2832 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2833 .ops = &clk_branch2_ops,
2834 },
2835 },
2836 };
2837
2838 static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2839 .mult = 1,
2840 .div = 6,
2841 .hw.init = &(const struct clk_init_data) {
2842 .name = "gcc_eud_at_div_clk_src",
2843 .parent_hws = (const struct clk_hw *[]) {
2844 &qdss_at_clk_src.clkr.hw
2845 },
2846 .num_parents = 1,
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_fixed_factor_ops,
2849 },
2850 };
2851
2852 static struct clk_branch gcc_usb0_eud_at_clk = {
2853 .halt_reg = 0x30004,
2854 .clkr = {
2855 .enable_reg = 0x30004,
2856 .enable_mask = BIT(0),
2857 .hw.init = &(const struct clk_init_data) {
2858 .name = "gcc_usb0_eud_at_clk",
2859 .parent_hws = (const struct clk_hw *[]) {
2860 &gcc_eud_at_div_clk_src.hw
2861 },
2862 .num_parents = 1,
2863 .flags = CLK_SET_RATE_PARENT,
2864 .ops = &clk_branch2_ops,
2865 },
2866 },
2867 };
2868
2869 static struct clk_branch gcc_qdss_eud_at_clk = {
2870 .halt_reg = 0x2d06c,
2871 .clkr = {
2872 .enable_reg = 0x2d06c,
2873 .enable_mask = BIT(0),
2874 .hw.init = &(const struct clk_init_data) {
2875 .name = "gcc_qdss_eud_at_clk",
2876 .parent_hws = (const struct clk_hw *[]) {
2877 &gcc_eud_at_div_clk_src.hw
2878 },
2879 .num_parents = 1,
2880 .flags = CLK_SET_RATE_PARENT,
2881 .ops = &clk_branch2_ops,
2882 },
2883 },
2884 };
2885
2886 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
2887 F(24000000, P_XO, 1, 0, 0),
2888 F(200000000, P_GPLL0, 4, 0, 0),
2889 { }
2890 };
2891
2892 static struct clk_rcg2 qdss_stm_clk_src = {
2893 .cmd_rcgr = 0x2d00c,
2894 .freq_tbl = ftbl_qdss_stm_clk_src,
2895 .hid_width = 5,
2896 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2897 .clkr.hw.init = &(const struct clk_init_data) {
2898 .name = "qdss_stm_clk_src",
2899 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2900 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2901 .ops = &clk_rcg2_ops,
2902 },
2903 };
2904
2905 static struct clk_branch gcc_qdss_stm_clk = {
2906 .halt_reg = 0x2d03c,
2907 .clkr = {
2908 .enable_reg = 0x2d03c,
2909 .enable_mask = BIT(0),
2910 .hw.init = &(const struct clk_init_data) {
2911 .name = "gcc_qdss_stm_clk",
2912 .parent_hws = (const struct clk_hw *[]) {
2913 &qdss_stm_clk_src.clkr.hw
2914 },
2915 .num_parents = 1,
2916 .flags = CLK_SET_RATE_PARENT,
2917 .ops = &clk_branch2_ops,
2918 },
2919 },
2920 };
2921
2922 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2923 .halt_reg = 0x2e034,
2924 .clkr = {
2925 .enable_reg = 0x2e034,
2926 .enable_mask = BIT(0),
2927 .hw.init = &(const struct clk_init_data) {
2928 .name = "gcc_sys_noc_qdss_stm_axi_clk",
2929 .parent_hws = (const struct clk_hw *[]) {
2930 &qdss_stm_clk_src.clkr.hw
2931 },
2932 .num_parents = 1,
2933 .flags = CLK_SET_RATE_PARENT,
2934 .ops = &clk_branch2_ops,
2935 },
2936 },
2937 };
2938
2939 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
2940 F(300000000, P_GPLL4, 4, 0, 0),
2941 { }
2942 };
2943
2944 static struct clk_rcg2 qdss_traceclkin_clk_src = {
2945 .cmd_rcgr = 0x2d014,
2946 .freq_tbl = ftbl_qdss_traceclkin_clk_src,
2947 .hid_width = 5,
2948 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2949 .clkr.hw.init = &(const struct clk_init_data) {
2950 .name = "qdss_traceclkin_clk_src",
2951 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2952 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2953 .ops = &clk_rcg2_ops,
2954 },
2955 };
2956
2957 static struct clk_branch gcc_qdss_traceclkin_clk = {
2958 .halt_reg = 0x2d040,
2959 .clkr = {
2960 .enable_reg = 0x2d040,
2961 .enable_mask = BIT(0),
2962 .hw.init = &(const struct clk_init_data) {
2963 .name = "gcc_qdss_traceclkin_clk",
2964 .parent_hws = (const struct clk_hw *[]) {
2965 &qdss_traceclkin_clk_src.clkr.hw
2966 },
2967 .num_parents = 1,
2968 .flags = CLK_SET_RATE_PARENT,
2969 .ops = &clk_branch2_ops,
2970 },
2971 },
2972 };
2973
2974 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
2975 F(600000000, P_GPLL4, 2, 0, 0),
2976 { }
2977 };
2978
2979 static struct clk_rcg2 qdss_tsctr_clk_src = {
2980 .cmd_rcgr = 0x2d01c,
2981 .freq_tbl = ftbl_qdss_tsctr_clk_src,
2982 .hid_width = 5,
2983 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2984 .clkr.hw.init = &(const struct clk_init_data) {
2985 .name = "qdss_tsctr_clk_src",
2986 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2987 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2988 .ops = &clk_rcg2_ops,
2989 },
2990 };
2991
2992 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
2993 .mult = 1,
2994 .div = 2,
2995 .hw.init = &(const struct clk_init_data) {
2996 .name = "qdss_tsctr_div2_clk_src",
2997 .parent_hws = (const struct clk_hw *[]) {
2998 &qdss_tsctr_clk_src.clkr.hw
2999 },
3000 .num_parents = 1,
3001 .flags = CLK_SET_RATE_PARENT,
3002 .ops = &clk_fixed_factor_ops,
3003 },
3004 };
3005
3006 static struct clk_branch gcc_qdss_tsctr_div2_clk = {
3007 .halt_reg = 0x2d044,
3008 .clkr = {
3009 .enable_reg = 0x2d044,
3010 .enable_mask = BIT(0),
3011 .hw.init = &(const struct clk_init_data) {
3012 .name = "gcc_qdss_tsctr_div2_clk",
3013 .parent_hws = (const struct clk_hw *[]) {
3014 &qdss_tsctr_div2_clk_src.hw
3015 },
3016 .num_parents = 1,
3017 .flags = CLK_SET_RATE_PARENT,
3018 .ops = &clk_branch2_ops,
3019 },
3020 },
3021 };
3022
3023 static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
3024 F(24000000, P_XO, 1, 0, 0),
3025 { }
3026 };
3027
3028 static struct clk_rcg2 uniphy_sys_clk_src = {
3029 .cmd_rcgr = 0x17090,
3030 .freq_tbl = ftbl_uniphy_sys_clk_src,
3031 .mnd_width = 8,
3032 .hid_width = 5,
3033 .parent_map = gcc_xo_map,
3034 .clkr.hw.init = &(const struct clk_init_data) {
3035 .name = "uniphy_sys_clk_src",
3036 .parent_data = gcc_xo_data,
3037 .num_parents = ARRAY_SIZE(gcc_xo_data),
3038 .ops = &clk_rcg2_ops,
3039 },
3040 };
3041
3042 static struct clk_rcg2 nss_ts_clk_src = {
3043 .cmd_rcgr = 0x17088,
3044 .freq_tbl = ftbl_uniphy_sys_clk_src,
3045 .mnd_width = 8,
3046 .hid_width = 5,
3047 .parent_map = gcc_xo_map,
3048 .clkr.hw.init = &(const struct clk_init_data) {
3049 .name = "nss_ts_clk_src",
3050 .parent_data = gcc_xo_data,
3051 .num_parents = ARRAY_SIZE(gcc_xo_data),
3052 .ops = &clk_rcg2_ops,
3053 },
3054 };
3055
3056 static struct clk_branch gcc_qdss_ts_clk = {
3057 .halt_reg = 0x2d078,
3058 .clkr = {
3059 .enable_reg = 0x2d078,
3060 .enable_mask = BIT(0),
3061 .hw.init = &(const struct clk_init_data) {
3062 .name = "gcc_qdss_ts_clk",
3063 .parent_hws = (const struct clk_hw *[]) {
3064 &nss_ts_clk_src.clkr.hw
3065 },
3066 .num_parents = 1,
3067 .flags = CLK_SET_RATE_PARENT,
3068 .ops = &clk_branch2_ops,
3069 },
3070 },
3071 };
3072
3073 static struct clk_fixed_factor qdss_dap_sync_clk_src = {
3074 .mult = 1,
3075 .div = 4,
3076 .hw.init = &(const struct clk_init_data) {
3077 .name = "qdss_dap_sync_clk_src",
3078 .parent_hws = (const struct clk_hw *[]) {
3079 &qdss_tsctr_clk_src.clkr.hw
3080 },
3081 .num_parents = 1,
3082 .ops = &clk_fixed_factor_ops,
3083 },
3084 };
3085
3086 static struct clk_branch gcc_qdss_tsctr_div4_clk = {
3087 .halt_reg = 0x2d04c,
3088 .clkr = {
3089 .enable_reg = 0x2d04c,
3090 .enable_mask = BIT(0),
3091 .hw.init = &(const struct clk_init_data) {
3092 .name = "gcc_qdss_tsctr_div4_clk",
3093 .parent_hws = (const struct clk_hw *[]) {
3094 &qdss_dap_sync_clk_src.hw
3095 },
3096 .num_parents = 1,
3097 .flags = CLK_SET_RATE_PARENT,
3098 .ops = &clk_branch2_ops,
3099 },
3100 },
3101 };
3102
3103 static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
3104 .mult = 1,
3105 .div = 8,
3106 .hw.init = &(const struct clk_init_data) {
3107 .name = "qdss_tsctr_div8_clk_src",
3108 .parent_hws = (const struct clk_hw *[]) {
3109 &qdss_tsctr_clk_src.clkr.hw
3110 },
3111 .num_parents = 1,
3112 .ops = &clk_fixed_factor_ops,
3113 },
3114 };
3115
3116 static struct clk_branch gcc_nss_ts_clk = {
3117 .halt_reg = 0x17018,
3118 .clkr = {
3119 .enable_reg = 0x17018,
3120 .enable_mask = BIT(0),
3121 .hw.init = &(const struct clk_init_data) {
3122 .name = "gcc_nss_ts_clk",
3123 .parent_hws = (const struct clk_hw *[]) {
3124 &nss_ts_clk_src.clkr.hw
3125 },
3126 .num_parents = 1,
3127 .flags = CLK_SET_RATE_PARENT,
3128 .ops = &clk_branch2_ops,
3129 },
3130 },
3131 };
3132
3133 static struct clk_branch gcc_qdss_tsctr_div8_clk = {
3134 .halt_reg = 0x2d050,
3135 .clkr = {
3136 .enable_reg = 0x2d050,
3137 .enable_mask = BIT(0),
3138 .hw.init = &(const struct clk_init_data) {
3139 .name = "gcc_qdss_tsctr_div8_clk",
3140 .parent_hws = (const struct clk_hw *[]) {
3141 &qdss_tsctr_div8_clk_src.hw
3142 },
3143 .num_parents = 1,
3144 .flags = CLK_SET_RATE_PARENT,
3145 .ops = &clk_branch2_ops,
3146 },
3147 },
3148 };
3149
3150 static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
3151 .mult = 1,
3152 .div = 16,
3153 .hw.init = &(const struct clk_init_data) {
3154 .name = "qdss_tsctr_div16_clk_src",
3155 .parent_hws = (const struct clk_hw *[]) {
3156 &qdss_tsctr_clk_src.clkr.hw
3157 },
3158 .num_parents = 1,
3159 .ops = &clk_fixed_factor_ops,
3160 },
3161 };
3162
3163 static struct clk_branch gcc_qdss_tsctr_div16_clk = {
3164 .halt_reg = 0x2d054,
3165 .clkr = {
3166 .enable_reg = 0x2d054,
3167 .enable_mask = BIT(0),
3168 .hw.init = &(const struct clk_init_data) {
3169 .name = "gcc_qdss_tsctr_div16_clk",
3170 .parent_hws = (const struct clk_hw *[]) {
3171 &qdss_tsctr_div16_clk_src.hw
3172 },
3173 .num_parents = 1,
3174 .flags = CLK_SET_RATE_PARENT,
3175 .ops = &clk_branch2_ops,
3176 },
3177 },
3178 };
3179
3180 static struct clk_branch gcc_qdss_dap_clk = {
3181 .halt_reg = 0x2d058,
3182 .clkr = {
3183 .enable_reg = 0x2d058,
3184 .enable_mask = BIT(0),
3185 .hw.init = &(const struct clk_init_data) {
3186 .name = "gcc_qdss_dap_clk",
3187 .parent_hws = (const struct clk_hw *[]) {
3188 &qdss_dap_sync_clk_src.hw
3189 },
3190 .num_parents = 1,
3191 .flags = CLK_SET_RATE_PARENT,
3192 .ops = &clk_branch2_ops,
3193 },
3194 },
3195 };
3196
3197 static struct clk_branch gcc_qdss_apb2jtag_clk = {
3198 .halt_reg = 0x2d05c,
3199 .clkr = {
3200 .enable_reg = 0x2d05c,
3201 .enable_mask = BIT(0),
3202 .hw.init = &(const struct clk_init_data) {
3203 .name = "gcc_qdss_apb2jtag_clk",
3204 .parent_hws = (const struct clk_hw *[]) {
3205 &qdss_dap_sync_clk_src.hw
3206 },
3207 .num_parents = 1,
3208 .flags = CLK_SET_RATE_PARENT,
3209 .ops = &clk_branch2_ops,
3210 },
3211 },
3212 };
3213
3214 static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
3215 .mult = 1,
3216 .div = 3,
3217 .hw.init = &(const struct clk_init_data) {
3218 .name = "qdss_tsctr_div3_clk_src",
3219 .parent_hws = (const struct clk_hw *[]) {
3220 &qdss_tsctr_clk_src.clkr.hw
3221 },
3222 .num_parents = 1,
3223 .ops = &clk_fixed_factor_ops,
3224 },
3225 };
3226
3227 static struct clk_branch gcc_qdss_tsctr_div3_clk = {
3228 .halt_reg = 0x2d048,
3229 .clkr = {
3230 .enable_reg = 0x2d048,
3231 .enable_mask = BIT(0),
3232 .hw.init = &(const struct clk_init_data) {
3233 .name = "gcc_qdss_tsctr_div3_clk",
3234 .parent_hws = (const struct clk_hw *[]) {
3235 &qdss_tsctr_div3_clk_src.hw
3236 },
3237 .num_parents = 1,
3238 .flags = CLK_SET_RATE_PARENT,
3239 .ops = &clk_branch2_ops,
3240 },
3241 },
3242 };
3243
3244 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
3245 F(24000000, P_XO, 1, 0, 0),
3246 F(100000000, P_GPLL0, 8, 0, 0),
3247 F(200000000, P_GPLL0, 4, 0, 0),
3248 F(320000000, P_GPLL0, 2.5, 0, 0),
3249 F(400000000, P_GPLL0, 2, 0, 0),
3250 { }
3251 };
3252
3253 static struct clk_rcg2 qpic_io_macro_clk_src = {
3254 .cmd_rcgr = 0x32004,
3255 .freq_tbl = ftbl_qpic_io_macro_clk_src,
3256 .hid_width = 5,
3257 .parent_map = gcc_xo_gpll0_gpll2_map,
3258 .clkr.hw.init = &(const struct clk_init_data) {
3259 .name = "qpic_io_macro_clk_src",
3260 .parent_data = gcc_xo_gpll0_gpll2,
3261 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
3262 .ops = &clk_rcg2_ops,
3263 },
3264 };
3265
3266 static struct clk_branch gcc_qpic_io_macro_clk = {
3267 .halt_reg = 0x3200c,
3268 .clkr = {
3269 .enable_reg = 0x3200c,
3270 .enable_mask = BIT(0),
3271 .hw.init = &(const struct clk_init_data){
3272 .name = "gcc_qpic_io_macro_clk",
3273 .parent_hws = (const struct clk_hw *[]){
3274 &qpic_io_macro_clk_src.clkr.hw
3275 },
3276 .num_parents = 1,
3277 .flags = CLK_SET_RATE_PARENT,
3278 .ops = &clk_branch2_ops,
3279 },
3280 },
3281 };
3282
3283 static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
3284 F(533333333, P_GPLL0, 1.5, 0, 0),
3285 { }
3286 };
3287
3288 static struct clk_rcg2 q6_axi_clk_src = {
3289 .cmd_rcgr = 0x25004,
3290 .freq_tbl = ftbl_q6_axi_clk_src,
3291 .hid_width = 5,
3292 .parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
3293 .clkr.hw.init = &(const struct clk_init_data) {
3294 .name = "q6_axi_clk_src",
3295 .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
3296 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
3297 .ops = &clk_rcg2_ops,
3298 },
3299 };
3300
3301 static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
3302 F(342857143, P_GPLL4, 3.5, 0, 0),
3303 { }
3304 };
3305
3306 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
3307 { P_XO, 0 },
3308 { P_GPLL0, 1 },
3309 { P_GPLL4, 2 },
3310 { P_BIAS_PLL_UBI_NC_CLK, 4 },
3311 };
3312
3313 static struct clk_rcg2 q6_axim2_clk_src = {
3314 .cmd_rcgr = 0x25028,
3315 .freq_tbl = ftbl_q6_axim2_clk_src,
3316 .hid_width = 5,
3317 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
3318 .clkr.hw.init = &(const struct clk_init_data) {
3319 .name = "q6_axim2_clk_src",
3320 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
3321 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
3322 .ops = &clk_rcg2_ops,
3323 },
3324 };
3325
3326 static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
3327 F(533333333, P_GPLL0, 1.5, 0, 0),
3328 { }
3329 };
3330
3331 static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
3332 .cmd_rcgr = 0x17004,
3333 .freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
3334 .hid_width = 5,
3335 .parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
3336 .clkr.hw.init = &(const struct clk_init_data) {
3337 .name = "nssnoc_memnoc_bfdcd_clk_src",
3338 .parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
3339 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
3340 .ops = &clk_rcg2_ops,
3341 },
3342 };
3343
3344 static struct clk_branch gcc_nssnoc_memnoc_clk = {
3345 .halt_reg = 0x17024,
3346 .clkr = {
3347 .enable_reg = 0x17024,
3348 .enable_mask = BIT(0),
3349 .hw.init = &(const struct clk_init_data) {
3350 .name = "gcc_nssnoc_memnoc_clk",
3351 .parent_hws = (const struct clk_hw *[]) {
3352 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3353 },
3354 .num_parents = 1,
3355 .flags = CLK_SET_RATE_PARENT,
3356 .ops = &clk_branch2_ops,
3357 },
3358 },
3359 };
3360
3361 static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
3362 .halt_reg = 0x17084,
3363 .clkr = {
3364 .enable_reg = 0x17084,
3365 .enable_mask = BIT(0),
3366 .hw.init = &(const struct clk_init_data) {
3367 .name = "gcc_nssnoc_mem_noc_1_clk",
3368 .parent_hws = (const struct clk_hw *[]) {
3369 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3370 },
3371 .num_parents = 1,
3372 .flags = CLK_SET_RATE_PARENT,
3373 .ops = &clk_branch2_ops,
3374 },
3375 },
3376 };
3377
3378 static struct clk_branch gcc_nss_tbu_clk = {
3379 .halt_reg = 0x12040,
3380 .clkr = {
3381 .enable_reg = 0xb00c,
3382 .enable_mask = BIT(4),
3383 .hw.init = &(const struct clk_init_data) {
3384 .name = "gcc_nss_tbu_clk",
3385 .parent_hws = (const struct clk_hw *[]) {
3386 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3387 },
3388 .num_parents = 1,
3389 .flags = CLK_SET_RATE_PARENT,
3390 .ops = &clk_branch2_ops,
3391 },
3392 },
3393 };
3394
3395 static struct clk_branch gcc_mem_noc_nssnoc_clk = {
3396 .halt_reg = 0x19014,
3397 .clkr = {
3398 .enable_reg = 0x19014,
3399 .enable_mask = BIT(0),
3400 .hw.init = &(const struct clk_init_data) {
3401 .name = "gcc_mem_noc_nssnoc_clk",
3402 .parent_hws = (const struct clk_hw *[]) {
3403 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3404 },
3405 .num_parents = 1,
3406 .flags = CLK_SET_RATE_PARENT,
3407 .ops = &clk_branch2_ops,
3408 },
3409 },
3410 };
3411
3412 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
3413 F(133333333, P_GPLL0, 6, 0, 0),
3414 { }
3415 };
3416
3417 static struct clk_rcg2 lpass_axim_clk_src = {
3418 .cmd_rcgr = 0x2700c,
3419 .freq_tbl = ftbl_lpass_axim_clk_src,
3420 .hid_width = 5,
3421 .parent_map = gcc_xo_gpll0_map,
3422 .clkr.hw.init = &(const struct clk_init_data) {
3423 .name = "lpass_axim_clk_src",
3424 .parent_data = gcc_xo_gpll0,
3425 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3426 .ops = &clk_rcg2_ops,
3427 },
3428 };
3429
3430 static struct clk_rcg2 lpass_sway_clk_src = {
3431 .cmd_rcgr = 0x27004,
3432 .freq_tbl = ftbl_lpass_axim_clk_src,
3433 .hid_width = 5,
3434 .parent_map = gcc_xo_gpll0_map,
3435 .clkr.hw.init = &(const struct clk_init_data) {
3436 .name = "lpass_sway_clk_src",
3437 .parent_data = gcc_xo_gpll0,
3438 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3439 .ops = &clk_rcg2_ops,
3440 },
3441 };
3442
3443 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
3444 F(24000000, P_XO, 1, 0, 0),
3445 F(100000000, P_GPLL0, 8, 0, 0),
3446 { }
3447 };
3448
3449 static struct clk_rcg2 adss_pwm_clk_src = {
3450 .cmd_rcgr = 0x1c004,
3451 .freq_tbl = ftbl_adss_pwm_clk_src,
3452 .hid_width = 5,
3453 .parent_map = gcc_xo_gpll0_map,
3454 .clkr.hw.init = &(const struct clk_init_data) {
3455 .name = "adss_pwm_clk_src",
3456 .parent_data = gcc_xo_gpll0,
3457 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3458 .ops = &clk_rcg2_ops,
3459 },
3460 };
3461
3462 static struct clk_branch gcc_adss_pwm_clk = {
3463 .halt_reg = 0x1c00c,
3464 .clkr = {
3465 .enable_reg = 0x1c00c,
3466 .enable_mask = BIT(0),
3467 .hw.init = &(const struct clk_init_data) {
3468 .name = "gcc_adss_pwm_clk",
3469 .parent_hws = (const struct clk_hw *[]) {
3470 &adss_pwm_clk_src.clkr.hw
3471 },
3472 .num_parents = 1,
3473 .flags = CLK_SET_RATE_PARENT,
3474 .ops = &clk_branch2_ops,
3475 },
3476 },
3477 };
3478
3479 static const struct freq_tbl ftbl_gp1_clk_src[] = {
3480 F(24000000, P_XO, 1, 0, 0),
3481 F(200000000, P_GPLL0, 4, 0, 0),
3482 { }
3483 };
3484
3485 static struct clk_rcg2 gp1_clk_src = {
3486 .cmd_rcgr = 0x8004,
3487 .freq_tbl = ftbl_gp1_clk_src,
3488 .hid_width = 5,
3489 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3490 .clkr.hw.init = &(const struct clk_init_data) {
3491 .name = "gp1_clk_src",
3492 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3493 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3494 .ops = &clk_rcg2_ops,
3495 },
3496 };
3497
3498 static struct clk_rcg2 gp2_clk_src = {
3499 .cmd_rcgr = 0x9004,
3500 .freq_tbl = ftbl_gp1_clk_src,
3501 .hid_width = 5,
3502 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3503 .clkr.hw.init = &(const struct clk_init_data) {
3504 .name = "gp2_clk_src",
3505 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3506 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3507 .ops = &clk_rcg2_ops,
3508 },
3509 };
3510
3511 static struct clk_rcg2 gp3_clk_src = {
3512 .cmd_rcgr = 0xa004,
3513 .freq_tbl = ftbl_gp1_clk_src,
3514 .hid_width = 5,
3515 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3516 .clkr.hw.init = &(const struct clk_init_data) {
3517 .name = "gp3_clk_src",
3518 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3519 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3520 .ops = &clk_rcg2_ops,
3521 },
3522 };
3523
3524 static struct clk_branch gcc_xo_clk_src = {
3525 .halt_reg = 0x34004,
3526 .clkr = {
3527 .enable_reg = 0x34004,
3528 .enable_mask = BIT(1),
3529 .hw.init = &(const struct clk_init_data) {
3530 .name = "gcc_xo_clk_src",
3531 .parent_data = gcc_xo_data,
3532 .num_parents = ARRAY_SIZE(gcc_xo_data),
3533 .flags = CLK_SET_RATE_PARENT,
3534 .ops = &clk_branch2_ops,
3535 },
3536 },
3537 };
3538
3539 static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
3540 .halt_reg = 0x17074,
3541 .clkr = {
3542 .enable_reg = 0x17074,
3543 .enable_mask = BIT(0),
3544 .hw.init = &(const struct clk_init_data) {
3545 .name = "gcc_nssnoc_xo_dcd_clk",
3546 .parent_hws = (const struct clk_hw *[]) {
3547 &gcc_xo_clk_src.clkr.hw
3548 },
3549 .num_parents = 1,
3550 .flags = CLK_SET_RATE_PARENT,
3551 .ops = &clk_branch2_ops,
3552 },
3553 },
3554 };
3555
3556 static struct clk_branch gcc_xo_clk = {
3557 .halt_reg = 0x34018,
3558 .clkr = {
3559 .enable_reg = 0x34018,
3560 .enable_mask = BIT(0),
3561 .hw.init = &(const struct clk_init_data) {
3562 .name = "gcc_xo_clk",
3563 .parent_hws = (const struct clk_hw *[]) {
3564 &gcc_xo_clk_src.clkr.hw
3565 },
3566 .num_parents = 1,
3567 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3568 .ops = &clk_branch2_ops,
3569 },
3570 },
3571 };
3572
3573 static struct clk_branch gcc_uniphy0_sys_clk = {
3574 .halt_reg = 0x17048,
3575 .clkr = {
3576 .enable_reg = 0x17048,
3577 .enable_mask = BIT(0),
3578 .hw.init = &(const struct clk_init_data) {
3579 .name = "gcc_uniphy0_sys_clk",
3580 .parent_hws = (const struct clk_hw *[]) {
3581 &uniphy_sys_clk_src.clkr.hw
3582 },
3583 .num_parents = 1,
3584 .flags = CLK_SET_RATE_PARENT,
3585 .ops = &clk_branch2_ops,
3586 },
3587 },
3588 };
3589
3590 static struct clk_branch gcc_uniphy1_sys_clk = {
3591 .halt_reg = 0x17058,
3592 .clkr = {
3593 .enable_reg = 0x17058,
3594 .enable_mask = BIT(0),
3595 .hw.init = &(const struct clk_init_data) {
3596 .name = "gcc_uniphy1_sys_clk",
3597 .parent_hws = (const struct clk_hw *[]) {
3598 &uniphy_sys_clk_src.clkr.hw
3599 },
3600 .num_parents = 1,
3601 .flags = CLK_SET_RATE_PARENT,
3602 .ops = &clk_branch2_ops,
3603 },
3604 },
3605 };
3606
3607 static struct clk_branch gcc_uniphy2_sys_clk = {
3608 .halt_reg = 0x17068,
3609 .clkr = {
3610 .enable_reg = 0x17068,
3611 .enable_mask = BIT(0),
3612 .hw.init = &(const struct clk_init_data) {
3613 .name = "gcc_uniphy2_sys_clk",
3614 .parent_hws = (const struct clk_hw *[]) {
3615 &uniphy_sys_clk_src.clkr.hw
3616 },
3617 .num_parents = 1,
3618 .flags = CLK_SET_RATE_PARENT,
3619 .ops = &clk_branch2_ops,
3620 },
3621 },
3622 };
3623
3624 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3625 .halt_reg = 0x3a008,
3626 .clkr = {
3627 .enable_reg = 0x3a008,
3628 .enable_mask = BIT(0),
3629 .hw.init = &(const struct clk_init_data) {
3630 .name = "gcc_cmn_12gpll_sys_clk",
3631 .parent_hws = (const struct clk_hw *[]) {
3632 &uniphy_sys_clk_src.clkr.hw
3633 },
3634 .num_parents = 1,
3635 .flags = CLK_SET_RATE_PARENT,
3636 .ops = &clk_branch2_ops,
3637 },
3638 },
3639 };
3640
3641 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
3642 .mult = 1,
3643 .div = 4,
3644 .hw.init = &(const struct clk_init_data) {
3645 .name = "gcc_xo_div4_clk_src",
3646 .parent_hws = (const struct clk_hw *[]) {
3647 &gcc_xo_clk_src.clkr.hw
3648 },
3649 .num_parents = 1,
3650 .flags = CLK_SET_RATE_PARENT,
3651 .ops = &clk_fixed_factor_ops,
3652 },
3653 };
3654
3655 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3656 .halt_reg = 0x1701c,
3657 .clkr = {
3658 .enable_reg = 0x1701c,
3659 .enable_mask = BIT(0),
3660 .hw.init = &(const struct clk_init_data) {
3661 .name = "gcc_nssnoc_qosgen_ref_clk",
3662 .parent_hws = (const struct clk_hw *[]) {
3663 &gcc_xo_div4_clk_src.hw
3664 },
3665 .num_parents = 1,
3666 .flags = CLK_SET_RATE_PARENT,
3667 .ops = &clk_branch2_ops,
3668 },
3669 },
3670 };
3671
3672 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3673 .halt_reg = 0x17020,
3674 .clkr = {
3675 .enable_reg = 0x17020,
3676 .enable_mask = BIT(0),
3677 .hw.init = &(const struct clk_init_data) {
3678 .name = "gcc_nssnoc_timeout_ref_clk",
3679 .parent_hws = (const struct clk_hw *[]) {
3680 &gcc_xo_div4_clk_src.hw
3681 },
3682 .num_parents = 1,
3683 .flags = CLK_SET_RATE_PARENT,
3684 .ops = &clk_branch2_ops,
3685 },
3686 },
3687 };
3688
3689 static struct clk_branch gcc_xo_div4_clk = {
3690 .halt_reg = 0x3401c,
3691 .clkr = {
3692 .enable_reg = 0x3401c,
3693 .enable_mask = BIT(0),
3694 .hw.init = &(const struct clk_init_data) {
3695 .name = "gcc_xo_div4_clk",
3696 .parent_hws = (const struct clk_hw *[]) {
3697 &gcc_xo_div4_clk_src.hw
3698 },
3699 .num_parents = 1,
3700 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3701 .ops = &clk_branch2_ops,
3702 },
3703 },
3704 };
3705
3706 static struct clk_hw *gcc_ipq9574_hws[] = {
3707 &gpll0_out_main_div2.hw,
3708 &gcc_xo_div4_clk_src.hw,
3709 &qdss_dap_sync_clk_src.hw,
3710 &qdss_tsctr_div2_clk_src.hw,
3711 &qdss_tsctr_div8_clk_src.hw,
3712 &qdss_tsctr_div16_clk_src.hw,
3713 &qdss_tsctr_div3_clk_src.hw,
3714 &gcc_eud_at_div_clk_src.hw,
3715 };
3716
3717 static struct clk_regmap *gcc_ipq9574_clks[] = {
3718 [GPLL0_MAIN] = &gpll0_main.clkr,
3719 [GPLL0] = &gpll0.clkr,
3720 [GPLL4_MAIN] = &gpll4_main.clkr,
3721 [GPLL4] = &gpll4.clkr,
3722 [GPLL2_MAIN] = &gpll2_main.clkr,
3723 [GPLL2] = &gpll2.clkr,
3724 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3725 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3726 [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
3727 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3728 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3729 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3730 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3731 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3732 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3733 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3734 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3735 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3736 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3737 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3738 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3739 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3740 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3741 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3742 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3743 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3744 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3745 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3746 [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3747 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3748 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3749 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3750 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3751 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3752 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3753 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3754 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3755 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3756 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3757 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3758 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3759 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3760 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3761 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3762 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3763 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3764 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3765 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3766 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3767 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3768 [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
3769 [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
3770 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3771 [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
3772 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3773 [PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
3774 [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
3775 [PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
3776 [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
3777 [PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
3778 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3779 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3780 [PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
3781 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3782 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3783 [PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
3784 [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
3785 [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
3786 [PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
3787 [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
3788 [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
3789 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
3790 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
3791 [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
3792 [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
3793 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3794 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3795 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3796 [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
3797 [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
3798 [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
3799 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
3800 [PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
3801 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
3802 [PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
3803 [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
3804 [PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
3805 [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
3806 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3807 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3808 [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
3809 [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
3810 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
3811 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3812 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
3813 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3814 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
3815 [GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
3816 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
3817 [USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
3818 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3819 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
3820 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3821 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3822 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3823 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3824 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3825 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3826 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3827 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3828 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3829 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
3830 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
3831 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
3832 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
3833 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3834 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3835 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3836 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3837 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3838 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
3839 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3840 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
3841 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
3842 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
3843 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
3844 [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
3845 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3846 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
3847 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
3848 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3849 [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
3850 [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
3851 [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
3852 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
3853 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3854 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
3855 [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
3856 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3857 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3858 [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
3859 [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
3860 [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
3861 [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
3862 [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
3863 [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
3864 [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
3865 [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
3866 [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
3867 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
3868 [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
3869 [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
3870 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3871 [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
3872 [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
3873 [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
3874 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3875 [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
3876 [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
3877 [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
3878 [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
3879 [GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
3880 [GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
3881 [GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
3882 [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
3883 [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
3884 [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
3885 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3886 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3887 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3888 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3889 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3890 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
3891 [GCC_XO_CLK] = &gcc_xo_clk.clkr,
3892 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
3893 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
3894 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
3895 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
3896 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
3897 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
3898 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
3899 [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
3900 [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
3901 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
3902 [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
3903 [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
3904 [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
3905 [GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
3906 [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
3907 [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
3908 [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
3909 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
3910 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
3911 [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
3912 [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
3913 [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
3914 };
3915
3916 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
3917 [GCC_ADSS_BCR] = { 0x1c000, 0 },
3918 [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
3919 [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
3920 [GCC_ANOC_BCR] = { 0x2e074, 0 },
3921 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
3922 [GCC_APSS_TCU_BCR] = { 0x12014, 0 },
3923 [GCC_BLSP1_BCR] = { 0x01000, 0 },
3924 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3925 [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
3926 [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
3927 [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
3928 [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
3929 [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
3930 [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
3931 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3932 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
3933 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
3934 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
3935 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
3936 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
3937 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
3938 [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
3939 [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
3940 [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
3941 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3942 [GCC_DCC_BCR] = { 0x35000, 0 },
3943 [GCC_DDRSS_BCR] = { 0x11000, 0 },
3944 [GCC_IMEM_BCR] = { 0x0e000, 0 },
3945 [GCC_LPASS_BCR] = { 0x27000, 0 },
3946 [GCC_MDIO_BCR] = { 0x1703c, 0 },
3947 [GCC_MPM_BCR] = { 0x37000, 0 },
3948 [GCC_MSG_RAM_BCR] = { 0x26000, 0 },
3949 [GCC_NSS_BCR] = { 0x17000, 0 },
3950 [GCC_NSS_TBU_BCR] = { 0x12044, 0 },
3951 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
3952 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
3953 [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 },
3954 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 },
3955 [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
3956 [GCC_NSSCC_ARES] = { 0x17038, 8 },
3957 [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
3958 [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
3959 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
3960 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
3961 [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
3962 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
3963 [GCC_NSS_CFG_ARES] = { 0x17038, 1 },
3964 [GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
3965 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
3966 [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
3967 [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
3968 [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
3969 [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
3970 [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
3971 [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3972 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
3973 [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
3974 [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
3975 [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
3976 [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
3977 [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
3978 [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
3979 [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3980 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
3981 [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
3982 [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
3983 [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
3984 [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
3985 [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
3986 [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
3987 [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3988 [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
3989 [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
3990 [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
3991 [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
3992 [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
3993 [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
3994 [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
3995 [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
3996 [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
3997 [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
3998 [GCC_PCIE0_BCR] = { 0x28000, 0 },
3999 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4000 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4001 [GCC_PCIE1_BCR] = { 0x29000, 0 },
4002 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4003 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4004 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4005 [GCC_PCIE2_BCR] = { 0x2a000, 0 },
4006 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4007 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4008 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4009 [GCC_PCIE3_BCR] = { 0x2b000, 0 },
4010 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4011 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4012 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4013 [GCC_PCNOC_BCR] = { 0x31000, 0 },
4014 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4015 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4016 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4017 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4018 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4019 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4020 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4021 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4022 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4023 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4024 [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4025 [GCC_PRNG_BCR] = { 0x13020, 0 },
4026 [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4027 [GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4028 [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4029 [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4030 [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4031 [GCC_QDSS_BCR] = { 0x2d000, 0 },
4032 [GCC_QPIC_BCR] = { 0x32000, 0 },
4033 [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4034 [GCC_QPIC_ARES] = { 0x3201c, 0 },
4035 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4036 [GCC_RBCPR_BCR] = { 0x39000, 0 },
4037 [GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4038 [GCC_SDCC_BCR] = { 0x33000, 0 },
4039 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4040 [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4041 [GCC_SNOC_BCR] = { 0x2e000, 0 },
4042 [GCC_SPDM_BCR] = { 0x36000, 0 },
4043 [GCC_TCSR_BCR] = { 0x3d000, 0 },
4044 [GCC_TLMM_BCR] = { 0x3e000, 0 },
4045 [GCC_TME_BCR] = { 0x10000, 0 },
4046 [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4047 [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4048 [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4049 [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4050 [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4051 [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4052 [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4053 [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4054 [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4055 [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4056 [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4057 [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4058 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4059 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4060 [GCC_USB_BCR] = { 0x2c000, 0 },
4061 [GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4062 [GCC_WCSSAON_RESET] = { 0x25074, 0 },
4063 [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4064 [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4065 [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4066 [GCC_WCSS_BCR] = { 0x18004, 0 },
4067 [GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4068 [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4069 [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4070 [GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4071 [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4072 };
4073
4074 #define IPQ_APPS_ID 9574 /* some unique value */
4075
4076 static const struct qcom_icc_hws_data icc_ipq9574_hws[] = {
4077 { MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
4078 { MASTER_SNOC_PCIE0, SLAVE_SNOC_PCIE0, GCC_SNOC_PCIE0_1LANE_S_CLK },
4079 { MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK },
4080 { MASTER_SNOC_PCIE1, SLAVE_SNOC_PCIE1, GCC_SNOC_PCIE1_1LANE_S_CLK },
4081 { MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
4082 { MASTER_SNOC_PCIE2, SLAVE_SNOC_PCIE2, GCC_SNOC_PCIE2_2LANE_S_CLK },
4083 { MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
4084 { MASTER_SNOC_PCIE3, SLAVE_SNOC_PCIE3, GCC_SNOC_PCIE3_2LANE_S_CLK },
4085 { MASTER_USB, SLAVE_USB, GCC_SNOC_USB_CLK },
4086 { MASTER_USB_AXI, SLAVE_USB_AXI, GCC_ANOC_USB_AXI_CLK },
4087 { MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
4088 { MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
4089 { MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
4090 { MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
4091 { MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
4092 { MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
4093 { MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
4094 { MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
4095 { MASTER_MEM_NOC_NSSNOC, SLAVE_MEM_NOC_NSSNOC, GCC_MEM_NOC_NSSNOC_CLK },
4096 { MASTER_NSSNOC_MEMNOC, SLAVE_NSSNOC_MEMNOC, GCC_NSSNOC_MEMNOC_CLK },
4097 { MASTER_NSSNOC_MEM_NOC_1, SLAVE_NSSNOC_MEM_NOC_1, GCC_NSSNOC_MEM_NOC_1_CLK },
4098 };
4099
4100 static const struct of_device_id gcc_ipq9574_match_table[] = {
4101 { .compatible = "qcom,ipq9574-gcc" },
4102 { }
4103 };
4104 MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
4105
4106 static const struct regmap_config gcc_ipq9574_regmap_config = {
4107 .reg_bits = 32,
4108 .reg_stride = 4,
4109 .val_bits = 32,
4110 .max_register = 0x7fffc,
4111 .fast_io = true,
4112 };
4113
4114 static const struct qcom_cc_desc gcc_ipq9574_desc = {
4115 .config = &gcc_ipq9574_regmap_config,
4116 .clks = gcc_ipq9574_clks,
4117 .num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
4118 .resets = gcc_ipq9574_resets,
4119 .num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
4120 .clk_hws = gcc_ipq9574_hws,
4121 .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
4122 .icc_hws = icc_ipq9574_hws,
4123 .num_icc_hws = ARRAY_SIZE(icc_ipq9574_hws),
4124 .icc_first_node_id = IPQ_APPS_ID,
4125 };
4126
gcc_ipq9574_probe(struct platform_device * pdev)4127 static int gcc_ipq9574_probe(struct platform_device *pdev)
4128 {
4129 return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
4130 }
4131
4132 static struct platform_driver gcc_ipq9574_driver = {
4133 .probe = gcc_ipq9574_probe,
4134 .driver = {
4135 .name = "qcom,gcc-ipq9574",
4136 .of_match_table = gcc_ipq9574_match_table,
4137 .sync_state = icc_sync_state,
4138 },
4139 };
4140
gcc_ipq9574_init(void)4141 static int __init gcc_ipq9574_init(void)
4142 {
4143 return platform_driver_register(&gcc_ipq9574_driver);
4144 }
4145 core_initcall(gcc_ipq9574_init);
4146
gcc_ipq9574_exit(void)4147 static void __exit gcc_ipq9574_exit(void)
4148 {
4149 platform_driver_unregister(&gcc_ipq9574_driver);
4150 }
4151 module_exit(gcc_ipq9574_exit);
4152
4153 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
4154 MODULE_LICENSE("GPL");
4155