1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap-divider.h"
18 #include "common.h"
19 #include "gdsc.h"
20
21 enum {
22 P_BI_TCXO,
23 P_DISP_CC_PLL0_OUT_EVEN,
24 P_DISP_CC_PLL0_OUT_MAIN,
25 P_DP_PHY_PLL_LINK_CLK,
26 P_DP_PHY_PLL_VCO_DIV_CLK,
27 P_DSI0_PHY_PLL_OUT_BYTECLK,
28 P_DSI0_PHY_PLL_OUT_DSICLK,
29 P_EDP_PHY_PLL_LINK_CLK,
30 P_EDP_PHY_PLL_VCO_DIV_CLK,
31 P_GCC_DISP_GPLL0_CLK,
32 };
33
34 static const struct pll_vco lucid_vco[] = {
35 { 249600000, 2000000000, 0 },
36 };
37
38 /* 1520MHz Configuration*/
39 static const struct alpha_pll_config disp_cc_pll0_config = {
40 .l = 0x4F,
41 .alpha = 0x2AAA,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002261,
44 .config_ctl_hi1_val = 0x329A299C,
45 .user_ctl_val = 0x00000001,
46 .user_ctl_hi_val = 0x00000805,
47 .user_ctl_hi1_val = 0x00000000,
48 };
49
50 static struct clk_alpha_pll disp_cc_pll0 = {
51 .offset = 0x0,
52 .vco_table = lucid_vco,
53 .num_vco = ARRAY_SIZE(lucid_vco),
54 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
55 .clkr = {
56 .hw.init = &(struct clk_init_data){
57 .name = "disp_cc_pll0",
58 .parent_data = &(const struct clk_parent_data){
59 .fw_name = "bi_tcxo",
60 },
61 .num_parents = 1,
62 .ops = &clk_alpha_pll_lucid_ops,
63 },
64 },
65 };
66
67 static const struct parent_map disp_cc_parent_map_0[] = {
68 { P_BI_TCXO, 0 },
69 };
70
71 static const struct clk_parent_data disp_cc_parent_data_0[] = {
72 { .fw_name = "bi_tcxo" },
73 };
74
75 static const struct parent_map disp_cc_parent_map_1[] = {
76 { P_BI_TCXO, 0 },
77 { P_DP_PHY_PLL_LINK_CLK, 1 },
78 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
79 };
80
81 static const struct clk_parent_data disp_cc_parent_data_1[] = {
82 { .fw_name = "bi_tcxo" },
83 { .fw_name = "dp_phy_pll_link_clk" },
84 { .fw_name = "dp_phy_pll_vco_div_clk" },
85 };
86
87 static const struct parent_map disp_cc_parent_map_2[] = {
88 { P_BI_TCXO, 0 },
89 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
90 };
91
92 static const struct clk_parent_data disp_cc_parent_data_2[] = {
93 { .fw_name = "bi_tcxo" },
94 { .fw_name = "dsi0_phy_pll_out_byteclk" },
95 };
96
97 static const struct parent_map disp_cc_parent_map_3[] = {
98 { P_BI_TCXO, 0 },
99 { P_EDP_PHY_PLL_LINK_CLK, 1 },
100 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2 },
101 };
102
103 static const struct clk_parent_data disp_cc_parent_data_3[] = {
104 { .fw_name = "bi_tcxo" },
105 { .fw_name = "edp_phy_pll_link_clk" },
106 { .fw_name = "edp_phy_pll_vco_div_clk" },
107 };
108
109 static const struct parent_map disp_cc_parent_map_4[] = {
110 { P_BI_TCXO, 0 },
111 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
112 { P_GCC_DISP_GPLL0_CLK, 4 },
113 { P_DISP_CC_PLL0_OUT_EVEN, 5 },
114 };
115
116 static const struct clk_parent_data disp_cc_parent_data_4[] = {
117 { .fw_name = "bi_tcxo" },
118 { .hw = &disp_cc_pll0.clkr.hw },
119 { .fw_name = "gcc_disp_gpll0_clk" },
120 { .hw = &disp_cc_pll0.clkr.hw },
121 };
122
123 static const struct parent_map disp_cc_parent_map_5[] = {
124 { P_BI_TCXO, 0 },
125 { P_GCC_DISP_GPLL0_CLK, 4 },
126 };
127
128 static const struct clk_parent_data disp_cc_parent_data_5[] = {
129 { .fw_name = "bi_tcxo" },
130 { .fw_name = "gcc_disp_gpll0_clk" },
131 };
132
133 static const struct parent_map disp_cc_parent_map_6[] = {
134 { P_BI_TCXO, 0 },
135 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
136 };
137
138 static const struct clk_parent_data disp_cc_parent_data_6[] = {
139 { .fw_name = "bi_tcxo" },
140 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
141 };
142
143 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
144 F(19200000, P_BI_TCXO, 1, 0, 0),
145 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
146 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
147 { }
148 };
149
150 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
151 .cmd_rcgr = 0x1170,
152 .mnd_width = 0,
153 .hid_width = 5,
154 .parent_map = disp_cc_parent_map_5,
155 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
156 .clkr.hw.init = &(struct clk_init_data){
157 .name = "disp_cc_mdss_ahb_clk_src",
158 .parent_data = disp_cc_parent_data_5,
159 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
160 .ops = &clk_rcg2_shared_ops,
161 },
162 };
163
164 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
165 .cmd_rcgr = 0x10d8,
166 .mnd_width = 0,
167 .hid_width = 5,
168 .parent_map = disp_cc_parent_map_2,
169 .clkr.hw.init = &(struct clk_init_data){
170 .name = "disp_cc_mdss_byte0_clk_src",
171 .parent_data = disp_cc_parent_data_2,
172 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
173 .flags = CLK_SET_RATE_PARENT,
174 .ops = &clk_byte2_ops,
175 },
176 };
177
178 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
179 F(19200000, P_BI_TCXO, 1, 0, 0),
180 { }
181 };
182
183 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
184 .cmd_rcgr = 0x1158,
185 .mnd_width = 0,
186 .hid_width = 5,
187 .parent_map = disp_cc_parent_map_0,
188 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
189 .clkr.hw.init = &(struct clk_init_data){
190 .name = "disp_cc_mdss_dp_aux_clk_src",
191 .parent_data = disp_cc_parent_data_0,
192 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
193 .ops = &clk_rcg2_ops,
194 },
195 };
196
197 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
198 .cmd_rcgr = 0x1128,
199 .mnd_width = 0,
200 .hid_width = 5,
201 .parent_map = disp_cc_parent_map_1,
202 .clkr.hw.init = &(struct clk_init_data){
203 .name = "disp_cc_mdss_dp_crypto_clk_src",
204 .parent_data = disp_cc_parent_data_1,
205 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
206 .ops = &clk_byte2_ops,
207 },
208 };
209
210 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
211 .cmd_rcgr = 0x110c,
212 .mnd_width = 0,
213 .hid_width = 5,
214 .parent_map = disp_cc_parent_map_1,
215 .clkr.hw.init = &(struct clk_init_data){
216 .name = "disp_cc_mdss_dp_link_clk_src",
217 .parent_data = disp_cc_parent_data_1,
218 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
219 .ops = &clk_byte2_ops,
220 },
221 };
222
223 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
224 .cmd_rcgr = 0x1140,
225 .mnd_width = 16,
226 .hid_width = 5,
227 .parent_map = disp_cc_parent_map_1,
228 .clkr.hw.init = &(struct clk_init_data){
229 .name = "disp_cc_mdss_dp_pixel_clk_src",
230 .parent_data = disp_cc_parent_data_1,
231 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
232 .ops = &clk_dp_ops,
233 },
234 };
235
236 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
237 .cmd_rcgr = 0x11d0,
238 .mnd_width = 0,
239 .hid_width = 5,
240 .parent_map = disp_cc_parent_map_0,
241 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
242 .clkr.hw.init = &(struct clk_init_data){
243 .name = "disp_cc_mdss_edp_aux_clk_src",
244 .parent_data = disp_cc_parent_data_0,
245 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
246 .ops = &clk_rcg2_ops,
247 },
248 };
249
250 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
251 .cmd_rcgr = 0x11a0,
252 .mnd_width = 0,
253 .hid_width = 5,
254 .parent_map = disp_cc_parent_map_3,
255 .clkr.hw.init = &(struct clk_init_data){
256 .name = "disp_cc_mdss_edp_link_clk_src",
257 .parent_data = disp_cc_parent_data_3,
258 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
259 .flags = CLK_SET_RATE_PARENT,
260 .ops = &clk_byte2_ops,
261 },
262 };
263
264 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
265 .cmd_rcgr = 0x1188,
266 .mnd_width = 16,
267 .hid_width = 5,
268 .parent_map = disp_cc_parent_map_3,
269 .clkr.hw.init = &(struct clk_init_data){
270 .name = "disp_cc_mdss_edp_pixel_clk_src",
271 .parent_data = disp_cc_parent_data_3,
272 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
273 .ops = &clk_dp_ops,
274 },
275 };
276
277 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
278 .cmd_rcgr = 0x10f4,
279 .mnd_width = 0,
280 .hid_width = 5,
281 .parent_map = disp_cc_parent_map_2,
282 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
283 .clkr.hw.init = &(struct clk_init_data){
284 .name = "disp_cc_mdss_esc0_clk_src",
285 .parent_data = disp_cc_parent_data_2,
286 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
287 .ops = &clk_rcg2_ops,
288 },
289 };
290
291 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
292 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
293 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
294 F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
295 F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
296 F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
297 { }
298 };
299
300 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
301 .cmd_rcgr = 0x1090,
302 .mnd_width = 0,
303 .hid_width = 5,
304 .parent_map = disp_cc_parent_map_4,
305 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
306 .clkr.hw.init = &(struct clk_init_data){
307 .name = "disp_cc_mdss_mdp_clk_src",
308 .parent_data = disp_cc_parent_data_4,
309 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
310 .ops = &clk_rcg2_shared_ops,
311 },
312 };
313
314 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
315 .cmd_rcgr = 0x1078,
316 .mnd_width = 8,
317 .hid_width = 5,
318 .parent_map = disp_cc_parent_map_6,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "disp_cc_mdss_pclk0_clk_src",
321 .parent_data = disp_cc_parent_data_6,
322 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
323 .flags = CLK_SET_RATE_PARENT,
324 .ops = &clk_pixel_ops,
325 },
326 };
327
328 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
329 .cmd_rcgr = 0x10a8,
330 .mnd_width = 0,
331 .hid_width = 5,
332 .parent_map = disp_cc_parent_map_4,
333 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
334 .clkr.hw.init = &(struct clk_init_data){
335 .name = "disp_cc_mdss_rot_clk_src",
336 .parent_data = disp_cc_parent_data_4,
337 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
338 .ops = &clk_rcg2_shared_ops,
339 },
340 };
341
342 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
343 .cmd_rcgr = 0x10c0,
344 .mnd_width = 0,
345 .hid_width = 5,
346 .parent_map = disp_cc_parent_map_0,
347 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
348 .clkr.hw.init = &(struct clk_init_data){
349 .name = "disp_cc_mdss_vsync_clk_src",
350 .parent_data = disp_cc_parent_data_0,
351 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
352 .ops = &clk_rcg2_ops,
353 },
354 };
355
356 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
357 .reg = 0x10f0,
358 .shift = 0,
359 .width = 4,
360 .clkr.hw.init = &(struct clk_init_data) {
361 .name = "disp_cc_mdss_byte0_div_clk_src",
362 .parent_hws = (const struct clk_hw*[]){
363 &disp_cc_mdss_byte0_clk_src.clkr.hw,
364 },
365 .num_parents = 1,
366 .ops = &clk_regmap_div_ops,
367 },
368 };
369
370 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
371 .reg = 0x1124,
372 .shift = 0,
373 .width = 4,
374 .clkr.hw.init = &(struct clk_init_data) {
375 .name = "disp_cc_mdss_dp_link_div_clk_src",
376 .parent_hws = (const struct clk_hw*[]){
377 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
378 },
379 .num_parents = 1,
380 .ops = &clk_regmap_div_ro_ops,
381 },
382 };
383
384 static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
385 .reg = 0x11b8,
386 .shift = 0,
387 .width = 4,
388 .clkr.hw.init = &(struct clk_init_data) {
389 .name = "disp_cc_mdss_edp_link_div_clk_src",
390 .parent_hws = (const struct clk_hw*[]){
391 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
392 },
393 .num_parents = 1,
394 .ops = &clk_regmap_div_ro_ops,
395 },
396 };
397
398 static struct clk_branch disp_cc_mdss_ahb_clk = {
399 .halt_reg = 0x1050,
400 .halt_check = BRANCH_HALT,
401 .clkr = {
402 .enable_reg = 0x1050,
403 .enable_mask = BIT(0),
404 .hw.init = &(struct clk_init_data){
405 .name = "disp_cc_mdss_ahb_clk",
406 .parent_hws = (const struct clk_hw*[]){
407 &disp_cc_mdss_ahb_clk_src.clkr.hw,
408 },
409 .num_parents = 1,
410 .flags = CLK_SET_RATE_PARENT,
411 .ops = &clk_branch2_ops,
412 },
413 },
414 };
415
416 static struct clk_branch disp_cc_mdss_byte0_clk = {
417 .halt_reg = 0x1030,
418 .halt_check = BRANCH_HALT,
419 .clkr = {
420 .enable_reg = 0x1030,
421 .enable_mask = BIT(0),
422 .hw.init = &(struct clk_init_data){
423 .name = "disp_cc_mdss_byte0_clk",
424 .parent_hws = (const struct clk_hw*[]){
425 &disp_cc_mdss_byte0_clk_src.clkr.hw,
426 },
427 .num_parents = 1,
428 .flags = CLK_SET_RATE_PARENT,
429 .ops = &clk_branch2_ops,
430 },
431 },
432 };
433
434 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
435 .halt_reg = 0x1034,
436 .halt_check = BRANCH_HALT,
437 .clkr = {
438 .enable_reg = 0x1034,
439 .enable_mask = BIT(0),
440 .hw.init = &(struct clk_init_data){
441 .name = "disp_cc_mdss_byte0_intf_clk",
442 .parent_hws = (const struct clk_hw*[]){
443 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
444 },
445 .num_parents = 1,
446 .flags = CLK_SET_RATE_PARENT,
447 .ops = &clk_branch2_ops,
448 },
449 },
450 };
451
452 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
453 .halt_reg = 0x104c,
454 .halt_check = BRANCH_HALT,
455 .clkr = {
456 .enable_reg = 0x104c,
457 .enable_mask = BIT(0),
458 .hw.init = &(struct clk_init_data){
459 .name = "disp_cc_mdss_dp_aux_clk",
460 .parent_hws = (const struct clk_hw*[]){
461 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
462 },
463 .num_parents = 1,
464 .flags = CLK_SET_RATE_PARENT,
465 .ops = &clk_branch2_ops,
466 },
467 },
468 };
469
470 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
471 .halt_reg = 0x1044,
472 .halt_check = BRANCH_HALT,
473 .clkr = {
474 .enable_reg = 0x1044,
475 .enable_mask = BIT(0),
476 .hw.init = &(struct clk_init_data){
477 .name = "disp_cc_mdss_dp_crypto_clk",
478 .parent_hws = (const struct clk_hw*[]){
479 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
480 },
481 .num_parents = 1,
482 .flags = CLK_SET_RATE_PARENT,
483 .ops = &clk_branch2_ops,
484 },
485 },
486 };
487
488 static struct clk_branch disp_cc_mdss_dp_link_clk = {
489 .halt_reg = 0x103c,
490 .halt_check = BRANCH_HALT,
491 .clkr = {
492 .enable_reg = 0x103c,
493 .enable_mask = BIT(0),
494 .hw.init = &(struct clk_init_data){
495 .name = "disp_cc_mdss_dp_link_clk",
496 .parent_hws = (const struct clk_hw*[]){
497 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
498 },
499 .num_parents = 1,
500 .flags = CLK_SET_RATE_PARENT,
501 .ops = &clk_branch2_ops,
502 },
503 },
504 };
505
506 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
507 .halt_reg = 0x1040,
508 .halt_check = BRANCH_HALT,
509 .clkr = {
510 .enable_reg = 0x1040,
511 .enable_mask = BIT(0),
512 .hw.init = &(struct clk_init_data){
513 .name = "disp_cc_mdss_dp_link_intf_clk",
514 .parent_hws = (const struct clk_hw*[]){
515 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
516 },
517 .num_parents = 1,
518 .flags = CLK_SET_RATE_PARENT,
519 .ops = &clk_branch2_ops,
520 },
521 },
522 };
523
524 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
525 .halt_reg = 0x1048,
526 .halt_check = BRANCH_HALT,
527 .clkr = {
528 .enable_reg = 0x1048,
529 .enable_mask = BIT(0),
530 .hw.init = &(struct clk_init_data){
531 .name = "disp_cc_mdss_dp_pixel_clk",
532 .parent_hws = (const struct clk_hw*[]){
533 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
534 },
535 .num_parents = 1,
536 .flags = CLK_SET_RATE_PARENT,
537 .ops = &clk_branch2_ops,
538 },
539 },
540 };
541
542 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
543 .halt_reg = 0x1060,
544 .halt_check = BRANCH_HALT,
545 .clkr = {
546 .enable_reg = 0x1060,
547 .enable_mask = BIT(0),
548 .hw.init = &(struct clk_init_data){
549 .name = "disp_cc_mdss_edp_aux_clk",
550 .parent_hws = (const struct clk_hw*[]){
551 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
552 },
553 .num_parents = 1,
554 .flags = CLK_SET_RATE_PARENT,
555 .ops = &clk_branch2_ops,
556 },
557 },
558 };
559
560 static struct clk_branch disp_cc_mdss_edp_link_clk = {
561 .halt_reg = 0x1058,
562 .halt_check = BRANCH_HALT,
563 .clkr = {
564 .enable_reg = 0x1058,
565 .enable_mask = BIT(0),
566 .hw.init = &(struct clk_init_data){
567 .name = "disp_cc_mdss_edp_link_clk",
568 .parent_hws = (const struct clk_hw*[]){
569 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
570 },
571 .num_parents = 1,
572 .flags = CLK_SET_RATE_PARENT,
573 .ops = &clk_branch2_ops,
574 },
575 },
576 };
577
578 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
579 .halt_reg = 0x105c,
580 .halt_check = BRANCH_HALT,
581 .clkr = {
582 .enable_reg = 0x105c,
583 .enable_mask = BIT(0),
584 .hw.init = &(struct clk_init_data){
585 .name = "disp_cc_mdss_edp_link_intf_clk",
586 .parent_hws = (const struct clk_hw*[]){
587 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw
588 },
589 .num_parents = 1,
590 .flags = CLK_SET_RATE_PARENT,
591 .ops = &clk_branch2_ops,
592 },
593 },
594 };
595
596 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
597 .halt_reg = 0x1054,
598 .halt_check = BRANCH_HALT,
599 .clkr = {
600 .enable_reg = 0x1054,
601 .enable_mask = BIT(0),
602 .hw.init = &(struct clk_init_data){
603 .name = "disp_cc_mdss_edp_pixel_clk",
604 .parent_hws = (const struct clk_hw*[]){
605 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
606 },
607 .num_parents = 1,
608 .flags = CLK_SET_RATE_PARENT,
609 .ops = &clk_branch2_ops,
610 },
611 },
612 };
613
614 static struct clk_branch disp_cc_mdss_esc0_clk = {
615 .halt_reg = 0x1038,
616 .halt_check = BRANCH_HALT,
617 .clkr = {
618 .enable_reg = 0x1038,
619 .enable_mask = BIT(0),
620 .hw.init = &(struct clk_init_data){
621 .name = "disp_cc_mdss_esc0_clk",
622 .parent_hws = (const struct clk_hw*[]){
623 &disp_cc_mdss_esc0_clk_src.clkr.hw,
624 },
625 .num_parents = 1,
626 .flags = CLK_SET_RATE_PARENT,
627 .ops = &clk_branch2_ops,
628 },
629 },
630 };
631
632 static struct clk_branch disp_cc_mdss_mdp_clk = {
633 .halt_reg = 0x1014,
634 .halt_check = BRANCH_HALT,
635 .clkr = {
636 .enable_reg = 0x1014,
637 .enable_mask = BIT(0),
638 .hw.init = &(struct clk_init_data){
639 .name = "disp_cc_mdss_mdp_clk",
640 .parent_hws = (const struct clk_hw*[]){
641 &disp_cc_mdss_mdp_clk_src.clkr.hw,
642 },
643 .num_parents = 1,
644 .flags = CLK_SET_RATE_PARENT,
645 .ops = &clk_branch2_ops,
646 },
647 },
648 };
649
650 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
651 .halt_reg = 0x1024,
652 .halt_check = BRANCH_HALT_VOTED,
653 .clkr = {
654 .enable_reg = 0x1024,
655 .enable_mask = BIT(0),
656 .hw.init = &(struct clk_init_data){
657 .name = "disp_cc_mdss_mdp_lut_clk",
658 .parent_hws = (const struct clk_hw*[]){
659 &disp_cc_mdss_mdp_clk_src.clkr.hw,
660 },
661 .num_parents = 1,
662 .flags = CLK_SET_RATE_PARENT,
663 .ops = &clk_branch2_ops,
664 },
665 },
666 };
667
668 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
669 .halt_reg = 0x2004,
670 .halt_check = BRANCH_HALT_VOTED,
671 .clkr = {
672 .enable_reg = 0x2004,
673 .enable_mask = BIT(0),
674 .hw.init = &(struct clk_init_data){
675 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
676 .parent_hws = (const struct clk_hw*[]){
677 &disp_cc_mdss_ahb_clk_src.clkr.hw,
678 },
679 .num_parents = 1,
680 .flags = CLK_SET_RATE_PARENT,
681 .ops = &clk_branch2_ops,
682 },
683 },
684 };
685
686 static struct clk_branch disp_cc_mdss_pclk0_clk = {
687 .halt_reg = 0x1010,
688 .halt_check = BRANCH_HALT,
689 .clkr = {
690 .enable_reg = 0x1010,
691 .enable_mask = BIT(0),
692 .hw.init = &(struct clk_init_data){
693 .name = "disp_cc_mdss_pclk0_clk",
694 .parent_hws = (const struct clk_hw*[]){
695 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
696 },
697 .num_parents = 1,
698 .flags = CLK_SET_RATE_PARENT,
699 .ops = &clk_branch2_ops,
700 },
701 },
702 };
703
704 static struct clk_branch disp_cc_mdss_rot_clk = {
705 .halt_reg = 0x101c,
706 .halt_check = BRANCH_HALT,
707 .clkr = {
708 .enable_reg = 0x101c,
709 .enable_mask = BIT(0),
710 .hw.init = &(struct clk_init_data){
711 .name = "disp_cc_mdss_rot_clk",
712 .parent_hws = (const struct clk_hw*[]){
713 &disp_cc_mdss_rot_clk_src.clkr.hw,
714 },
715 .num_parents = 1,
716 .flags = CLK_SET_RATE_PARENT,
717 .ops = &clk_branch2_ops,
718 },
719 },
720 };
721
722 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
723 .halt_reg = 0x200c,
724 .halt_check = BRANCH_HALT,
725 .clkr = {
726 .enable_reg = 0x200c,
727 .enable_mask = BIT(0),
728 .hw.init = &(struct clk_init_data){
729 .name = "disp_cc_mdss_rscc_ahb_clk",
730 .parent_hws = (const struct clk_hw*[]){
731 &disp_cc_mdss_ahb_clk_src.clkr.hw,
732 },
733 .num_parents = 1,
734 .flags = CLK_SET_RATE_PARENT,
735 .ops = &clk_branch2_ops,
736 },
737 },
738 };
739
740 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
741 .halt_reg = 0x2008,
742 .halt_check = BRANCH_HALT,
743 .clkr = {
744 .enable_reg = 0x2008,
745 .enable_mask = BIT(0),
746 .hw.init = &(struct clk_init_data){
747 .name = "disp_cc_mdss_rscc_vsync_clk",
748 .parent_hws = (const struct clk_hw*[]){
749 &disp_cc_mdss_vsync_clk_src.clkr.hw,
750 },
751 .num_parents = 1,
752 .flags = CLK_SET_RATE_PARENT,
753 .ops = &clk_branch2_ops,
754 },
755 },
756 };
757
758 static struct clk_branch disp_cc_mdss_vsync_clk = {
759 .halt_reg = 0x102c,
760 .halt_check = BRANCH_HALT,
761 .clkr = {
762 .enable_reg = 0x102c,
763 .enable_mask = BIT(0),
764 .hw.init = &(struct clk_init_data){
765 .name = "disp_cc_mdss_vsync_clk",
766 .parent_hws = (const struct clk_hw*[]){
767 &disp_cc_mdss_vsync_clk_src.clkr.hw,
768 },
769 .num_parents = 1,
770 .flags = CLK_SET_RATE_PARENT,
771 .ops = &clk_branch2_ops,
772 },
773 },
774 };
775
776 static struct clk_branch disp_cc_sleep_clk = {
777 .halt_reg = 0x5004,
778 .halt_check = BRANCH_HALT,
779 .clkr = {
780 .enable_reg = 0x5004,
781 .enable_mask = BIT(0),
782 .hw.init = &(struct clk_init_data){
783 .name = "disp_cc_sleep_clk",
784 .ops = &clk_branch2_ops,
785 },
786 },
787 };
788
789 static struct gdsc disp_cc_mdss_core_gdsc = {
790 .gdscr = 0x1004,
791 .en_rest_wait_val = 0x2,
792 .en_few_wait_val = 0x2,
793 .clk_dis_wait_val = 0xf,
794 .pd = {
795 .name = "disp_cc_mdss_core_gdsc",
796 },
797 .pwrsts = PWRSTS_OFF_ON,
798 .flags = HW_CTRL | RETAIN_FF_ENABLE,
799 };
800
801 static struct clk_regmap *disp_cc_sc7280_clocks[] = {
802 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
803 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
804 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
805 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
806 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
807 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
808 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
809 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
810 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
811 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
812 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
813 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
814 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
815 &disp_cc_mdss_dp_link_div_clk_src.clkr,
816 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
817 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
818 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
819 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
820 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
821 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
822 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
823 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] =
824 &disp_cc_mdss_edp_link_div_clk_src.clkr,
825 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
826 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
827 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
828 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
829 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
830 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
831 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
832 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
833 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
834 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
835 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
836 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
837 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
838 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
839 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
840 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
841 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
842 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
843 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
844 };
845
846 static struct gdsc *disp_cc_sc7280_gdscs[] = {
847 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
848 };
849
850 static const struct regmap_config disp_cc_sc7280_regmap_config = {
851 .reg_bits = 32,
852 .reg_stride = 4,
853 .val_bits = 32,
854 .max_register = 0x10000,
855 .fast_io = true,
856 };
857
858 static const struct qcom_cc_desc disp_cc_sc7280_desc = {
859 .config = &disp_cc_sc7280_regmap_config,
860 .clks = disp_cc_sc7280_clocks,
861 .num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
862 .gdscs = disp_cc_sc7280_gdscs,
863 .num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
864 };
865
866 static const struct of_device_id disp_cc_sc7280_match_table[] = {
867 { .compatible = "qcom,sc7280-dispcc" },
868 { }
869 };
870 MODULE_DEVICE_TABLE(of, disp_cc_sc7280_match_table);
871
disp_cc_sc7280_probe(struct platform_device * pdev)872 static int disp_cc_sc7280_probe(struct platform_device *pdev)
873 {
874 struct regmap *regmap;
875
876 regmap = qcom_cc_map(pdev, &disp_cc_sc7280_desc);
877 if (IS_ERR(regmap))
878 return PTR_ERR(regmap);
879
880 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
881
882 /* Keep some clocks always-on */
883 qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */
884
885 return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap);
886 }
887
888 static struct platform_driver disp_cc_sc7280_driver = {
889 .probe = disp_cc_sc7280_probe,
890 .driver = {
891 .name = "disp_cc-sc7280",
892 .of_match_table = disp_cc_sc7280_match_table,
893 },
894 };
895
896 module_platform_driver(disp_cc_sc7280_driver);
897
898 MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver");
899 MODULE_LICENSE("GPL v2");
900