1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12
13 #include "clk-alpha-pll.h"
14 #include "common.h"
15
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
18 # define PLL_BYPASSNL BIT(1)
19 # define PLL_RESET_N BIT(2)
20 # define PLL_OFFLINE_REQ BIT(7)
21 # define PLL_LOCK_COUNT_SHIFT 8
22 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_SHIFT 14
24 # define PLL_BIAS_COUNT_MASK 0x3f
25 # define PLL_VOTE_FSM_ENA BIT(20)
26 # define PLL_FSM_ENA BIT(20)
27 # define PLL_VOTE_FSM_RESET BIT(21)
28 # define PLL_UPDATE BIT(22)
29 # define PLL_UPDATE_BYPASS BIT(23)
30 # define PLL_FSM_LEGACY_MODE BIT(24)
31 # define PLL_OFFLINE_ACK BIT(28)
32 # define ALPHA_PLL_ACK_LATCH BIT(29)
33 # define PLL_ACTIVE_FLAG BIT(30)
34 # define PLL_LOCK_DET BIT(31)
35
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42 # define PLL_POST_DIV_SHIFT 8
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
44 # define PLL_ALPHA_MSB BIT(15)
45 # define PLL_ALPHA_EN BIT(24)
46 # define PLL_ALPHA_MODE BIT(25)
47 # define PLL_VCO_SHIFT 20
48 # define PLL_VCO_MASK 0x3
49
50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52
53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
61 #define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3])
62 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
65
66 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
67 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
68 [PLL_OFF_L_VAL] = 0x04,
69 [PLL_OFF_ALPHA_VAL] = 0x08,
70 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
71 [PLL_OFF_USER_CTL] = 0x10,
72 [PLL_OFF_USER_CTL_U] = 0x14,
73 [PLL_OFF_CONFIG_CTL] = 0x18,
74 [PLL_OFF_TEST_CTL] = 0x1c,
75 [PLL_OFF_TEST_CTL_U] = 0x20,
76 [PLL_OFF_STATUS] = 0x24,
77 },
78 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
79 [PLL_OFF_L_VAL] = 0x04,
80 [PLL_OFF_ALPHA_VAL] = 0x08,
81 [PLL_OFF_USER_CTL] = 0x10,
82 [PLL_OFF_CONFIG_CTL] = 0x14,
83 [PLL_OFF_CONFIG_CTL_U] = 0x18,
84 [PLL_OFF_TEST_CTL] = 0x1c,
85 [PLL_OFF_TEST_CTL_U] = 0x20,
86 [PLL_OFF_STATUS] = 0x24,
87 },
88 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
89 [PLL_OFF_L_VAL] = 0x08,
90 [PLL_OFF_ALPHA_VAL] = 0x10,
91 [PLL_OFF_USER_CTL] = 0x18,
92 [PLL_OFF_CONFIG_CTL] = 0x20,
93 [PLL_OFF_CONFIG_CTL_U] = 0x24,
94 [PLL_OFF_STATUS] = 0x28,
95 [PLL_OFF_TEST_CTL] = 0x30,
96 [PLL_OFF_TEST_CTL_U] = 0x34,
97 },
98 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
99 [PLL_OFF_L_VAL] = 0x04,
100 [PLL_OFF_ALPHA_VAL] = 0x08,
101 [PLL_OFF_USER_CTL] = 0x0c,
102 [PLL_OFF_CONFIG_CTL] = 0x10,
103 [PLL_OFF_CONFIG_CTL_U] = 0x14,
104 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
105 [PLL_OFF_TEST_CTL] = 0x1c,
106 [PLL_OFF_TEST_CTL_U] = 0x20,
107 [PLL_OFF_TEST_CTL_U1] = 0x24,
108 [PLL_OFF_OPMODE] = 0x28,
109 [PLL_OFF_STATUS] = 0x38,
110 },
111 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
112 [PLL_OFF_L_VAL] = 0x04,
113 [PLL_OFF_ALPHA_VAL] = 0x08,
114 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
115 [PLL_OFF_USER_CTL] = 0x10,
116 [PLL_OFF_CONFIG_CTL] = 0x18,
117 [PLL_OFF_TEST_CTL] = 0x1c,
118 [PLL_OFF_STATUS] = 0x24,
119 },
120 [CLK_ALPHA_PLL_TYPE_FABIA] = {
121 [PLL_OFF_L_VAL] = 0x04,
122 [PLL_OFF_USER_CTL] = 0x0c,
123 [PLL_OFF_USER_CTL_U] = 0x10,
124 [PLL_OFF_CONFIG_CTL] = 0x14,
125 [PLL_OFF_CONFIG_CTL_U] = 0x18,
126 [PLL_OFF_TEST_CTL] = 0x1c,
127 [PLL_OFF_TEST_CTL_U] = 0x20,
128 [PLL_OFF_STATUS] = 0x24,
129 [PLL_OFF_OPMODE] = 0x2c,
130 [PLL_OFF_FRAC] = 0x38,
131 },
132 [CLK_ALPHA_PLL_TYPE_TRION] = {
133 [PLL_OFF_L_VAL] = 0x04,
134 [PLL_OFF_CAL_L_VAL] = 0x08,
135 [PLL_OFF_USER_CTL] = 0x0c,
136 [PLL_OFF_USER_CTL_U] = 0x10,
137 [PLL_OFF_USER_CTL_U1] = 0x14,
138 [PLL_OFF_CONFIG_CTL] = 0x18,
139 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
140 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
141 [PLL_OFF_TEST_CTL] = 0x24,
142 [PLL_OFF_TEST_CTL_U] = 0x28,
143 [PLL_OFF_TEST_CTL_U1] = 0x2c,
144 [PLL_OFF_STATUS] = 0x30,
145 [PLL_OFF_OPMODE] = 0x38,
146 [PLL_OFF_ALPHA_VAL] = 0x40,
147 },
148 [CLK_ALPHA_PLL_TYPE_AGERA] = {
149 [PLL_OFF_L_VAL] = 0x04,
150 [PLL_OFF_ALPHA_VAL] = 0x08,
151 [PLL_OFF_USER_CTL] = 0x0c,
152 [PLL_OFF_CONFIG_CTL] = 0x10,
153 [PLL_OFF_CONFIG_CTL_U] = 0x14,
154 [PLL_OFF_TEST_CTL] = 0x18,
155 [PLL_OFF_TEST_CTL_U] = 0x1c,
156 [PLL_OFF_STATUS] = 0x2c,
157 },
158 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
159 [PLL_OFF_L_VAL] = 0x04,
160 [PLL_OFF_ALPHA_VAL] = 0x08,
161 [PLL_OFF_USER_CTL] = 0x0c,
162 [PLL_OFF_CONFIG_CTL] = 0x10,
163 [PLL_OFF_CONFIG_CTL_U] = 0x14,
164 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
165 [PLL_OFF_TEST_CTL] = 0x1c,
166 [PLL_OFF_TEST_CTL_U] = 0x20,
167 [PLL_OFF_TEST_CTL_U1] = 0x24,
168 [PLL_OFF_OPMODE] = 0x28,
169 [PLL_OFF_STATUS] = 0x38,
170 },
171 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
172 [PLL_OFF_OPMODE] = 0x04,
173 [PLL_OFF_STATUS] = 0x0c,
174 [PLL_OFF_L_VAL] = 0x10,
175 [PLL_OFF_ALPHA_VAL] = 0x14,
176 [PLL_OFF_USER_CTL] = 0x18,
177 [PLL_OFF_USER_CTL_U] = 0x1c,
178 [PLL_OFF_CONFIG_CTL] = 0x20,
179 [PLL_OFF_CONFIG_CTL_U] = 0x24,
180 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
181 [PLL_OFF_TEST_CTL] = 0x2c,
182 [PLL_OFF_TEST_CTL_U] = 0x30,
183 [PLL_OFF_TEST_CTL_U1] = 0x34,
184 },
185 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
186 [PLL_OFF_OPMODE] = 0x04,
187 [PLL_OFF_STATE] = 0x08,
188 [PLL_OFF_STATUS] = 0x0c,
189 [PLL_OFF_L_VAL] = 0x10,
190 [PLL_OFF_ALPHA_VAL] = 0x14,
191 [PLL_OFF_USER_CTL] = 0x18,
192 [PLL_OFF_USER_CTL_U] = 0x1c,
193 [PLL_OFF_CONFIG_CTL] = 0x20,
194 [PLL_OFF_CONFIG_CTL_U] = 0x24,
195 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
196 [PLL_OFF_TEST_CTL] = 0x2c,
197 [PLL_OFF_TEST_CTL_U] = 0x30,
198 [PLL_OFF_TEST_CTL_U1] = 0x34,
199 [PLL_OFF_TEST_CTL_U2] = 0x38,
200 },
201 [CLK_ALPHA_PLL_TYPE_PONGO_ELU] = {
202 [PLL_OFF_OPMODE] = 0x04,
203 [PLL_OFF_STATE] = 0x08,
204 [PLL_OFF_STATUS] = 0x0c,
205 [PLL_OFF_L_VAL] = 0x10,
206 [PLL_OFF_USER_CTL] = 0x14,
207 [PLL_OFF_USER_CTL_U] = 0x18,
208 [PLL_OFF_CONFIG_CTL] = 0x1c,
209 [PLL_OFF_CONFIG_CTL_U] = 0x20,
210 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
211 [PLL_OFF_CONFIG_CTL_U2] = 0x28,
212 [PLL_OFF_TEST_CTL] = 0x2c,
213 [PLL_OFF_TEST_CTL_U] = 0x30,
214 [PLL_OFF_TEST_CTL_U1] = 0x34,
215 [PLL_OFF_TEST_CTL_U2] = 0x38,
216 [PLL_OFF_TEST_CTL_U3] = 0x3c,
217 },
218 [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = {
219 [PLL_OFF_OPMODE] = 0x04,
220 [PLL_OFF_STATE] = 0x08,
221 [PLL_OFF_STATUS] = 0x0c,
222 [PLL_OFF_L_VAL] = 0x10,
223 [PLL_OFF_ALPHA_VAL] = 0x14,
224 [PLL_OFF_USER_CTL] = 0x18,
225 [PLL_OFF_USER_CTL_U] = 0x1c,
226 [PLL_OFF_CONFIG_CTL] = 0x20,
227 [PLL_OFF_CONFIG_CTL_U] = 0x24,
228 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
229 [PLL_OFF_TEST_CTL] = 0x2c,
230 [PLL_OFF_TEST_CTL_U] = 0x30,
231 },
232 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
233 [PLL_OFF_OPMODE] = 0x04,
234 [PLL_OFF_STATUS] = 0x0c,
235 [PLL_OFF_L_VAL] = 0x10,
236 [PLL_OFF_USER_CTL] = 0x14,
237 [PLL_OFF_USER_CTL_U] = 0x18,
238 [PLL_OFF_CONFIG_CTL] = 0x1c,
239 [PLL_OFF_CONFIG_CTL_U] = 0x20,
240 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
241 [PLL_OFF_TEST_CTL] = 0x28,
242 [PLL_OFF_TEST_CTL_U] = 0x2c,
243 },
244 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
245 [PLL_OFF_L_VAL] = 0x04,
246 [PLL_OFF_ALPHA_VAL] = 0x08,
247 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
248 [PLL_OFF_TEST_CTL] = 0x10,
249 [PLL_OFF_TEST_CTL_U] = 0x14,
250 [PLL_OFF_USER_CTL] = 0x18,
251 [PLL_OFF_USER_CTL_U] = 0x1c,
252 [PLL_OFF_CONFIG_CTL] = 0x20,
253 [PLL_OFF_STATUS] = 0x24,
254 },
255 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
256 [PLL_OFF_L_VAL] = 0x04,
257 [PLL_OFF_ALPHA_VAL] = 0x08,
258 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
259 [PLL_OFF_TEST_CTL] = 0x10,
260 [PLL_OFF_TEST_CTL_U] = 0x14,
261 [PLL_OFF_USER_CTL] = 0x18,
262 [PLL_OFF_CONFIG_CTL] = 0x1C,
263 [PLL_OFF_STATUS] = 0x20,
264 },
265 [CLK_ALPHA_PLL_TYPE_STROMER] = {
266 [PLL_OFF_L_VAL] = 0x08,
267 [PLL_OFF_ALPHA_VAL] = 0x10,
268 [PLL_OFF_ALPHA_VAL_U] = 0x14,
269 [PLL_OFF_USER_CTL] = 0x18,
270 [PLL_OFF_USER_CTL_U] = 0x1c,
271 [PLL_OFF_CONFIG_CTL] = 0x20,
272 [PLL_OFF_STATUS] = 0x28,
273 [PLL_OFF_TEST_CTL] = 0x30,
274 [PLL_OFF_TEST_CTL_U] = 0x34,
275 },
276 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
277 [PLL_OFF_L_VAL] = 0x04,
278 [PLL_OFF_USER_CTL] = 0x08,
279 [PLL_OFF_USER_CTL_U] = 0x0c,
280 [PLL_OFF_CONFIG_CTL] = 0x10,
281 [PLL_OFF_TEST_CTL] = 0x14,
282 [PLL_OFF_TEST_CTL_U] = 0x18,
283 [PLL_OFF_STATUS] = 0x1c,
284 [PLL_OFF_ALPHA_VAL] = 0x24,
285 [PLL_OFF_ALPHA_VAL_U] = 0x28,
286 },
287 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
288 [PLL_OFF_L_VAL] = 0x04,
289 [PLL_OFF_ALPHA_VAL] = 0x08,
290 [PLL_OFF_USER_CTL] = 0x0c,
291 [PLL_OFF_USER_CTL_U] = 0x10,
292 [PLL_OFF_CONFIG_CTL] = 0x14,
293 [PLL_OFF_CONFIG_CTL_U] = 0x18,
294 [PLL_OFF_CONFIG_CTL_U1] = 0x1c,
295 [PLL_OFF_CONFIG_CTL_U2] = 0x20,
296 [PLL_OFF_TEST_CTL] = 0x24,
297 [PLL_OFF_TEST_CTL_U] = 0x28,
298 [PLL_OFF_TEST_CTL_U1] = 0x2c,
299 [PLL_OFF_OPMODE] = 0x30,
300 [PLL_OFF_STATUS] = 0x3c,
301 },
302 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
303 [PLL_OFF_L_VAL] = 0x04,
304 [PLL_OFF_ALPHA_VAL] = 0x08,
305 [PLL_OFF_TEST_CTL] = 0x0c,
306 [PLL_OFF_TEST_CTL_U] = 0x10,
307 [PLL_OFF_USER_CTL] = 0x14,
308 [PLL_OFF_CONFIG_CTL] = 0x18,
309 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
310 [PLL_OFF_STATUS] = 0x20,
311 },
312
313 };
314 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
315
316 /*
317 * Even though 40 bits are present, use only 32 for ease of calculation.
318 */
319 #define ALPHA_REG_BITWIDTH 40
320 #define ALPHA_REG_16BIT_WIDTH 16
321 #define ALPHA_BITWIDTH 32U
322 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
323
324 #define ALPHA_PLL_STATUS_REG_SHIFT 8
325
326 #define PLL_HUAYRA_M_WIDTH 8
327 #define PLL_HUAYRA_M_SHIFT 8
328 #define PLL_HUAYRA_M_MASK 0xff
329 #define PLL_HUAYRA_N_SHIFT 0
330 #define PLL_HUAYRA_N_MASK 0xff
331 #define PLL_HUAYRA_ALPHA_WIDTH 16
332
333 #define PLL_STANDBY 0x0
334 #define PLL_RUN 0x1
335 #define PLL_OUT_MASK 0x7
336 #define PLL_RATE_MARGIN 500
337
338 /* TRION PLL specific settings and offsets */
339 #define TRION_PLL_CAL_VAL 0x44
340 #define TRION_PCAL_DONE BIT(26)
341
342 /* LUCID PLL specific settings and offsets */
343 #define LUCID_PCAL_DONE BIT(27)
344
345 /* LUCID 5LPE PLL specific settings and offsets */
346 #define LUCID_5LPE_PCAL_DONE BIT(11)
347 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
348 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
349 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
350
351 /* LUCID EVO PLL specific settings and offsets */
352 #define LUCID_EVO_PCAL_NOT_DONE BIT(8)
353 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
354 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
355 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
356 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
357
358 /* PONGO ELU PLL specific setting and offsets */
359 #define PONGO_PLL_OUT_MASK GENMASK(1, 0)
360 #define PONGO_PLL_L_VAL_MASK GENMASK(11, 0)
361 #define PONGO_XO_PRESENT BIT(10)
362 #define PONGO_CLOCK_SELECT BIT(12)
363
364 /* ZONDA PLL specific */
365 #define ZONDA_PLL_OUT_MASK 0xf
366 #define ZONDA_STAY_IN_CFA BIT(16)
367 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
368
369 #define pll_alpha_width(p) \
370 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
371 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
372
373 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
374
375 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
376 struct clk_alpha_pll, clkr)
377
378 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
379 struct clk_alpha_pll_postdiv, clkr)
380
wait_for_pll(struct clk_alpha_pll * pll,u32 mask,bool inverse,const char * action)381 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
382 const char *action)
383 {
384 u32 val;
385 int count;
386 int ret;
387 const char *name = clk_hw_get_name(&pll->clkr.hw);
388
389 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
390 if (ret)
391 return ret;
392
393 /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */
394 for (count = 1500; count > 0; count--) {
395 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
396 if (ret)
397 return ret;
398 if (inverse && !(val & mask))
399 return 0;
400 else if ((val & mask) == mask)
401 return 0;
402
403 udelay(1);
404 }
405
406 WARN(1, "%s failed to %s!\n", name, action);
407 return -ETIMEDOUT;
408 }
409
410 #define wait_for_pll_enable_active(pll) \
411 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
412
413 #define wait_for_pll_enable_lock(pll) \
414 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
415
416 #define wait_for_zonda_pll_freq_lock(pll) \
417 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
418
419 #define wait_for_pll_disable(pll) \
420 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
421
422 #define wait_for_pll_offline(pll) \
423 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
424
425 #define wait_for_pll_update(pll) \
426 wait_for_pll(pll, PLL_UPDATE, 1, "update")
427
428 #define wait_for_pll_update_ack_set(pll) \
429 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
430
431 #define wait_for_pll_update_ack_clear(pll) \
432 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
433
clk_alpha_pll_write_config(struct regmap * regmap,unsigned int reg,unsigned int val)434 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
435 unsigned int val)
436 {
437 if (val)
438 regmap_write(regmap, reg, val);
439 }
440
clk_alpha_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)441 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
442 const struct alpha_pll_config *config)
443 {
444 u32 val, mask;
445
446 regmap_write(regmap, PLL_L_VAL(pll), config->l);
447 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
448 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
449
450 if (pll_has_64bit_config(pll))
451 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
452 config->config_ctl_hi_val);
453
454 if (pll_alpha_width(pll) > 32)
455 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
456
457 val = config->main_output_mask;
458 val |= config->aux_output_mask;
459 val |= config->aux2_output_mask;
460 val |= config->early_output_mask;
461 val |= config->pre_div_val;
462 val |= config->post_div_val;
463 val |= config->vco_val;
464 val |= config->alpha_en_mask;
465 val |= config->alpha_mode_mask;
466
467 mask = config->main_output_mask;
468 mask |= config->aux_output_mask;
469 mask |= config->aux2_output_mask;
470 mask |= config->early_output_mask;
471 mask |= config->pre_div_mask;
472 mask |= config->post_div_mask;
473 mask |= config->vco_mask;
474 mask |= config->alpha_en_mask;
475 mask |= config->alpha_mode_mask;
476
477 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
478
479 if (config->test_ctl_mask)
480 regmap_update_bits(regmap, PLL_TEST_CTL(pll),
481 config->test_ctl_mask,
482 config->test_ctl_val);
483 else
484 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
485 config->test_ctl_val);
486
487 if (config->test_ctl_hi_mask)
488 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
489 config->test_ctl_hi_mask,
490 config->test_ctl_hi_val);
491 else
492 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
493 config->test_ctl_hi_val);
494
495 if (pll->flags & SUPPORTS_FSM_MODE)
496 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
497 }
498 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
499
clk_alpha_pll_hwfsm_enable(struct clk_hw * hw)500 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
501 {
502 int ret;
503 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
504 u32 val;
505
506 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
507 if (ret)
508 return ret;
509
510 val |= PLL_FSM_ENA;
511
512 if (pll->flags & SUPPORTS_OFFLINE_REQ)
513 val &= ~PLL_OFFLINE_REQ;
514
515 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
516 if (ret)
517 return ret;
518
519 /* Make sure enable request goes through before waiting for update */
520 mb();
521
522 return wait_for_pll_enable_active(pll);
523 }
524
clk_alpha_pll_hwfsm_disable(struct clk_hw * hw)525 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
526 {
527 int ret;
528 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
529 u32 val;
530
531 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
532 if (ret)
533 return;
534
535 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
536 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
537 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
538 if (ret)
539 return;
540
541 ret = wait_for_pll_offline(pll);
542 if (ret)
543 return;
544 }
545
546 /* Disable hwfsm */
547 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
548 PLL_FSM_ENA, 0);
549 if (ret)
550 return;
551
552 wait_for_pll_disable(pll);
553 }
554
pll_is_enabled(struct clk_hw * hw,u32 mask)555 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
556 {
557 int ret;
558 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
559 u32 val;
560
561 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
562 if (ret)
563 return ret;
564
565 return !!(val & mask);
566 }
567
clk_alpha_pll_hwfsm_is_enabled(struct clk_hw * hw)568 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
569 {
570 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
571 }
572
clk_alpha_pll_is_enabled(struct clk_hw * hw)573 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
574 {
575 return pll_is_enabled(hw, PLL_LOCK_DET);
576 }
577
clk_alpha_pll_enable(struct clk_hw * hw)578 static int clk_alpha_pll_enable(struct clk_hw *hw)
579 {
580 int ret;
581 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
582 u32 val, mask;
583
584 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
585 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
586 if (ret)
587 return ret;
588
589 /* If in FSM mode, just vote for it */
590 if (val & PLL_VOTE_FSM_ENA) {
591 ret = clk_enable_regmap(hw);
592 if (ret)
593 return ret;
594 return wait_for_pll_enable_active(pll);
595 }
596
597 /* Skip if already enabled */
598 if ((val & mask) == mask)
599 return 0;
600
601 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
602 PLL_BYPASSNL, PLL_BYPASSNL);
603 if (ret)
604 return ret;
605
606 /*
607 * H/W requires a 5us delay between disabling the bypass and
608 * de-asserting the reset.
609 */
610 mb();
611 udelay(5);
612
613 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
614 PLL_RESET_N, PLL_RESET_N);
615 if (ret)
616 return ret;
617
618 ret = wait_for_pll_enable_lock(pll);
619 if (ret)
620 return ret;
621
622 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
623 PLL_OUTCTRL, PLL_OUTCTRL);
624
625 /* Ensure that the write above goes through before returning. */
626 mb();
627 return ret;
628 }
629
clk_alpha_pll_disable(struct clk_hw * hw)630 static void clk_alpha_pll_disable(struct clk_hw *hw)
631 {
632 int ret;
633 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
634 u32 val, mask;
635
636 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
637 if (ret)
638 return;
639
640 /* If in FSM mode, just unvote it */
641 if (val & PLL_VOTE_FSM_ENA) {
642 clk_disable_regmap(hw);
643 return;
644 }
645
646 mask = PLL_OUTCTRL;
647 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
648
649 /* Delay of 2 output clock ticks required until output is disabled */
650 mb();
651 udelay(1);
652
653 mask = PLL_RESET_N | PLL_BYPASSNL;
654 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
655 }
656
657 static unsigned long
alpha_pll_calc_rate(u64 prate,u32 l,u32 a,u32 alpha_width)658 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
659 {
660 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
661 }
662
663 static unsigned long
alpha_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u64 * a,u32 alpha_width)664 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
665 u32 alpha_width)
666 {
667 u64 remainder;
668 u64 quotient;
669
670 quotient = rate;
671 remainder = do_div(quotient, prate);
672 *l = quotient;
673
674 if (!remainder) {
675 *a = 0;
676 return rate;
677 }
678
679 /* Upper ALPHA_BITWIDTH bits of Alpha */
680 quotient = remainder << ALPHA_SHIFT(alpha_width);
681
682 remainder = do_div(quotient, prate);
683
684 if (remainder)
685 quotient++;
686
687 *a = quotient;
688 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
689 }
690
691 static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll * pll,unsigned long rate)692 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
693 {
694 const struct pll_vco *v = pll->vco_table;
695 const struct pll_vco *end = v + pll->num_vco;
696
697 for (; v < end; v++)
698 if (rate >= v->min_freq && rate <= v->max_freq)
699 return v;
700
701 return NULL;
702 }
703
704 static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)705 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
706 {
707 u32 l, low, high, ctl;
708 u64 a = 0, prate = parent_rate;
709 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
710 u32 alpha_width = pll_alpha_width(pll);
711
712 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
713 return 0;
714
715 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
716 return 0;
717
718 if (ctl & PLL_ALPHA_EN) {
719 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low))
720 return 0;
721 if (alpha_width > 32) {
722 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
723 &high))
724 return 0;
725 a = (u64)high << 32 | low;
726 } else {
727 a = low & GENMASK(alpha_width - 1, 0);
728 }
729
730 if (alpha_width > ALPHA_BITWIDTH)
731 a >>= alpha_width - ALPHA_BITWIDTH;
732 }
733
734 return alpha_pll_calc_rate(prate, l, a, alpha_width);
735 }
736
737
__clk_alpha_pll_update_latch(struct clk_alpha_pll * pll)738 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
739 {
740 int ret;
741 u32 mode;
742
743 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
744
745 /* Latch the input to the PLL */
746 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
747 PLL_UPDATE);
748
749 /* Wait for 2 reference cycle before checking ACK bit */
750 udelay(1);
751
752 /*
753 * PLL will latch the new L, Alpha and freq control word.
754 * PLL will respond by raising PLL_ACK_LATCH output when new programming
755 * has been latched in and PLL is being updated. When
756 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
757 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
758 */
759 if (mode & PLL_UPDATE_BYPASS) {
760 ret = wait_for_pll_update_ack_set(pll);
761 if (ret)
762 return ret;
763
764 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
765 } else {
766 ret = wait_for_pll_update(pll);
767 if (ret)
768 return ret;
769 }
770
771 ret = wait_for_pll_update_ack_clear(pll);
772 if (ret)
773 return ret;
774
775 /* Wait for PLL output to stabilize */
776 udelay(10);
777
778 return 0;
779 }
780
clk_alpha_pll_update_latch(struct clk_alpha_pll * pll,int (* is_enabled)(struct clk_hw *))781 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
782 int (*is_enabled)(struct clk_hw *))
783 {
784 if (!is_enabled(&pll->clkr.hw) ||
785 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
786 return 0;
787
788 return __clk_alpha_pll_update_latch(pll);
789 }
790
__clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,int (* is_enabled)(struct clk_hw *))791 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
792 unsigned long prate,
793 int (*is_enabled)(struct clk_hw *))
794 {
795 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
796 const struct pll_vco *vco;
797 u32 l, alpha_width = pll_alpha_width(pll);
798 u64 a;
799
800 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
801 vco = alpha_pll_find_vco(pll, rate);
802 if (pll->vco_table && !vco) {
803 pr_err("%s: alpha pll not in a valid vco range\n",
804 clk_hw_get_name(hw));
805 return -EINVAL;
806 }
807
808 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
809
810 if (alpha_width > ALPHA_BITWIDTH)
811 a <<= alpha_width - ALPHA_BITWIDTH;
812
813 if (alpha_width > 32)
814 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
815
816 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
817
818 if (vco) {
819 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
820 PLL_VCO_MASK << PLL_VCO_SHIFT,
821 vco->val << PLL_VCO_SHIFT);
822 }
823
824 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
825 PLL_ALPHA_EN, PLL_ALPHA_EN);
826
827 return clk_alpha_pll_update_latch(pll, is_enabled);
828 }
829
clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)830 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
831 unsigned long prate)
832 {
833 return __clk_alpha_pll_set_rate(hw, rate, prate,
834 clk_alpha_pll_is_enabled);
835 }
836
clk_alpha_pll_hwfsm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)837 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
838 unsigned long prate)
839 {
840 return __clk_alpha_pll_set_rate(hw, rate, prate,
841 clk_alpha_pll_hwfsm_is_enabled);
842 }
843
clk_alpha_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)844 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
845 unsigned long *prate)
846 {
847 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
848 u32 l, alpha_width = pll_alpha_width(pll);
849 u64 a;
850 unsigned long min_freq, max_freq;
851
852 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
853 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
854 return rate;
855
856 min_freq = pll->vco_table[0].min_freq;
857 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
858
859 return clamp(rate, min_freq, max_freq);
860 }
861
clk_huayra_2290_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)862 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
863 const struct alpha_pll_config *config)
864 {
865 u32 val;
866
867 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
868 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
869 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
870 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
871 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
872 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
873 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
874 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
875 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
876
877 /* Set PLL_BYPASSNL */
878 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
879 regmap_read(regmap, PLL_MODE(pll), &val);
880
881 /* Wait 5 us between setting BYPASS and deasserting reset */
882 udelay(5);
883
884 /* Take PLL out from reset state */
885 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
886 regmap_read(regmap, PLL_MODE(pll), &val);
887
888 /* Wait 50us for PLL_LOCK_DET bit to go high */
889 usleep_range(50, 55);
890
891 /* Enable PLL output */
892 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
893 }
894 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure);
895
896 static unsigned long
alpha_huayra_pll_calc_rate(u64 prate,u32 l,u32 a)897 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
898 {
899 /*
900 * a contains 16 bit alpha_val in two’s complement number in the range
901 * of [-0.5, 0.5).
902 */
903 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
904 l -= 1;
905
906 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
907 }
908
909 static unsigned long
alpha_huayra_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u32 * a)910 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
911 u32 *l, u32 *a)
912 {
913 u64 remainder;
914 u64 quotient;
915
916 quotient = rate;
917 remainder = do_div(quotient, prate);
918 *l = quotient;
919
920 if (!remainder) {
921 *a = 0;
922 return rate;
923 }
924
925 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
926 remainder = do_div(quotient, prate);
927
928 if (remainder)
929 quotient++;
930
931 /*
932 * alpha_val should be in two’s complement number in the range
933 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
934 * since alpha value will be subtracted in this case.
935 */
936 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
937 *l += 1;
938
939 *a = quotient;
940 return alpha_huayra_pll_calc_rate(prate, *l, *a);
941 }
942
943 static unsigned long
alpha_pll_huayra_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)944 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
945 {
946 u64 rate = parent_rate, tmp;
947 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
948 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
949
950 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
951 return 0;
952
953 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
954 return 0;
955
956 if (ctl & PLL_ALPHA_EN) {
957 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
958 /*
959 * Depending upon alpha_mode, it can be treated as M/N value or
960 * as a two’s complement number. When alpha_mode=1,
961 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
962 *
963 * Fout=FIN*(L+(M/N))
964 *
965 * M is a signed number (-128 to 127) and N is unsigned
966 * (0 to 255). M/N has to be within +/-0.5.
967 *
968 * When alpha_mode=0, it is a two’s complement number in the
969 * range [-0.5, 0.5).
970 *
971 * Fout=FIN*(L+(alpha_val)/2^16)
972 *
973 * where alpha_val is two’s complement number.
974 */
975 if (!(ctl & PLL_ALPHA_MODE))
976 return alpha_huayra_pll_calc_rate(rate, l, alpha);
977
978 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
979 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
980
981 rate *= l;
982 tmp = parent_rate;
983 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
984 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
985 tmp *= alpha_m;
986 do_div(tmp, alpha_n);
987 rate -= tmp;
988 } else {
989 tmp *= alpha_m;
990 do_div(tmp, alpha_n);
991 rate += tmp;
992 }
993
994 return rate;
995 }
996
997 return alpha_huayra_pll_calc_rate(rate, l, alpha);
998 }
999
alpha_pll_huayra_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1000 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
1001 unsigned long prate)
1002 {
1003 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1004 u32 l, a, ctl, cur_alpha = 0;
1005
1006 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
1007
1008 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1009
1010 if (ctl & PLL_ALPHA_EN)
1011 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
1012
1013 /*
1014 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
1015 * without having to go through the power on sequence.
1016 */
1017 if (clk_alpha_pll_is_enabled(hw)) {
1018 if (cur_alpha != a) {
1019 pr_err("%s: clock needs to be gated\n",
1020 clk_hw_get_name(hw));
1021 return -EBUSY;
1022 }
1023
1024 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1025 /* Ensure that the write above goes to detect L val change. */
1026 mb();
1027 return wait_for_pll_enable_lock(pll);
1028 }
1029
1030 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1031 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1032
1033 if (a == 0)
1034 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1035 PLL_ALPHA_EN, 0x0);
1036 else
1037 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1038 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
1039
1040 return 0;
1041 }
1042
alpha_pll_huayra_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1043 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
1044 unsigned long *prate)
1045 {
1046 u32 l, a;
1047
1048 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
1049 }
1050
trion_pll_is_enabled(struct clk_alpha_pll * pll,struct regmap * regmap)1051 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
1052 struct regmap *regmap)
1053 {
1054 u32 mode_val, opmode_val;
1055 int ret;
1056
1057 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
1058 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1059 if (ret)
1060 return 0;
1061
1062 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
1063 }
1064
clk_trion_pll_is_enabled(struct clk_hw * hw)1065 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
1066 {
1067 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1068
1069 return trion_pll_is_enabled(pll, pll->clkr.regmap);
1070 }
1071
clk_trion_pll_enable(struct clk_hw * hw)1072 static int clk_trion_pll_enable(struct clk_hw *hw)
1073 {
1074 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1075 struct regmap *regmap = pll->clkr.regmap;
1076 u32 val;
1077 int ret;
1078
1079 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1080 if (ret)
1081 return ret;
1082
1083 /* If in FSM mode, just vote for it */
1084 if (val & PLL_VOTE_FSM_ENA) {
1085 ret = clk_enable_regmap(hw);
1086 if (ret)
1087 return ret;
1088 return wait_for_pll_enable_active(pll);
1089 }
1090
1091 /* Set operation mode to RUN */
1092 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1093
1094 ret = wait_for_pll_enable_lock(pll);
1095 if (ret)
1096 return ret;
1097
1098 /* Enable the PLL outputs */
1099 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1100 PLL_OUT_MASK, PLL_OUT_MASK);
1101 if (ret)
1102 return ret;
1103
1104 /* Enable the global PLL outputs */
1105 return regmap_update_bits(regmap, PLL_MODE(pll),
1106 PLL_OUTCTRL, PLL_OUTCTRL);
1107 }
1108
clk_trion_pll_disable(struct clk_hw * hw)1109 static void clk_trion_pll_disable(struct clk_hw *hw)
1110 {
1111 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1112 struct regmap *regmap = pll->clkr.regmap;
1113 u32 val;
1114 int ret;
1115
1116 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1117 if (ret)
1118 return;
1119
1120 /* If in FSM mode, just unvote it */
1121 if (val & PLL_VOTE_FSM_ENA) {
1122 clk_disable_regmap(hw);
1123 return;
1124 }
1125
1126 /* Disable the global PLL output */
1127 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1128 if (ret)
1129 return;
1130
1131 /* Disable the PLL outputs */
1132 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1133 PLL_OUT_MASK, 0);
1134 if (ret)
1135 return;
1136
1137 /* Place the PLL mode in STANDBY */
1138 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1139 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1140 }
1141
1142 static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1143 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1144 {
1145 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1146 u32 l, frac, alpha_width = pll_alpha_width(pll);
1147
1148 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
1149 return 0;
1150
1151 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac))
1152 return 0;
1153
1154 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1155 }
1156
1157 const struct clk_ops clk_alpha_pll_fixed_ops = {
1158 .enable = clk_alpha_pll_enable,
1159 .disable = clk_alpha_pll_disable,
1160 .is_enabled = clk_alpha_pll_is_enabled,
1161 .recalc_rate = clk_alpha_pll_recalc_rate,
1162 };
1163 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1164
1165 const struct clk_ops clk_alpha_pll_ops = {
1166 .enable = clk_alpha_pll_enable,
1167 .disable = clk_alpha_pll_disable,
1168 .is_enabled = clk_alpha_pll_is_enabled,
1169 .recalc_rate = clk_alpha_pll_recalc_rate,
1170 .round_rate = clk_alpha_pll_round_rate,
1171 .set_rate = clk_alpha_pll_set_rate,
1172 };
1173 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1174
1175 const struct clk_ops clk_alpha_pll_huayra_ops = {
1176 .enable = clk_alpha_pll_enable,
1177 .disable = clk_alpha_pll_disable,
1178 .is_enabled = clk_alpha_pll_is_enabled,
1179 .recalc_rate = alpha_pll_huayra_recalc_rate,
1180 .round_rate = alpha_pll_huayra_round_rate,
1181 .set_rate = alpha_pll_huayra_set_rate,
1182 };
1183 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1184
1185 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1186 .enable = clk_alpha_pll_hwfsm_enable,
1187 .disable = clk_alpha_pll_hwfsm_disable,
1188 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1189 .recalc_rate = clk_alpha_pll_recalc_rate,
1190 .round_rate = clk_alpha_pll_round_rate,
1191 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1192 };
1193 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1194
1195 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1196 .enable = clk_trion_pll_enable,
1197 .disable = clk_trion_pll_disable,
1198 .is_enabled = clk_trion_pll_is_enabled,
1199 .recalc_rate = clk_trion_pll_recalc_rate,
1200 .round_rate = clk_alpha_pll_round_rate,
1201 };
1202 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1203
1204 static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1205 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1206 {
1207 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1208 u32 ctl;
1209
1210 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
1211 return 0;
1212
1213 ctl >>= PLL_POST_DIV_SHIFT;
1214 ctl &= PLL_POST_DIV_MASK(pll);
1215
1216 return parent_rate >> fls(ctl);
1217 }
1218
1219 static const struct clk_div_table clk_alpha_div_table[] = {
1220 { 0x0, 1 },
1221 { 0x1, 2 },
1222 { 0x3, 4 },
1223 { 0x7, 8 },
1224 { 0xf, 16 },
1225 { }
1226 };
1227
1228 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1229 { 0x0, 1 },
1230 { 0x1, 2 },
1231 { 0x3, 4 },
1232 { }
1233 };
1234
1235 static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1236 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1237 unsigned long *prate)
1238 {
1239 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1240 const struct clk_div_table *table;
1241
1242 if (pll->width == 2)
1243 table = clk_alpha_2bit_div_table;
1244 else
1245 table = clk_alpha_div_table;
1246
1247 return divider_round_rate(hw, rate, prate, table,
1248 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1249 }
1250
1251 static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1252 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1253 unsigned long *prate)
1254 {
1255 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1256 u32 ctl, div;
1257
1258 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1259
1260 ctl >>= PLL_POST_DIV_SHIFT;
1261 ctl &= BIT(pll->width) - 1;
1262 div = 1 << fls(ctl);
1263
1264 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1265 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1266
1267 return DIV_ROUND_UP_ULL((u64)*prate, div);
1268 }
1269
clk_alpha_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1270 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1271 unsigned long parent_rate)
1272 {
1273 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1274 int div;
1275
1276 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1277 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1278
1279 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1280 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1281 div << PLL_POST_DIV_SHIFT);
1282 }
1283
1284 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1285 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1286 .round_rate = clk_alpha_pll_postdiv_round_rate,
1287 .set_rate = clk_alpha_pll_postdiv_set_rate,
1288 };
1289 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1290
1291 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1292 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1293 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1294 };
1295 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1296
clk_fabia_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1297 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1298 const struct alpha_pll_config *config)
1299 {
1300 u32 val, mask;
1301
1302 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1303 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1304 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1305 config->config_ctl_val);
1306 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1307 config->config_ctl_hi_val);
1308 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1309 config->user_ctl_val);
1310 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1311 config->user_ctl_hi_val);
1312 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1313 config->test_ctl_val);
1314 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1315 config->test_ctl_hi_val);
1316
1317 if (config->post_div_mask) {
1318 mask = config->post_div_mask;
1319 val = config->post_div_val;
1320 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1321 }
1322
1323 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1324 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1325 PLL_FSM_LEGACY_MODE);
1326
1327 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1328 PLL_UPDATE_BYPASS);
1329
1330 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1331 }
1332 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1333
alpha_pll_fabia_enable(struct clk_hw * hw)1334 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1335 {
1336 int ret;
1337 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1338 u32 val, opmode_val;
1339 struct regmap *regmap = pll->clkr.regmap;
1340
1341 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1342 if (ret)
1343 return ret;
1344
1345 /* If in FSM mode, just vote for it */
1346 if (val & PLL_VOTE_FSM_ENA) {
1347 ret = clk_enable_regmap(hw);
1348 if (ret)
1349 return ret;
1350 return wait_for_pll_enable_active(pll);
1351 }
1352
1353 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1354 if (ret)
1355 return ret;
1356
1357 /* Skip If PLL is already running */
1358 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1359 return 0;
1360
1361 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1362 if (ret)
1363 return ret;
1364
1365 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1366 if (ret)
1367 return ret;
1368
1369 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1370 PLL_RESET_N);
1371 if (ret)
1372 return ret;
1373
1374 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1375 if (ret)
1376 return ret;
1377
1378 ret = wait_for_pll_enable_lock(pll);
1379 if (ret)
1380 return ret;
1381
1382 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1383 PLL_OUT_MASK, PLL_OUT_MASK);
1384 if (ret)
1385 return ret;
1386
1387 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1388 PLL_OUTCTRL);
1389 }
1390
alpha_pll_fabia_disable(struct clk_hw * hw)1391 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1392 {
1393 int ret;
1394 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1395 u32 val;
1396 struct regmap *regmap = pll->clkr.regmap;
1397
1398 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1399 if (ret)
1400 return;
1401
1402 /* If in FSM mode, just unvote it */
1403 if (val & PLL_FSM_ENA) {
1404 clk_disable_regmap(hw);
1405 return;
1406 }
1407
1408 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1409 if (ret)
1410 return;
1411
1412 /* Disable main outputs */
1413 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1414 if (ret)
1415 return;
1416
1417 /* Place the PLL in STANDBY */
1418 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1419 }
1420
alpha_pll_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1421 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1422 unsigned long parent_rate)
1423 {
1424 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1425 u32 l, frac, alpha_width = pll_alpha_width(pll);
1426
1427 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
1428 return 0;
1429
1430 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac))
1431 return 0;
1432
1433 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1434 }
1435
1436 /*
1437 * Due to limited number of bits for fractional rate programming, the
1438 * rounded up rate could be marginally higher than the requested rate.
1439 */
alpha_pll_check_rate_margin(struct clk_hw * hw,unsigned long rrate,unsigned long rate)1440 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1441 unsigned long rrate, unsigned long rate)
1442 {
1443 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1444
1445 if (rrate > rate_margin || rrate < rate) {
1446 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1447 clk_hw_get_name(hw), rrate, rate, rate_margin);
1448 return -EINVAL;
1449 }
1450
1451 return 0;
1452 }
1453
alpha_pll_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1454 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1455 unsigned long prate)
1456 {
1457 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1458 u32 l, alpha_width = pll_alpha_width(pll);
1459 unsigned long rrate;
1460 int ret;
1461 u64 a;
1462
1463 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1464
1465 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1466 if (ret < 0)
1467 return ret;
1468
1469 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1470 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1471
1472 return __clk_alpha_pll_update_latch(pll);
1473 }
1474
alpha_pll_fabia_prepare(struct clk_hw * hw)1475 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1476 {
1477 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1478 const struct pll_vco *vco;
1479 struct clk_hw *parent_hw;
1480 unsigned long cal_freq, rrate;
1481 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1482 const char *name = clk_hw_get_name(hw);
1483 u64 a;
1484 int ret;
1485
1486 /* Check if calibration needs to be done i.e. PLL is in reset */
1487 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1488 if (ret)
1489 return ret;
1490
1491 /* Return early if calibration is not needed. */
1492 if (val & PLL_RESET_N)
1493 return 0;
1494
1495 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1496 if (!vco) {
1497 pr_err("%s: alpha pll not in a valid vco range\n", name);
1498 return -EINVAL;
1499 }
1500
1501 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1502 pll->vco_table[0].max_freq) * 54, 100);
1503
1504 parent_hw = clk_hw_get_parent(hw);
1505 if (!parent_hw)
1506 return -EINVAL;
1507
1508 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1509 &cal_l, &a, alpha_width);
1510
1511 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1512 if (ret < 0)
1513 return ret;
1514
1515 /* Setup PLL for calibration frequency */
1516 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1517
1518 /* Bringup the PLL at calibration frequency */
1519 ret = clk_alpha_pll_enable(hw);
1520 if (ret) {
1521 pr_err("%s: alpha pll calibration failed\n", name);
1522 return ret;
1523 }
1524
1525 clk_alpha_pll_disable(hw);
1526
1527 return 0;
1528 }
1529
1530 const struct clk_ops clk_alpha_pll_fabia_ops = {
1531 .prepare = alpha_pll_fabia_prepare,
1532 .enable = alpha_pll_fabia_enable,
1533 .disable = alpha_pll_fabia_disable,
1534 .is_enabled = clk_alpha_pll_is_enabled,
1535 .set_rate = alpha_pll_fabia_set_rate,
1536 .recalc_rate = alpha_pll_fabia_recalc_rate,
1537 .round_rate = clk_alpha_pll_round_rate,
1538 };
1539 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1540
1541 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1542 .enable = alpha_pll_fabia_enable,
1543 .disable = alpha_pll_fabia_disable,
1544 .is_enabled = clk_alpha_pll_is_enabled,
1545 .recalc_rate = alpha_pll_fabia_recalc_rate,
1546 .round_rate = clk_alpha_pll_round_rate,
1547 };
1548 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1549
clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1550 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1551 unsigned long parent_rate)
1552 {
1553 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1554 u32 i, div = 1, val;
1555 int ret;
1556
1557 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1558 if (ret)
1559 return ret;
1560
1561 val >>= pll->post_div_shift;
1562 val &= BIT(pll->width) - 1;
1563
1564 for (i = 0; i < pll->num_post_div; i++) {
1565 if (pll->post_div_table[i].val == val) {
1566 div = pll->post_div_table[i].div;
1567 break;
1568 }
1569 }
1570
1571 return (parent_rate / div);
1572 }
1573
1574 static unsigned long
clk_trion_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1575 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1576 {
1577 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1578 struct regmap *regmap = pll->clkr.regmap;
1579 u32 i, div = 1, val;
1580
1581 if (regmap_read(regmap, PLL_USER_CTL(pll), &val))
1582 return 0;
1583
1584 val >>= pll->post_div_shift;
1585 val &= PLL_POST_DIV_MASK(pll);
1586
1587 for (i = 0; i < pll->num_post_div; i++) {
1588 if (pll->post_div_table[i].val == val) {
1589 div = pll->post_div_table[i].div;
1590 break;
1591 }
1592 }
1593
1594 return (parent_rate / div);
1595 }
1596
1597 static long
clk_trion_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1598 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1599 unsigned long *prate)
1600 {
1601 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1602
1603 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1604 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1605 };
1606
1607 static int
clk_trion_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1608 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1609 unsigned long parent_rate)
1610 {
1611 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1612 struct regmap *regmap = pll->clkr.regmap;
1613 int i, val = 0, div;
1614
1615 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1616 for (i = 0; i < pll->num_post_div; i++) {
1617 if (pll->post_div_table[i].div == div) {
1618 val = pll->post_div_table[i].val;
1619 break;
1620 }
1621 }
1622
1623 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1624 PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
1625 val << pll->post_div_shift);
1626 }
1627
1628 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1629 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1630 .round_rate = clk_trion_pll_postdiv_round_rate,
1631 .set_rate = clk_trion_pll_postdiv_set_rate,
1632 };
1633 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1634
clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1635 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1636 unsigned long rate, unsigned long *prate)
1637 {
1638 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1639
1640 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1641 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1642 }
1643
clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1644 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1645 unsigned long rate, unsigned long parent_rate)
1646 {
1647 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1648 int i, val = 0, div, ret;
1649
1650 /*
1651 * If the PLL is in FSM mode, then treat set_rate callback as a
1652 * no-operation.
1653 */
1654 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1655 if (ret)
1656 return ret;
1657
1658 if (val & PLL_VOTE_FSM_ENA)
1659 return 0;
1660
1661 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1662 for (i = 0; i < pll->num_post_div; i++) {
1663 if (pll->post_div_table[i].div == div) {
1664 val = pll->post_div_table[i].val;
1665 break;
1666 }
1667 }
1668
1669 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1670 (BIT(pll->width) - 1) << pll->post_div_shift,
1671 val << pll->post_div_shift);
1672 }
1673
1674 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1675 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1676 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1677 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1678 };
1679 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1680
1681 /**
1682 * clk_trion_pll_configure - configure the trion pll
1683 *
1684 * @pll: clk alpha pll
1685 * @regmap: register map
1686 * @config: configuration to apply for pll
1687 */
clk_trion_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1688 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1689 const struct alpha_pll_config *config)
1690 {
1691 /*
1692 * If the bootloader left the PLL enabled it's likely that there are
1693 * RCGs that will lock up if we disable the PLL below.
1694 */
1695 if (trion_pll_is_enabled(pll, regmap)) {
1696 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1697 return;
1698 }
1699
1700 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1701 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1702 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1703 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1704 config->config_ctl_val);
1705 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1706 config->config_ctl_hi_val);
1707 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1708 config->config_ctl_hi1_val);
1709 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1710 config->user_ctl_val);
1711 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1712 config->user_ctl_hi_val);
1713 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1714 config->user_ctl_hi1_val);
1715 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1716 config->test_ctl_val);
1717 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1718 config->test_ctl_hi_val);
1719 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1720 config->test_ctl_hi1_val);
1721
1722 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1723 PLL_UPDATE_BYPASS);
1724
1725 /* Disable PLL output */
1726 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1727
1728 /* Set operation mode to OFF */
1729 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1730
1731 /* Place the PLL in STANDBY mode */
1732 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1733 }
1734 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1735
1736 /*
1737 * The TRION PLL requires a power-on self-calibration which happens when the
1738 * PLL comes out of reset. Calibrate in case it is not completed.
1739 */
__alpha_pll_trion_prepare(struct clk_hw * hw,u32 pcal_done)1740 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1741 {
1742 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1743 u32 val;
1744 int ret;
1745
1746 /* Return early if calibration is not needed. */
1747 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1748 if (val & pcal_done)
1749 return 0;
1750
1751 /* On/off to calibrate */
1752 ret = clk_trion_pll_enable(hw);
1753 if (!ret)
1754 clk_trion_pll_disable(hw);
1755
1756 return ret;
1757 }
1758
alpha_pll_trion_prepare(struct clk_hw * hw)1759 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1760 {
1761 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1762 }
1763
alpha_pll_lucid_prepare(struct clk_hw * hw)1764 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1765 {
1766 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1767 }
1768
__alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,u32 latch_bit,u32 latch_ack)1769 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1770 unsigned long prate, u32 latch_bit, u32 latch_ack)
1771 {
1772 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1773 unsigned long rrate;
1774 u32 val, l, alpha_width = pll_alpha_width(pll);
1775 u64 a;
1776 int ret;
1777
1778 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1779
1780 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1781 if (ret < 0)
1782 return ret;
1783
1784 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l);
1785 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1786
1787 /* Latch the PLL input */
1788 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1789 if (ret)
1790 return ret;
1791
1792 /* Wait for 2 reference cycles before checking the ACK bit. */
1793 udelay(1);
1794 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1795 if (!(val & latch_ack)) {
1796 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1797 return -EINVAL;
1798 }
1799
1800 /* Return the latch input to 0 */
1801 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1802 if (ret)
1803 return ret;
1804
1805 if (clk_hw_is_enabled(hw)) {
1806 ret = wait_for_pll_enable_lock(pll);
1807 if (ret)
1808 return ret;
1809 }
1810
1811 /* Wait for PLL output to stabilize */
1812 udelay(100);
1813 return 0;
1814 }
1815
alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1816 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1817 unsigned long prate)
1818 {
1819 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1820 }
1821
1822 const struct clk_ops clk_alpha_pll_trion_ops = {
1823 .prepare = alpha_pll_trion_prepare,
1824 .enable = clk_trion_pll_enable,
1825 .disable = clk_trion_pll_disable,
1826 .is_enabled = clk_trion_pll_is_enabled,
1827 .recalc_rate = clk_trion_pll_recalc_rate,
1828 .round_rate = clk_alpha_pll_round_rate,
1829 .set_rate = alpha_pll_trion_set_rate,
1830 };
1831 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1832
1833 const struct clk_ops clk_alpha_pll_lucid_ops = {
1834 .prepare = alpha_pll_lucid_prepare,
1835 .enable = clk_trion_pll_enable,
1836 .disable = clk_trion_pll_disable,
1837 .is_enabled = clk_trion_pll_is_enabled,
1838 .recalc_rate = clk_trion_pll_recalc_rate,
1839 .round_rate = clk_alpha_pll_round_rate,
1840 .set_rate = alpha_pll_trion_set_rate,
1841 };
1842 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1843
1844 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1845 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1846 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1847 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1848 };
1849 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1850
clk_agera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1851 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1852 const struct alpha_pll_config *config)
1853 {
1854 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1855 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1856 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1857 config->user_ctl_val);
1858 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1859 config->config_ctl_val);
1860 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1861 config->config_ctl_hi_val);
1862 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1863 config->test_ctl_val);
1864 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1865 config->test_ctl_hi_val);
1866 }
1867 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1868
clk_alpha_pll_agera_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1869 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1870 unsigned long prate)
1871 {
1872 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1873 u32 l, alpha_width = pll_alpha_width(pll);
1874 int ret;
1875 unsigned long rrate;
1876 u64 a;
1877
1878 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1879 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1880 if (ret < 0)
1881 return ret;
1882
1883 /* change L_VAL without having to go through the power on sequence */
1884 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1885 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1886
1887 if (clk_hw_is_enabled(hw))
1888 return wait_for_pll_enable_lock(pll);
1889
1890 return 0;
1891 }
1892
1893 const struct clk_ops clk_alpha_pll_agera_ops = {
1894 .enable = clk_alpha_pll_enable,
1895 .disable = clk_alpha_pll_disable,
1896 .is_enabled = clk_alpha_pll_is_enabled,
1897 .recalc_rate = alpha_pll_fabia_recalc_rate,
1898 .round_rate = clk_alpha_pll_round_rate,
1899 .set_rate = clk_alpha_pll_agera_set_rate,
1900 };
1901 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1902
1903 /**
1904 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1905 *
1906 * @pll: clk alpha pll
1907 * @regmap: register map
1908 * @config: configuration to apply for pll
1909 */
clk_lucid_5lpe_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1910 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1911 const struct alpha_pll_config *config)
1912 {
1913 /*
1914 * If the bootloader left the PLL enabled it's likely that there are
1915 * RCGs that will lock up if we disable the PLL below.
1916 */
1917 if (trion_pll_is_enabled(pll, regmap)) {
1918 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
1919 return;
1920 }
1921
1922 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1923 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1924 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1925 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1926 config->config_ctl_val);
1927 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1928 config->config_ctl_hi_val);
1929 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1930 config->config_ctl_hi1_val);
1931 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1932 config->user_ctl_val);
1933 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1934 config->user_ctl_hi_val);
1935 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1936 config->user_ctl_hi1_val);
1937 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1938 config->test_ctl_val);
1939 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1940 config->test_ctl_hi_val);
1941 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1942 config->test_ctl_hi1_val);
1943
1944 /* Disable PLL output */
1945 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1946
1947 /* Set operation mode to OFF */
1948 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1949
1950 /* Place the PLL in STANDBY mode */
1951 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1952 }
1953 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
1954
alpha_pll_lucid_5lpe_enable(struct clk_hw * hw)1955 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1956 {
1957 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1958 u32 val;
1959 int ret;
1960
1961 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1962 if (ret)
1963 return ret;
1964
1965 /* If in FSM mode, just vote for it */
1966 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1967 ret = clk_enable_regmap(hw);
1968 if (ret)
1969 return ret;
1970 return wait_for_pll_enable_lock(pll);
1971 }
1972
1973 /* Check if PLL is already enabled, return if enabled */
1974 if (trion_pll_is_enabled(pll, pll->clkr.regmap))
1975 return 0;
1976
1977 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1978 if (ret)
1979 return ret;
1980
1981 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1982
1983 ret = wait_for_pll_enable_lock(pll);
1984 if (ret)
1985 return ret;
1986
1987 /* Enable the PLL outputs */
1988 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1989 if (ret)
1990 return ret;
1991
1992 /* Enable the global PLL outputs */
1993 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1994 }
1995
alpha_pll_lucid_5lpe_disable(struct clk_hw * hw)1996 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1997 {
1998 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1999 u32 val;
2000 int ret;
2001
2002 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
2003 if (ret)
2004 return;
2005
2006 /* If in FSM mode, just unvote it */
2007 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
2008 clk_disable_regmap(hw);
2009 return;
2010 }
2011
2012 /* Disable the global PLL output */
2013 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2014 if (ret)
2015 return;
2016
2017 /* Disable the PLL outputs */
2018 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2019 if (ret)
2020 return;
2021
2022 /* Place the PLL mode in STANDBY */
2023 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
2024 }
2025
2026 /*
2027 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
2028 * when the PLL comes out of reset. Calibrate in case it is not completed.
2029 */
alpha_pll_lucid_5lpe_prepare(struct clk_hw * hw)2030 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
2031 {
2032 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2033 struct clk_hw *p;
2034 u32 val = 0;
2035 int ret;
2036
2037 /* Return early if calibration is not needed. */
2038 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2039 if (val & LUCID_5LPE_PCAL_DONE)
2040 return 0;
2041
2042 p = clk_hw_get_parent(hw);
2043 if (!p)
2044 return -EINVAL;
2045
2046 ret = alpha_pll_lucid_5lpe_enable(hw);
2047 if (ret)
2048 return ret;
2049
2050 alpha_pll_lucid_5lpe_disable(hw);
2051
2052 return 0;
2053 }
2054
alpha_pll_lucid_5lpe_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2055 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
2056 unsigned long prate)
2057 {
2058 return __alpha_pll_trion_set_rate(hw, rate, prate,
2059 LUCID_5LPE_PLL_LATCH_INPUT,
2060 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
2061 }
2062
__clk_lucid_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,unsigned long enable_vote_run)2063 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2064 unsigned long parent_rate,
2065 unsigned long enable_vote_run)
2066 {
2067 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
2068 struct regmap *regmap = pll->clkr.regmap;
2069 int i, val, div, ret;
2070 u32 mask;
2071
2072 /*
2073 * If the PLL is in FSM mode, then treat set_rate callback as a
2074 * no-operation.
2075 */
2076 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2077 if (ret)
2078 return ret;
2079
2080 if (val & enable_vote_run)
2081 return 0;
2082
2083 if (!pll->post_div_table) {
2084 pr_err("Missing the post_div_table for the %s PLL\n",
2085 clk_hw_get_name(&pll->clkr.hw));
2086 return -EINVAL;
2087 }
2088
2089 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
2090 for (i = 0; i < pll->num_post_div; i++) {
2091 if (pll->post_div_table[i].div == div) {
2092 val = pll->post_div_table[i].val;
2093 break;
2094 }
2095 }
2096
2097 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
2098 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2099 mask, val << pll->post_div_shift);
2100 }
2101
clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2102 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2103 unsigned long parent_rate)
2104 {
2105 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
2106 }
2107
2108 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
2109 .prepare = alpha_pll_lucid_5lpe_prepare,
2110 .enable = alpha_pll_lucid_5lpe_enable,
2111 .disable = alpha_pll_lucid_5lpe_disable,
2112 .is_enabled = clk_trion_pll_is_enabled,
2113 .recalc_rate = clk_trion_pll_recalc_rate,
2114 .round_rate = clk_alpha_pll_round_rate,
2115 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2116 };
2117 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
2118
2119 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
2120 .enable = alpha_pll_lucid_5lpe_enable,
2121 .disable = alpha_pll_lucid_5lpe_disable,
2122 .is_enabled = clk_trion_pll_is_enabled,
2123 .recalc_rate = clk_trion_pll_recalc_rate,
2124 .round_rate = clk_alpha_pll_round_rate,
2125 };
2126 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
2127
2128 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
2129 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2130 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2131 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
2132 };
2133 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
2134
clk_zonda_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2135 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2136 const struct alpha_pll_config *config)
2137 {
2138 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2139 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2140 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2141 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2142 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2143 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2144 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2145 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2146 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2147 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2148 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2149
2150 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
2151
2152 /* Disable PLL output */
2153 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2154
2155 /* Set operation mode to OFF */
2156 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2157
2158 /* Place the PLL in STANDBY mode */
2159 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2160 }
2161 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
2162
clk_zonda_pll_enable(struct clk_hw * hw)2163 static int clk_zonda_pll_enable(struct clk_hw *hw)
2164 {
2165 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2166 struct regmap *regmap = pll->clkr.regmap;
2167 u32 val;
2168 int ret;
2169
2170 regmap_read(regmap, PLL_MODE(pll), &val);
2171
2172 /* If in FSM mode, just vote for it */
2173 if (val & PLL_VOTE_FSM_ENA) {
2174 ret = clk_enable_regmap(hw);
2175 if (ret)
2176 return ret;
2177 return wait_for_pll_enable_active(pll);
2178 }
2179
2180 /* Get the PLL out of bypass mode */
2181 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
2182
2183 /*
2184 * H/W requires a 1us delay between disabling the bypass and
2185 * de-asserting the reset.
2186 */
2187 udelay(1);
2188
2189 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2190
2191 /* Set operation mode to RUN */
2192 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2193
2194 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
2195
2196 /* If cfa mode then poll for freq lock */
2197 if (val & ZONDA_STAY_IN_CFA)
2198 ret = wait_for_zonda_pll_freq_lock(pll);
2199 else
2200 ret = wait_for_pll_enable_lock(pll);
2201 if (ret)
2202 return ret;
2203
2204 /* Enable the PLL outputs */
2205 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2206
2207 /* Enable the global PLL outputs */
2208 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2209
2210 return 0;
2211 }
2212
clk_zonda_pll_disable(struct clk_hw * hw)2213 static void clk_zonda_pll_disable(struct clk_hw *hw)
2214 {
2215 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2216 struct regmap *regmap = pll->clkr.regmap;
2217 u32 val;
2218
2219 regmap_read(regmap, PLL_MODE(pll), &val);
2220
2221 /* If in FSM mode, just unvote it */
2222 if (val & PLL_VOTE_FSM_ENA) {
2223 clk_disable_regmap(hw);
2224 return;
2225 }
2226
2227 /* Disable the global PLL output */
2228 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2229
2230 /* Disable the PLL outputs */
2231 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2232
2233 /* Put the PLL in bypass and reset */
2234 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2235
2236 /* Place the PLL mode in OFF state */
2237 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2238 }
2239
zonda_pll_adjust_l_val(unsigned long rate,unsigned long prate,u32 * l)2240 static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
2241 {
2242 u64 remainder, quotient;
2243
2244 quotient = rate;
2245 remainder = do_div(quotient, prate);
2246
2247 *l = rate + (u32)(remainder * 2 >= prate);
2248 }
2249
clk_zonda_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2250 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2251 unsigned long prate)
2252 {
2253 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2254 unsigned long rrate;
2255 u32 test_ctl_val;
2256 u32 l, alpha_width = pll_alpha_width(pll);
2257 u64 a;
2258 int ret;
2259
2260 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2261
2262 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2263 if (ret < 0)
2264 return ret;
2265
2266 if (a & PLL_ALPHA_MSB)
2267 zonda_pll_adjust_l_val(rate, prate, &l);
2268
2269 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2270 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2271
2272 if (!clk_hw_is_enabled(hw))
2273 return 0;
2274
2275 /* Wait before polling for the frequency latch */
2276 udelay(5);
2277
2278 /* Read stay in cfa mode */
2279 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2280
2281 /* If cfa mode then poll for freq lock */
2282 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2283 ret = wait_for_zonda_pll_freq_lock(pll);
2284 else
2285 ret = wait_for_pll_enable_lock(pll);
2286 if (ret)
2287 return ret;
2288
2289 /* Wait for PLL output to stabilize */
2290 udelay(100);
2291 return 0;
2292 }
2293
2294 const struct clk_ops clk_alpha_pll_zonda_ops = {
2295 .enable = clk_zonda_pll_enable,
2296 .disable = clk_zonda_pll_disable,
2297 .is_enabled = clk_trion_pll_is_enabled,
2298 .recalc_rate = clk_trion_pll_recalc_rate,
2299 .round_rate = clk_alpha_pll_round_rate,
2300 .set_rate = clk_zonda_pll_set_rate,
2301 };
2302 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2303
clk_lucid_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2304 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2305 const struct alpha_pll_config *config)
2306 {
2307 u32 lval = config->l;
2308
2309 /*
2310 * If the bootloader left the PLL enabled it's likely that there are
2311 * RCGs that will lock up if we disable the PLL below.
2312 */
2313 if (trion_pll_is_enabled(pll, regmap)) {
2314 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
2315 return;
2316 }
2317
2318 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2319 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2320 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2321 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2322 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2323 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2324 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2325 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2326 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2327 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2328 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2329 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2330
2331 /* Disable PLL output */
2332 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2333
2334 /* Set operation mode to STANDBY and de-assert the reset */
2335 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2336 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2337 }
2338 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2339
clk_lucid_ole_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2340 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2341 const struct alpha_pll_config *config)
2342 {
2343 u32 lval = config->l;
2344
2345 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2346 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
2347 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2348 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2349 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2350 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2351 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2352 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2353 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2354 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2355 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2356 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2357 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2358
2359 /* Disable PLL output */
2360 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2361
2362 /* Set operation mode to STANDBY and de-assert the reset */
2363 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2364 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2365 }
2366 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
2367
alpha_pll_lucid_evo_enable(struct clk_hw * hw)2368 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2369 {
2370 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2371 struct regmap *regmap = pll->clkr.regmap;
2372 u32 val;
2373 int ret;
2374
2375 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2376 if (ret)
2377 return ret;
2378
2379 /* If in FSM mode, just vote for it */
2380 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2381 ret = clk_enable_regmap(hw);
2382 if (ret)
2383 return ret;
2384 return wait_for_pll_enable_lock(pll);
2385 }
2386
2387 /* Check if PLL is already enabled */
2388 if (trion_pll_is_enabled(pll, regmap))
2389 return 0;
2390
2391 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2392 if (ret)
2393 return ret;
2394
2395 /* Set operation mode to RUN */
2396 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2397
2398 ret = wait_for_pll_enable_lock(pll);
2399 if (ret)
2400 return ret;
2401
2402 /* Enable the PLL outputs */
2403 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2404 if (ret)
2405 return ret;
2406
2407 /* Enable the global PLL outputs */
2408 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2409 if (ret)
2410 return ret;
2411
2412 /* Ensure that the write above goes through before returning. */
2413 mb();
2414 return ret;
2415 }
2416
_alpha_pll_lucid_evo_disable(struct clk_hw * hw,bool reset)2417 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2418 {
2419 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2420 struct regmap *regmap = pll->clkr.regmap;
2421 u32 val;
2422 int ret;
2423
2424 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2425 if (ret)
2426 return;
2427
2428 /* If in FSM mode, just unvote it */
2429 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2430 clk_disable_regmap(hw);
2431 return;
2432 }
2433
2434 /* Disable the global PLL output */
2435 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2436 if (ret)
2437 return;
2438
2439 /* Disable the PLL outputs */
2440 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2441 if (ret)
2442 return;
2443
2444 /* Place the PLL mode in STANDBY */
2445 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2446
2447 if (reset)
2448 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2449 }
2450
_alpha_pll_lucid_evo_prepare(struct clk_hw * hw,bool reset)2451 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2452 {
2453 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2454 struct clk_hw *p;
2455 u32 val = 0;
2456 int ret;
2457
2458 /* Return early if calibration is not needed. */
2459 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2460 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2461 return 0;
2462
2463 p = clk_hw_get_parent(hw);
2464 if (!p)
2465 return -EINVAL;
2466
2467 ret = alpha_pll_lucid_evo_enable(hw);
2468 if (ret)
2469 return ret;
2470
2471 _alpha_pll_lucid_evo_disable(hw, reset);
2472
2473 return 0;
2474 }
2475
alpha_pll_lucid_evo_disable(struct clk_hw * hw)2476 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2477 {
2478 _alpha_pll_lucid_evo_disable(hw, false);
2479 }
2480
alpha_pll_lucid_evo_prepare(struct clk_hw * hw)2481 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2482 {
2483 return _alpha_pll_lucid_evo_prepare(hw, false);
2484 }
2485
alpha_pll_reset_lucid_evo_disable(struct clk_hw * hw)2486 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2487 {
2488 _alpha_pll_lucid_evo_disable(hw, true);
2489 }
2490
alpha_pll_reset_lucid_evo_prepare(struct clk_hw * hw)2491 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2492 {
2493 return _alpha_pll_lucid_evo_prepare(hw, true);
2494 }
2495
alpha_pll_lucid_evo_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2496 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2497 unsigned long parent_rate)
2498 {
2499 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2500 struct regmap *regmap = pll->clkr.regmap;
2501 u32 l, frac;
2502
2503 if (regmap_read(regmap, PLL_L_VAL(pll), &l))
2504 return 0;
2505 l &= LUCID_EVO_PLL_L_VAL_MASK;
2506
2507 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac))
2508 return 0;
2509
2510 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2511 }
2512
clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2513 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2514 unsigned long parent_rate)
2515 {
2516 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2517 }
2518
2519 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2520 .enable = alpha_pll_lucid_evo_enable,
2521 .disable = alpha_pll_lucid_evo_disable,
2522 .is_enabled = clk_trion_pll_is_enabled,
2523 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2524 .round_rate = clk_alpha_pll_round_rate,
2525 };
2526 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2527
2528 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2529 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2530 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2531 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2532 };
2533 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2534
2535 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2536 .prepare = alpha_pll_lucid_evo_prepare,
2537 .enable = alpha_pll_lucid_evo_enable,
2538 .disable = alpha_pll_lucid_evo_disable,
2539 .is_enabled = clk_trion_pll_is_enabled,
2540 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2541 .round_rate = clk_alpha_pll_round_rate,
2542 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2543 };
2544 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2545
2546 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2547 .prepare = alpha_pll_reset_lucid_evo_prepare,
2548 .enable = alpha_pll_lucid_evo_enable,
2549 .disable = alpha_pll_reset_lucid_evo_disable,
2550 .is_enabled = clk_trion_pll_is_enabled,
2551 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2552 .round_rate = clk_alpha_pll_round_rate,
2553 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2554 };
2555 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2556
alpha_pll_pongo_elu_prepare(struct clk_hw * hw)2557 static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw)
2558 {
2559 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2560 struct regmap *regmap = pll->clkr.regmap;
2561 int ret;
2562
2563 /* Enable PLL intially to one-time calibrate against XO. */
2564 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2565 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2566 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT);
2567
2568 /* Set regmap for wait_for_pll() */
2569 pll->clkr.regmap = regmap;
2570 ret = wait_for_pll_enable_lock(pll);
2571 if (ret) {
2572 /* Reverse calibration - disable PLL output */
2573 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2574 return ret;
2575 }
2576
2577 /* Disable PLL after one-time calibration. */
2578 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2579
2580 /* Select internally generated clock. */
2581 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT,
2582 PONGO_CLOCK_SELECT);
2583
2584 return 0;
2585 }
2586
alpha_pll_pongo_elu_enable(struct clk_hw * hw)2587 static int alpha_pll_pongo_elu_enable(struct clk_hw *hw)
2588 {
2589 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2590 struct regmap *regmap = pll->clkr.regmap;
2591 int ret;
2592
2593 /* Check if PLL is already enabled */
2594 if (trion_pll_is_enabled(pll, regmap))
2595 return 0;
2596
2597 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2598 if (ret)
2599 return ret;
2600
2601 /* Set operation mode to RUN */
2602 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2603
2604 ret = wait_for_pll_enable_lock(pll);
2605 if (ret)
2606 return ret;
2607
2608 /* Enable the global PLL outputs */
2609 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2610 if (ret)
2611 return ret;
2612
2613 /* Ensure that the write above goes through before returning. */
2614 mb();
2615
2616 return ret;
2617 }
2618
alpha_pll_pongo_elu_disable(struct clk_hw * hw)2619 static void alpha_pll_pongo_elu_disable(struct clk_hw *hw)
2620 {
2621 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2622 struct regmap *regmap = pll->clkr.regmap;
2623 int ret;
2624
2625 /* Disable the global PLL output */
2626 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2627 if (ret)
2628 return;
2629
2630 /* Place the PLL mode in STANDBY */
2631 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2632 }
2633
alpha_pll_pongo_elu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2634 static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw,
2635 unsigned long parent_rate)
2636 {
2637 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2638 struct regmap *regmap = pll->clkr.regmap;
2639 u32 l;
2640
2641 if (regmap_read(regmap, PLL_L_VAL(pll), &l))
2642 return 0;
2643
2644 l &= PONGO_PLL_L_VAL_MASK;
2645
2646 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll));
2647 }
2648
2649 const struct clk_ops clk_alpha_pll_pongo_elu_ops = {
2650 .prepare = alpha_pll_pongo_elu_prepare,
2651 .enable = alpha_pll_pongo_elu_enable,
2652 .disable = alpha_pll_pongo_elu_disable,
2653 .recalc_rate = alpha_pll_pongo_elu_recalc_rate,
2654 };
2655 EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops);
2656
clk_pongo_elu_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2657 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll,
2658 struct regmap *regmap,
2659 const struct alpha_pll_config *config)
2660 {
2661 u32 val;
2662
2663 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK,
2664 PONGO_PLL_OUT_MASK);
2665
2666 if (trion_pll_is_enabled(pll, regmap))
2667 return;
2668
2669 if (regmap_read(regmap, PLL_L_VAL(pll), &val))
2670 return;
2671 val &= PONGO_PLL_L_VAL_MASK;
2672 if (val)
2673 return;
2674
2675 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2676 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2677 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2678 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2679 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2680 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val);
2681 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
2682 config->user_ctl_val | PONGO_PLL_OUT_MASK);
2683 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2684 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2685 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2686 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2687 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2688 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val);
2689
2690 /* Disable PLL output */
2691 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2692 }
2693 EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure);
2694
clk_rivian_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2695 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2696 const struct alpha_pll_config *config)
2697 {
2698 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2699 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2700 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2701 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2702 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2703 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2704 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2705 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2706
2707 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2708
2709 regmap_update_bits(regmap, PLL_MODE(pll),
2710 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2711 PLL_RESET_N | PLL_BYPASSNL);
2712 }
2713 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2714
clk_rivian_evo_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2715 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2716 unsigned long parent_rate)
2717 {
2718 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2719 u32 l;
2720
2721 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
2722 return 0;
2723
2724 return parent_rate * l;
2725 }
2726
clk_rivian_evo_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)2727 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2728 unsigned long *prate)
2729 {
2730 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2731 unsigned long min_freq, max_freq;
2732 u32 l;
2733 u64 a;
2734
2735 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2736 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2737 return rate;
2738
2739 min_freq = pll->vco_table[0].min_freq;
2740 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2741
2742 return clamp(rate, min_freq, max_freq);
2743 }
2744
2745 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2746 .enable = alpha_pll_lucid_5lpe_enable,
2747 .disable = alpha_pll_lucid_5lpe_disable,
2748 .is_enabled = clk_trion_pll_is_enabled,
2749 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2750 .round_rate = clk_rivian_evo_pll_round_rate,
2751 };
2752 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2753
clk_stromer_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2754 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2755 const struct alpha_pll_config *config)
2756 {
2757 u32 val, val_u, mask, mask_u;
2758
2759 regmap_write(regmap, PLL_L_VAL(pll), config->l);
2760 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2761 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2762
2763 if (pll_has_64bit_config(pll))
2764 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2765 config->config_ctl_hi_val);
2766
2767 if (pll_alpha_width(pll) > 32)
2768 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2769
2770 val = config->main_output_mask;
2771 val |= config->aux_output_mask;
2772 val |= config->aux2_output_mask;
2773 val |= config->early_output_mask;
2774 val |= config->pre_div_val;
2775 val |= config->post_div_val;
2776 val |= config->vco_val;
2777 val |= config->alpha_en_mask;
2778 val |= config->alpha_mode_mask;
2779
2780 mask = config->main_output_mask;
2781 mask |= config->aux_output_mask;
2782 mask |= config->aux2_output_mask;
2783 mask |= config->early_output_mask;
2784 mask |= config->pre_div_mask;
2785 mask |= config->post_div_mask;
2786 mask |= config->vco_mask;
2787 mask |= config->alpha_en_mask;
2788 mask |= config->alpha_mode_mask;
2789
2790 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2791
2792 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2793 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2794 val_u |= config->lock_det;
2795
2796 mask_u = config->status_mask;
2797 mask_u |= config->lock_det;
2798
2799 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2800 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2801 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2802
2803 if (pll->flags & SUPPORTS_FSM_MODE)
2804 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2805 }
2806 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2807
clk_alpha_pll_stromer_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)2808 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2809 struct clk_rate_request *req)
2810 {
2811 u32 l;
2812 u64 a;
2813
2814 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2815 &l, &a, ALPHA_REG_BITWIDTH);
2816
2817 return 0;
2818 }
2819
clk_alpha_pll_stromer_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2820 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2821 unsigned long prate)
2822 {
2823 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2824 int ret;
2825 u32 l;
2826 u64 a;
2827
2828 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2829
2830 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2831
2832 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
2833 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2834 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2835 a >> ALPHA_BITWIDTH);
2836
2837 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2838 PLL_ALPHA_EN, PLL_ALPHA_EN);
2839
2840 if (!clk_hw_is_enabled(hw))
2841 return 0;
2842
2843 /*
2844 * Stromer PLL supports Dynamic programming.
2845 * It allows the PLL frequency to be changed on-the-fly without first
2846 * execution of a shutdown procedure followed by a bring up procedure.
2847 */
2848 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2849 PLL_UPDATE);
2850
2851 ret = wait_for_pll_update(pll);
2852 if (ret)
2853 return ret;
2854
2855 return wait_for_pll_enable_lock(pll);
2856 }
2857
2858 const struct clk_ops clk_alpha_pll_stromer_ops = {
2859 .enable = clk_alpha_pll_enable,
2860 .disable = clk_alpha_pll_disable,
2861 .is_enabled = clk_alpha_pll_is_enabled,
2862 .recalc_rate = clk_alpha_pll_recalc_rate,
2863 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2864 .set_rate = clk_alpha_pll_stromer_set_rate,
2865 };
2866 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
2867
clk_alpha_pll_stromer_plus_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2868 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
2869 unsigned long rate,
2870 unsigned long prate)
2871 {
2872 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2873 u32 l, alpha_width = pll_alpha_width(pll);
2874 int ret, pll_mode;
2875 u64 a;
2876
2877 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2878
2879 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
2880 if (ret)
2881 return ret;
2882
2883 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
2884
2885 /* Delay of 2 output clock ticks required until output is disabled */
2886 udelay(1);
2887
2888 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2889
2890 if (alpha_width > ALPHA_BITWIDTH)
2891 a <<= alpha_width - ALPHA_BITWIDTH;
2892
2893 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2894 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2895 a >> ALPHA_BITWIDTH);
2896
2897 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2898 PLL_ALPHA_EN, PLL_ALPHA_EN);
2899
2900 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2901
2902 /* Wait five micro seconds or more */
2903 udelay(5);
2904 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2905 PLL_RESET_N);
2906
2907 /* The lock time should be less than 50 micro seconds worst case */
2908 usleep_range(50, 60);
2909
2910 ret = wait_for_pll_enable_lock(pll);
2911 if (ret) {
2912 pr_err("Wait for PLL enable lock failed [%s] %d\n",
2913 clk_hw_get_name(hw), ret);
2914 return ret;
2915 }
2916
2917 if (pll_mode & PLL_OUTCTRL)
2918 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
2919 PLL_OUTCTRL);
2920
2921 return 0;
2922 }
2923
2924 const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
2925 .prepare = clk_alpha_pll_enable,
2926 .unprepare = clk_alpha_pll_disable,
2927 .is_enabled = clk_alpha_pll_is_enabled,
2928 .recalc_rate = clk_alpha_pll_recalc_rate,
2929 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2930 .set_rate = clk_alpha_pll_stromer_plus_set_rate,
2931 };
2932 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
2933
clk_regera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2934 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2935 const struct alpha_pll_config *config)
2936 {
2937 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2938 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2939 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2940 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2941 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2942 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2943 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2944 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2945 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2946 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2947 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2948
2949 /* Set operation mode to STANDBY */
2950 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2951 }
2952 EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
2953
2954 const struct clk_ops clk_alpha_pll_regera_ops = {
2955 .enable = clk_zonda_pll_enable,
2956 .disable = clk_zonda_pll_disable,
2957 .is_enabled = clk_alpha_pll_is_enabled,
2958 .recalc_rate = clk_trion_pll_recalc_rate,
2959 .round_rate = clk_alpha_pll_round_rate,
2960 .set_rate = clk_zonda_pll_set_rate,
2961 };
2962 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
2963