1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-pll.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "common.h"
20 #include "gdsc.h"
21 #include "reset.h"
22
23 enum {
24 DT_BI_TCXO,
25 };
26
27 enum {
28 P_BI_TCXO,
29 P_CAM_CC_PLL0_OUT_EVEN,
30 P_CAM_CC_PLL0_OUT_MAIN,
31 P_CAM_CC_PLL0_OUT_ODD,
32 P_CAM_CC_PLL1_OUT_EVEN,
33 P_CAM_CC_PLL1_OUT_MAIN,
34 P_CAM_CC_PLL2_OUT_EVEN,
35 P_CAM_CC_PLL2_OUT_MAIN,
36 P_CAM_CC_PLL3_OUT_EVEN,
37 P_CAM_CC_PLL4_OUT_EVEN,
38 P_CAM_CC_PLL4_OUT_MAIN,
39 };
40
41 static const struct pll_vco lucid_evo_vco[] = {
42 { 249600000, 2020000000, 0 },
43 };
44
45 static const struct pll_vco rivian_evo_vco[] = {
46 { 864000000, 1056000000, 0 },
47 };
48
49 /* 1200.0 MHz Configuration */
50 static const struct alpha_pll_config cam_cc_pll0_config = {
51 .l = 0x3e,
52 .alpha = 0x8000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00008400,
57 .user_ctl_hi_val = 0x00000805,
58 };
59
60 static struct clk_alpha_pll cam_cc_pll0 = {
61 .offset = 0x0,
62 .vco_table = lucid_evo_vco,
63 .num_vco = ARRAY_SIZE(lucid_evo_vco),
64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
65 .clkr = {
66 .hw.init = &(const struct clk_init_data) {
67 .name = "cam_cc_pll0",
68 .parent_data = &(const struct clk_parent_data) {
69 .index = DT_BI_TCXO,
70 },
71 .num_parents = 1,
72 .ops = &clk_alpha_pll_lucid_evo_ops,
73 },
74 },
75 };
76
77 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
78 { 0x1, 2 },
79 { }
80 };
81
82 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
83 .offset = 0x0,
84 .post_div_shift = 10,
85 .post_div_table = post_div_table_cam_cc_pll0_out_even,
86 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
87 .width = 4,
88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
89 .clkr.hw.init = &(const struct clk_init_data) {
90 .name = "cam_cc_pll0_out_even",
91 .parent_hws = (const struct clk_hw*[]) {
92 &cam_cc_pll0.clkr.hw,
93 },
94 .num_parents = 1,
95 .flags = CLK_SET_RATE_PARENT,
96 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
97 },
98 };
99
100 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
101 { 0x2, 3 },
102 { }
103 };
104
105 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
106 .offset = 0x0,
107 .post_div_shift = 14,
108 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
109 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
110 .width = 4,
111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
112 .clkr.hw.init = &(const struct clk_init_data) {
113 .name = "cam_cc_pll0_out_odd",
114 .parent_hws = (const struct clk_hw*[]) {
115 &cam_cc_pll0.clkr.hw,
116 },
117 .num_parents = 1,
118 .flags = CLK_SET_RATE_PARENT,
119 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
120 },
121 };
122
123 /* 600.0 MHz Configuration */
124 static const struct alpha_pll_config cam_cc_pll1_config = {
125 .l = 0x1f,
126 .alpha = 0x4000,
127 .config_ctl_val = 0x20485699,
128 .config_ctl_hi_val = 0x00182261,
129 .config_ctl_hi1_val = 0x32aa299c,
130 .user_ctl_val = 0x00000400,
131 .user_ctl_hi_val = 0x00000805,
132 };
133
134 static struct clk_alpha_pll cam_cc_pll1 = {
135 .offset = 0x1000,
136 .vco_table = lucid_evo_vco,
137 .num_vco = ARRAY_SIZE(lucid_evo_vco),
138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
139 .clkr = {
140 .hw.init = &(const struct clk_init_data) {
141 .name = "cam_cc_pll1",
142 .parent_data = &(const struct clk_parent_data) {
143 .index = DT_BI_TCXO,
144 },
145 .num_parents = 1,
146 .ops = &clk_alpha_pll_lucid_evo_ops,
147 },
148 },
149 };
150
151 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
152 { 0x1, 2 },
153 { }
154 };
155
156 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
157 .offset = 0x1000,
158 .post_div_shift = 10,
159 .post_div_table = post_div_table_cam_cc_pll1_out_even,
160 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
161 .width = 4,
162 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
163 .clkr.hw.init = &(const struct clk_init_data) {
164 .name = "cam_cc_pll1_out_even",
165 .parent_hws = (const struct clk_hw*[]) {
166 &cam_cc_pll1.clkr.hw,
167 },
168 .num_parents = 1,
169 .flags = CLK_SET_RATE_PARENT,
170 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
171 },
172 };
173
174 /* 960.0 MHz Configuration */
175 static const struct alpha_pll_config cam_cc_pll2_config = {
176 .l = 0x32,
177 .alpha = 0x0,
178 .config_ctl_val = 0x90008820,
179 .config_ctl_hi_val = 0x00890263,
180 .config_ctl_hi1_val = 0x00000247,
181 .user_ctl_val = 0x00000400,
182 .user_ctl_hi_val = 0x00400000,
183 };
184
185 static struct clk_alpha_pll cam_cc_pll2 = {
186 .offset = 0x2000,
187 .vco_table = rivian_evo_vco,
188 .num_vco = ARRAY_SIZE(rivian_evo_vco),
189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
190 .clkr = {
191 .hw.init = &(const struct clk_init_data) {
192 .name = "cam_cc_pll2",
193 .parent_data = &(const struct clk_parent_data) {
194 .index = DT_BI_TCXO,
195 },
196 .num_parents = 1,
197 .ops = &clk_alpha_pll_rivian_evo_ops,
198 },
199 },
200 };
201
202 static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = {
203 { 0x1, 2 },
204 { }
205 };
206
207 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
208 .offset = 0x2000,
209 .post_div_shift = 10,
210 .post_div_table = post_div_table_cam_cc_pll2_out_even,
211 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even),
212 .width = 4,
213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
214 .clkr.hw.init = &(const struct clk_init_data) {
215 .name = "cam_cc_pll2_out_even",
216 .parent_hws = (const struct clk_hw*[]) {
217 &cam_cc_pll2.clkr.hw,
218 },
219 .num_parents = 1,
220 .flags = CLK_SET_RATE_PARENT,
221 .ops = &clk_alpha_pll_postdiv_rivian_evo_ops,
222 },
223 };
224
225 /* 600.0 MHz Configuration */
226 static const struct alpha_pll_config cam_cc_pll3_config = {
227 .l = 0x1f,
228 .alpha = 0x4000,
229 .config_ctl_val = 0x20485699,
230 .config_ctl_hi_val = 0x00182261,
231 .config_ctl_hi1_val = 0x32aa299c,
232 .user_ctl_val = 0x00000400,
233 .user_ctl_hi_val = 0x00000805,
234 };
235
236 static struct clk_alpha_pll cam_cc_pll3 = {
237 .offset = 0x3000,
238 .vco_table = lucid_evo_vco,
239 .num_vco = ARRAY_SIZE(lucid_evo_vco),
240 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
241 .clkr = {
242 .hw.init = &(const struct clk_init_data) {
243 .name = "cam_cc_pll3",
244 .parent_data = &(const struct clk_parent_data) {
245 .index = DT_BI_TCXO,
246 },
247 .num_parents = 1,
248 .ops = &clk_alpha_pll_lucid_evo_ops,
249 },
250 },
251 };
252
253 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
254 { 0x1, 2 },
255 { }
256 };
257
258 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
259 .offset = 0x3000,
260 .post_div_shift = 10,
261 .post_div_table = post_div_table_cam_cc_pll3_out_even,
262 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
263 .width = 4,
264 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
265 .clkr.hw.init = &(const struct clk_init_data) {
266 .name = "cam_cc_pll3_out_even",
267 .parent_hws = (const struct clk_hw*[]) {
268 &cam_cc_pll3.clkr.hw,
269 },
270 .num_parents = 1,
271 .flags = CLK_SET_RATE_PARENT,
272 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
273 },
274 };
275
276 /* 700.0 MHz Configuration */
277 static const struct alpha_pll_config cam_cc_pll4_config = {
278 .l = 0x24,
279 .alpha = 0x7555,
280 .config_ctl_val = 0x20485699,
281 .config_ctl_hi_val = 0x00182261,
282 .config_ctl_hi1_val = 0x32aa299c,
283 .user_ctl_val = 0x00000400,
284 .user_ctl_hi_val = 0x00000805,
285 };
286
287 static struct clk_alpha_pll cam_cc_pll4 = {
288 .offset = 0x4000,
289 .vco_table = lucid_evo_vco,
290 .num_vco = ARRAY_SIZE(lucid_evo_vco),
291 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
292 .clkr = {
293 .hw.init = &(const struct clk_init_data) {
294 .name = "cam_cc_pll4",
295 .parent_data = &(const struct clk_parent_data) {
296 .index = DT_BI_TCXO,
297 },
298 .num_parents = 1,
299 .ops = &clk_alpha_pll_lucid_evo_ops,
300 },
301 },
302 };
303
304 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
305 { 0x1, 2 },
306 { }
307 };
308
309 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
310 .offset = 0x4000,
311 .post_div_shift = 10,
312 .post_div_table = post_div_table_cam_cc_pll4_out_even,
313 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
314 .width = 4,
315 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
316 .clkr.hw.init = &(const struct clk_init_data) {
317 .name = "cam_cc_pll4_out_even",
318 .parent_hws = (const struct clk_hw*[]) {
319 &cam_cc_pll4.clkr.hw,
320 },
321 .num_parents = 1,
322 .flags = CLK_SET_RATE_PARENT,
323 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
324 },
325 };
326
327 static const struct parent_map cam_cc_parent_map_0[] = {
328 { P_BI_TCXO, 0 },
329 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
330 { P_CAM_CC_PLL0_OUT_ODD, 5 },
331 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
332 };
333
334 static const struct clk_parent_data cam_cc_parent_data_0[] = {
335 { .index = DT_BI_TCXO },
336 { .hw = &cam_cc_pll0.clkr.hw },
337 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
338 { .hw = &cam_cc_pll0_out_even.clkr.hw },
339 };
340
341 static const struct parent_map cam_cc_parent_map_1[] = {
342 { P_BI_TCXO, 0 },
343 { P_CAM_CC_PLL2_OUT_EVEN, 3 },
344 { P_CAM_CC_PLL2_OUT_MAIN, 4 },
345 };
346
347 static const struct clk_parent_data cam_cc_parent_data_1[] = {
348 { .index = DT_BI_TCXO },
349 { .hw = &cam_cc_pll2_out_even.clkr.hw },
350 { .hw = &cam_cc_pll2.clkr.hw },
351 };
352
353 static const struct parent_map cam_cc_parent_map_2[] = {
354 { P_BI_TCXO, 0 },
355 { P_CAM_CC_PLL0_OUT_ODD, 5 },
356 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
357 };
358
359 static const struct clk_parent_data cam_cc_parent_data_2[] = {
360 { .index = DT_BI_TCXO },
361 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
362 { .hw = &cam_cc_pll0_out_even.clkr.hw },
363 };
364
365 static const struct parent_map cam_cc_parent_map_3[] = {
366 { P_BI_TCXO, 0 },
367 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
368 { P_CAM_CC_PLL4_OUT_EVEN, 2 },
369 { P_CAM_CC_PLL4_OUT_MAIN, 3 },
370 { P_CAM_CC_PLL0_OUT_ODD, 5 },
371 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
372 };
373
374 static const struct clk_parent_data cam_cc_parent_data_3[] = {
375 { .index = DT_BI_TCXO },
376 { .hw = &cam_cc_pll0.clkr.hw },
377 { .hw = &cam_cc_pll4_out_even.clkr.hw },
378 { .hw = &cam_cc_pll4.clkr.hw },
379 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
380 { .hw = &cam_cc_pll0_out_even.clkr.hw },
381 };
382
383 static const struct parent_map cam_cc_parent_map_4[] = {
384 { P_BI_TCXO, 0 },
385 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
386 { P_CAM_CC_PLL1_OUT_MAIN, 2 },
387 { P_CAM_CC_PLL1_OUT_EVEN, 3 },
388 { P_CAM_CC_PLL0_OUT_ODD, 5 },
389 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
390 };
391
392 static const struct clk_parent_data cam_cc_parent_data_4[] = {
393 { .index = DT_BI_TCXO },
394 { .hw = &cam_cc_pll0.clkr.hw },
395 { .hw = &cam_cc_pll1.clkr.hw },
396 { .hw = &cam_cc_pll1_out_even.clkr.hw },
397 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
398 { .hw = &cam_cc_pll0_out_even.clkr.hw },
399 };
400
401 static const struct parent_map cam_cc_parent_map_5[] = {
402 { P_BI_TCXO, 0 },
403 { P_CAM_CC_PLL1_OUT_MAIN, 2 },
404 { P_CAM_CC_PLL1_OUT_EVEN, 3 },
405 };
406
407 static const struct clk_parent_data cam_cc_parent_data_5[] = {
408 { .index = DT_BI_TCXO },
409 { .hw = &cam_cc_pll1.clkr.hw },
410 { .hw = &cam_cc_pll1_out_even.clkr.hw },
411 };
412
413 static const struct parent_map cam_cc_parent_map_6[] = {
414 { P_BI_TCXO, 0 },
415 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
416 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
417 };
418
419 static const struct clk_parent_data cam_cc_parent_data_6[] = {
420 { .index = DT_BI_TCXO },
421 { .hw = &cam_cc_pll0.clkr.hw },
422 { .hw = &cam_cc_pll0_out_even.clkr.hw },
423 };
424
425 static const struct parent_map cam_cc_parent_map_7[] = {
426 { P_BI_TCXO, 0 },
427 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
428 { P_CAM_CC_PLL3_OUT_EVEN, 5 },
429 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
430 };
431
432 static const struct clk_parent_data cam_cc_parent_data_7[] = {
433 { .index = DT_BI_TCXO },
434 { .hw = &cam_cc_pll0.clkr.hw },
435 { .hw = &cam_cc_pll3_out_even.clkr.hw },
436 { .hw = &cam_cc_pll0_out_even.clkr.hw },
437 };
438
439 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
440 F(19200000, P_BI_TCXO, 1, 0, 0),
441 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
442 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
443 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
444 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
445 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
446 { }
447 };
448
449 static struct clk_rcg2 cam_cc_bps_clk_src = {
450 .cmd_rcgr = 0xa004,
451 .mnd_width = 0,
452 .hid_width = 5,
453 .parent_map = cam_cc_parent_map_4,
454 .freq_tbl = ftbl_cam_cc_bps_clk_src,
455 .clkr.hw.init = &(const struct clk_init_data) {
456 .name = "cam_cc_bps_clk_src",
457 .parent_data = cam_cc_parent_data_4,
458 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
459 .flags = CLK_SET_RATE_PARENT,
460 .ops = &clk_rcg2_shared_ops,
461 },
462 };
463
464 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
465 F(19200000, P_BI_TCXO, 1, 0, 0),
466 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
467 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
468 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
469 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
470 { }
471 };
472
473 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
474 .cmd_rcgr = 0x13014,
475 .mnd_width = 0,
476 .hid_width = 5,
477 .parent_map = cam_cc_parent_map_0,
478 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
479 .clkr.hw.init = &(const struct clk_init_data) {
480 .name = "cam_cc_camnoc_axi_clk_src",
481 .parent_data = cam_cc_parent_data_0,
482 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
483 .flags = CLK_SET_RATE_PARENT,
484 .ops = &clk_rcg2_shared_ops,
485 },
486 };
487
488 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
489 F(19200000, P_BI_TCXO, 1, 0, 0),
490 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
491 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
492 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
493 { }
494 };
495
496 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
497 .cmd_rcgr = 0x10004,
498 .mnd_width = 8,
499 .hid_width = 5,
500 .parent_map = cam_cc_parent_map_2,
501 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
502 .clkr.hw.init = &(const struct clk_init_data) {
503 .name = "cam_cc_cci_0_clk_src",
504 .parent_data = cam_cc_parent_data_2,
505 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
506 .flags = CLK_SET_RATE_PARENT,
507 .ops = &clk_rcg2_shared_ops,
508 },
509 };
510
511 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
512 .cmd_rcgr = 0x11004,
513 .mnd_width = 8,
514 .hid_width = 5,
515 .parent_map = cam_cc_parent_map_2,
516 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
517 .clkr.hw.init = &(const struct clk_init_data) {
518 .name = "cam_cc_cci_1_clk_src",
519 .parent_data = cam_cc_parent_data_2,
520 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
521 .flags = CLK_SET_RATE_PARENT,
522 .ops = &clk_rcg2_shared_ops,
523 },
524 };
525
526 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
527 F(19200000, P_BI_TCXO, 1, 0, 0),
528 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
529 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
530 { }
531 };
532
533 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
534 .cmd_rcgr = 0xc054,
535 .mnd_width = 0,
536 .hid_width = 5,
537 .parent_map = cam_cc_parent_map_0,
538 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
539 .clkr.hw.init = &(const struct clk_init_data) {
540 .name = "cam_cc_cphy_rx_clk_src",
541 .parent_data = cam_cc_parent_data_0,
542 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
543 .flags = CLK_SET_RATE_PARENT,
544 .ops = &clk_rcg2_shared_ops,
545 },
546 };
547
548 static struct clk_rcg2 cam_cc_cre_clk_src = {
549 .cmd_rcgr = 0x16004,
550 .mnd_width = 0,
551 .hid_width = 5,
552 .parent_map = cam_cc_parent_map_5,
553 .freq_tbl = ftbl_cam_cc_bps_clk_src,
554 .clkr.hw.init = &(const struct clk_init_data) {
555 .name = "cam_cc_cre_clk_src",
556 .parent_data = cam_cc_parent_data_5,
557 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
558 .flags = CLK_SET_RATE_PARENT,
559 .ops = &clk_rcg2_shared_ops,
560 },
561 };
562
563 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
564 F(19200000, P_BI_TCXO, 1, 0, 0),
565 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
566 { }
567 };
568
569 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
570 .cmd_rcgr = 0x9004,
571 .mnd_width = 0,
572 .hid_width = 5,
573 .parent_map = cam_cc_parent_map_0,
574 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
575 .clkr.hw.init = &(const struct clk_init_data) {
576 .name = "cam_cc_csi0phytimer_clk_src",
577 .parent_data = cam_cc_parent_data_0,
578 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
579 .flags = CLK_SET_RATE_PARENT,
580 .ops = &clk_rcg2_shared_ops,
581 },
582 };
583
584 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
585 .cmd_rcgr = 0x9028,
586 .mnd_width = 0,
587 .hid_width = 5,
588 .parent_map = cam_cc_parent_map_0,
589 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
590 .clkr.hw.init = &(const struct clk_init_data) {
591 .name = "cam_cc_csi1phytimer_clk_src",
592 .parent_data = cam_cc_parent_data_0,
593 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
594 .flags = CLK_SET_RATE_PARENT,
595 .ops = &clk_rcg2_shared_ops,
596 },
597 };
598
599 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
600 .cmd_rcgr = 0x904c,
601 .mnd_width = 0,
602 .hid_width = 5,
603 .parent_map = cam_cc_parent_map_0,
604 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
605 .clkr.hw.init = &(const struct clk_init_data) {
606 .name = "cam_cc_csi2phytimer_clk_src",
607 .parent_data = cam_cc_parent_data_0,
608 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
609 .flags = CLK_SET_RATE_PARENT,
610 .ops = &clk_rcg2_shared_ops,
611 },
612 };
613
614 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
615 F(19200000, P_BI_TCXO, 1, 0, 0),
616 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
617 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
618 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0),
619 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0),
620 { }
621 };
622
623 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
624 .cmd_rcgr = 0xa02c,
625 .mnd_width = 0,
626 .hid_width = 5,
627 .parent_map = cam_cc_parent_map_0,
628 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
629 .clkr.hw.init = &(const struct clk_init_data) {
630 .name = "cam_cc_fast_ahb_clk_src",
631 .parent_data = cam_cc_parent_data_0,
632 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
633 .flags = CLK_SET_RATE_PARENT,
634 .ops = &clk_rcg2_shared_ops,
635 },
636 };
637
638 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
639 F(19200000, P_BI_TCXO, 1, 0, 0),
640 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
641 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
642 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
643 { }
644 };
645
646 static struct clk_rcg2 cam_cc_icp_clk_src = {
647 .cmd_rcgr = 0xf014,
648 .mnd_width = 0,
649 .hid_width = 5,
650 .parent_map = cam_cc_parent_map_6,
651 .freq_tbl = ftbl_cam_cc_icp_clk_src,
652 .clkr.hw.init = &(const struct clk_init_data) {
653 .name = "cam_cc_icp_clk_src",
654 .parent_data = cam_cc_parent_data_6,
655 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
656 .flags = CLK_SET_RATE_PARENT,
657 .ops = &clk_rcg2_shared_ops,
658 },
659 };
660
661 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
662 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50),
663 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
664 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0),
665 { }
666 };
667
668 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
669 .cmd_rcgr = 0x8004,
670 .mnd_width = 8,
671 .hid_width = 5,
672 .parent_map = cam_cc_parent_map_1,
673 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
674 .clkr.hw.init = &(const struct clk_init_data) {
675 .name = "cam_cc_mclk0_clk_src",
676 .parent_data = cam_cc_parent_data_1,
677 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
678 .flags = CLK_SET_RATE_PARENT,
679 .ops = &clk_rcg2_shared_ops,
680 },
681 };
682
683 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
684 .cmd_rcgr = 0x8024,
685 .mnd_width = 8,
686 .hid_width = 5,
687 .parent_map = cam_cc_parent_map_1,
688 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
689 .clkr.hw.init = &(const struct clk_init_data) {
690 .name = "cam_cc_mclk1_clk_src",
691 .parent_data = cam_cc_parent_data_1,
692 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
693 .flags = CLK_SET_RATE_PARENT,
694 .ops = &clk_rcg2_shared_ops,
695 },
696 };
697
698 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
699 .cmd_rcgr = 0x8044,
700 .mnd_width = 8,
701 .hid_width = 5,
702 .parent_map = cam_cc_parent_map_1,
703 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
704 .clkr.hw.init = &(const struct clk_init_data) {
705 .name = "cam_cc_mclk2_clk_src",
706 .parent_data = cam_cc_parent_data_1,
707 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
708 .flags = CLK_SET_RATE_PARENT,
709 .ops = &clk_rcg2_shared_ops,
710 },
711 };
712
713 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
714 .cmd_rcgr = 0x8064,
715 .mnd_width = 8,
716 .hid_width = 5,
717 .parent_map = cam_cc_parent_map_1,
718 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
719 .clkr.hw.init = &(const struct clk_init_data) {
720 .name = "cam_cc_mclk3_clk_src",
721 .parent_data = cam_cc_parent_data_1,
722 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
723 .flags = CLK_SET_RATE_PARENT,
724 .ops = &clk_rcg2_shared_ops,
725 },
726 };
727
728 static const struct freq_tbl ftbl_cam_cc_ope_0_clk_src[] = {
729 F(19200000, P_BI_TCXO, 1, 0, 0),
730 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
731 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
732 F(460000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
733 F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
734 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
735 { }
736 };
737
738 static struct clk_rcg2 cam_cc_ope_0_clk_src = {
739 .cmd_rcgr = 0xb004,
740 .mnd_width = 0,
741 .hid_width = 5,
742 .parent_map = cam_cc_parent_map_7,
743 .freq_tbl = ftbl_cam_cc_ope_0_clk_src,
744 .clkr.hw.init = &(const struct clk_init_data) {
745 .name = "cam_cc_ope_0_clk_src",
746 .parent_data = cam_cc_parent_data_7,
747 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
748 .flags = CLK_SET_RATE_PARENT,
749 .ops = &clk_rcg2_shared_ops,
750 },
751 };
752
753 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
754 F(19200000, P_BI_TCXO, 1, 0, 0),
755 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
756 { }
757 };
758
759 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
760 .cmd_rcgr = 0xa048,
761 .mnd_width = 0,
762 .hid_width = 5,
763 .parent_map = cam_cc_parent_map_0,
764 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
765 .clkr.hw.init = &(const struct clk_init_data) {
766 .name = "cam_cc_slow_ahb_clk_src",
767 .parent_data = cam_cc_parent_data_0,
768 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
769 .flags = CLK_SET_RATE_PARENT,
770 .ops = &clk_rcg2_shared_ops,
771 },
772 };
773
774 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = {
775 F(19200000, P_BI_TCXO, 1, 0, 0),
776 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
777 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
778 F(548000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
779 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
780 { }
781 };
782
783 static struct clk_rcg2 cam_cc_tfe_0_clk_src = {
784 .cmd_rcgr = 0xc004,
785 .mnd_width = 0,
786 .hid_width = 5,
787 .parent_map = cam_cc_parent_map_3,
788 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src,
789 .clkr.hw.init = &(const struct clk_init_data) {
790 .name = "cam_cc_tfe_0_clk_src",
791 .parent_data = cam_cc_parent_data_3,
792 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
793 .flags = CLK_SET_RATE_PARENT,
794 .ops = &clk_rcg2_shared_ops,
795 },
796 };
797
798 static struct clk_rcg2 cam_cc_tfe_0_csid_clk_src = {
799 .cmd_rcgr = 0xc02c,
800 .mnd_width = 0,
801 .hid_width = 5,
802 .parent_map = cam_cc_parent_map_0,
803 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
804 .clkr.hw.init = &(const struct clk_init_data) {
805 .name = "cam_cc_tfe_0_csid_clk_src",
806 .parent_data = cam_cc_parent_data_0,
807 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
808 .flags = CLK_SET_RATE_PARENT,
809 .ops = &clk_rcg2_shared_ops,
810 },
811 };
812
813 static struct clk_rcg2 cam_cc_tfe_1_clk_src = {
814 .cmd_rcgr = 0xd004,
815 .mnd_width = 0,
816 .hid_width = 5,
817 .parent_map = cam_cc_parent_map_3,
818 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src,
819 .clkr.hw.init = &(const struct clk_init_data) {
820 .name = "cam_cc_tfe_1_clk_src",
821 .parent_data = cam_cc_parent_data_3,
822 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
823 .flags = CLK_SET_RATE_PARENT,
824 .ops = &clk_rcg2_shared_ops,
825 },
826 };
827
828 static struct clk_rcg2 cam_cc_tfe_1_csid_clk_src = {
829 .cmd_rcgr = 0xd024,
830 .mnd_width = 0,
831 .hid_width = 5,
832 .parent_map = cam_cc_parent_map_0,
833 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
834 .clkr.hw.init = &(const struct clk_init_data) {
835 .name = "cam_cc_tfe_1_csid_clk_src",
836 .parent_data = cam_cc_parent_data_0,
837 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
838 .flags = CLK_SET_RATE_PARENT,
839 .ops = &clk_rcg2_shared_ops,
840 },
841 };
842
843 static struct clk_branch cam_cc_bps_ahb_clk = {
844 .halt_reg = 0xa060,
845 .halt_check = BRANCH_HALT,
846 .clkr = {
847 .enable_reg = 0xa060,
848 .enable_mask = BIT(0),
849 .hw.init = &(const struct clk_init_data) {
850 .name = "cam_cc_bps_ahb_clk",
851 .parent_hws = (const struct clk_hw*[]) {
852 &cam_cc_slow_ahb_clk_src.clkr.hw,
853 },
854 .num_parents = 1,
855 .flags = CLK_SET_RATE_PARENT,
856 .ops = &clk_branch2_ops,
857 },
858 },
859 };
860
861 static struct clk_branch cam_cc_bps_areg_clk = {
862 .halt_reg = 0xa044,
863 .halt_check = BRANCH_HALT,
864 .clkr = {
865 .enable_reg = 0xa044,
866 .enable_mask = BIT(0),
867 .hw.init = &(const struct clk_init_data) {
868 .name = "cam_cc_bps_areg_clk",
869 .parent_hws = (const struct clk_hw*[]) {
870 &cam_cc_fast_ahb_clk_src.clkr.hw,
871 },
872 .num_parents = 1,
873 .flags = CLK_SET_RATE_PARENT,
874 .ops = &clk_branch2_ops,
875 },
876 },
877 };
878
879 static struct clk_branch cam_cc_bps_clk = {
880 .halt_reg = 0xa01c,
881 .halt_check = BRANCH_HALT,
882 .clkr = {
883 .enable_reg = 0xa01c,
884 .enable_mask = BIT(0),
885 .hw.init = &(const struct clk_init_data) {
886 .name = "cam_cc_bps_clk",
887 .parent_hws = (const struct clk_hw*[]) {
888 &cam_cc_bps_clk_src.clkr.hw,
889 },
890 .num_parents = 1,
891 .flags = CLK_SET_RATE_PARENT,
892 .ops = &clk_branch2_ops,
893 },
894 },
895 };
896
897 static struct clk_branch cam_cc_camnoc_atb_clk = {
898 .halt_reg = 0x13034,
899 .halt_check = BRANCH_HALT,
900 .clkr = {
901 .enable_reg = 0x13034,
902 .enable_mask = BIT(0),
903 .hw.init = &(const struct clk_init_data) {
904 .name = "cam_cc_camnoc_atb_clk",
905 .ops = &clk_branch2_ops,
906 },
907 },
908 };
909
910 static struct clk_branch cam_cc_camnoc_axi_clk = {
911 .halt_reg = 0x1302c,
912 .halt_check = BRANCH_HALT,
913 .clkr = {
914 .enable_reg = 0x1302c,
915 .enable_mask = BIT(0),
916 .hw.init = &(const struct clk_init_data) {
917 .name = "cam_cc_camnoc_axi_clk",
918 .parent_hws = (const struct clk_hw*[]) {
919 &cam_cc_camnoc_axi_clk_src.clkr.hw,
920 },
921 .num_parents = 1,
922 .flags = CLK_SET_RATE_PARENT,
923 .ops = &clk_branch2_ops,
924 },
925 },
926 };
927
928 static struct clk_branch cam_cc_camnoc_axi_hf_clk = {
929 .halt_reg = 0x1300c,
930 .halt_check = BRANCH_HALT,
931 .clkr = {
932 .enable_reg = 0x1300c,
933 .enable_mask = BIT(0),
934 .hw.init = &(const struct clk_init_data) {
935 .name = "cam_cc_camnoc_axi_hf_clk",
936 .ops = &clk_branch2_ops,
937 },
938 },
939 };
940
941 static struct clk_branch cam_cc_camnoc_axi_sf_clk = {
942 .halt_reg = 0x13004,
943 .halt_check = BRANCH_HALT,
944 .clkr = {
945 .enable_reg = 0x13004,
946 .enable_mask = BIT(0),
947 .hw.init = &(const struct clk_init_data) {
948 .name = "cam_cc_camnoc_axi_sf_clk",
949 .ops = &clk_branch2_ops,
950 },
951 },
952 };
953
954 static struct clk_branch cam_cc_cci_0_clk = {
955 .halt_reg = 0x1001c,
956 .halt_check = BRANCH_HALT,
957 .clkr = {
958 .enable_reg = 0x1001c,
959 .enable_mask = BIT(0),
960 .hw.init = &(const struct clk_init_data) {
961 .name = "cam_cc_cci_0_clk",
962 .parent_hws = (const struct clk_hw*[]) {
963 &cam_cc_cci_0_clk_src.clkr.hw,
964 },
965 .num_parents = 1,
966 .flags = CLK_SET_RATE_PARENT,
967 .ops = &clk_branch2_ops,
968 },
969 },
970 };
971
972 static struct clk_branch cam_cc_cci_1_clk = {
973 .halt_reg = 0x1101c,
974 .halt_check = BRANCH_HALT,
975 .clkr = {
976 .enable_reg = 0x1101c,
977 .enable_mask = BIT(0),
978 .hw.init = &(const struct clk_init_data) {
979 .name = "cam_cc_cci_1_clk",
980 .parent_hws = (const struct clk_hw*[]) {
981 &cam_cc_cci_1_clk_src.clkr.hw,
982 },
983 .num_parents = 1,
984 .flags = CLK_SET_RATE_PARENT,
985 .ops = &clk_branch2_ops,
986 },
987 },
988 };
989
990 static struct clk_branch cam_cc_core_ahb_clk = {
991 .halt_reg = 0x1401c,
992 .halt_check = BRANCH_HALT_DELAY,
993 .clkr = {
994 .enable_reg = 0x1401c,
995 .enable_mask = BIT(0),
996 .hw.init = &(const struct clk_init_data) {
997 .name = "cam_cc_core_ahb_clk",
998 .parent_hws = (const struct clk_hw*[]) {
999 &cam_cc_slow_ahb_clk_src.clkr.hw,
1000 },
1001 .num_parents = 1,
1002 .flags = CLK_SET_RATE_PARENT,
1003 .ops = &clk_branch2_ops,
1004 },
1005 },
1006 };
1007
1008 static struct clk_branch cam_cc_cpas_ahb_clk = {
1009 .halt_reg = 0x12004,
1010 .halt_check = BRANCH_HALT,
1011 .clkr = {
1012 .enable_reg = 0x12004,
1013 .enable_mask = BIT(0),
1014 .hw.init = &(const struct clk_init_data) {
1015 .name = "cam_cc_cpas_ahb_clk",
1016 .parent_hws = (const struct clk_hw*[]) {
1017 &cam_cc_slow_ahb_clk_src.clkr.hw,
1018 },
1019 .num_parents = 1,
1020 .flags = CLK_SET_RATE_PARENT,
1021 .ops = &clk_branch2_ops,
1022 },
1023 },
1024 };
1025
1026 static struct clk_branch cam_cc_cre_ahb_clk = {
1027 .halt_reg = 0x16020,
1028 .halt_check = BRANCH_HALT,
1029 .clkr = {
1030 .enable_reg = 0x16020,
1031 .enable_mask = BIT(0),
1032 .hw.init = &(const struct clk_init_data) {
1033 .name = "cam_cc_cre_ahb_clk",
1034 .parent_hws = (const struct clk_hw*[]) {
1035 &cam_cc_slow_ahb_clk_src.clkr.hw,
1036 },
1037 .num_parents = 1,
1038 .flags = CLK_SET_RATE_PARENT,
1039 .ops = &clk_branch2_ops,
1040 },
1041 },
1042 };
1043
1044 static struct clk_branch cam_cc_cre_clk = {
1045 .halt_reg = 0x1601c,
1046 .halt_check = BRANCH_HALT,
1047 .clkr = {
1048 .enable_reg = 0x1601c,
1049 .enable_mask = BIT(0),
1050 .hw.init = &(const struct clk_init_data) {
1051 .name = "cam_cc_cre_clk",
1052 .parent_hws = (const struct clk_hw*[]) {
1053 &cam_cc_cre_clk_src.clkr.hw,
1054 },
1055 .num_parents = 1,
1056 .flags = CLK_SET_RATE_PARENT,
1057 .ops = &clk_branch2_ops,
1058 },
1059 },
1060 };
1061
1062 static struct clk_branch cam_cc_csi0phytimer_clk = {
1063 .halt_reg = 0x901c,
1064 .halt_check = BRANCH_HALT,
1065 .clkr = {
1066 .enable_reg = 0x901c,
1067 .enable_mask = BIT(0),
1068 .hw.init = &(const struct clk_init_data) {
1069 .name = "cam_cc_csi0phytimer_clk",
1070 .parent_hws = (const struct clk_hw*[]) {
1071 &cam_cc_csi0phytimer_clk_src.clkr.hw,
1072 },
1073 .num_parents = 1,
1074 .flags = CLK_SET_RATE_PARENT,
1075 .ops = &clk_branch2_ops,
1076 },
1077 },
1078 };
1079
1080 static struct clk_branch cam_cc_csi1phytimer_clk = {
1081 .halt_reg = 0x9040,
1082 .halt_check = BRANCH_HALT,
1083 .clkr = {
1084 .enable_reg = 0x9040,
1085 .enable_mask = BIT(0),
1086 .hw.init = &(const struct clk_init_data) {
1087 .name = "cam_cc_csi1phytimer_clk",
1088 .parent_hws = (const struct clk_hw*[]) {
1089 &cam_cc_csi1phytimer_clk_src.clkr.hw,
1090 },
1091 .num_parents = 1,
1092 .flags = CLK_SET_RATE_PARENT,
1093 .ops = &clk_branch2_ops,
1094 },
1095 },
1096 };
1097
1098 static struct clk_branch cam_cc_csi2phytimer_clk = {
1099 .halt_reg = 0x9064,
1100 .halt_check = BRANCH_HALT,
1101 .clkr = {
1102 .enable_reg = 0x9064,
1103 .enable_mask = BIT(0),
1104 .hw.init = &(const struct clk_init_data) {
1105 .name = "cam_cc_csi2phytimer_clk",
1106 .parent_hws = (const struct clk_hw*[]) {
1107 &cam_cc_csi2phytimer_clk_src.clkr.hw,
1108 },
1109 .num_parents = 1,
1110 .flags = CLK_SET_RATE_PARENT,
1111 .ops = &clk_branch2_ops,
1112 },
1113 },
1114 };
1115
1116 static struct clk_branch cam_cc_csiphy0_clk = {
1117 .halt_reg = 0x9020,
1118 .halt_check = BRANCH_HALT,
1119 .clkr = {
1120 .enable_reg = 0x9020,
1121 .enable_mask = BIT(0),
1122 .hw.init = &(const struct clk_init_data) {
1123 .name = "cam_cc_csiphy0_clk",
1124 .parent_hws = (const struct clk_hw*[]) {
1125 &cam_cc_cphy_rx_clk_src.clkr.hw,
1126 },
1127 .num_parents = 1,
1128 .flags = CLK_SET_RATE_PARENT,
1129 .ops = &clk_branch2_ops,
1130 },
1131 },
1132 };
1133
1134 static struct clk_branch cam_cc_csiphy1_clk = {
1135 .halt_reg = 0x9044,
1136 .halt_check = BRANCH_HALT,
1137 .clkr = {
1138 .enable_reg = 0x9044,
1139 .enable_mask = BIT(0),
1140 .hw.init = &(const struct clk_init_data) {
1141 .name = "cam_cc_csiphy1_clk",
1142 .parent_hws = (const struct clk_hw*[]) {
1143 &cam_cc_cphy_rx_clk_src.clkr.hw,
1144 },
1145 .num_parents = 1,
1146 .flags = CLK_SET_RATE_PARENT,
1147 .ops = &clk_branch2_ops,
1148 },
1149 },
1150 };
1151
1152 static struct clk_branch cam_cc_csiphy2_clk = {
1153 .halt_reg = 0x9068,
1154 .halt_check = BRANCH_HALT,
1155 .clkr = {
1156 .enable_reg = 0x9068,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(const struct clk_init_data) {
1159 .name = "cam_cc_csiphy2_clk",
1160 .parent_hws = (const struct clk_hw*[]) {
1161 &cam_cc_cphy_rx_clk_src.clkr.hw,
1162 },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1166 },
1167 },
1168 };
1169
1170 static struct clk_branch cam_cc_icp_atb_clk = {
1171 .halt_reg = 0xf004,
1172 .halt_check = BRANCH_HALT,
1173 .clkr = {
1174 .enable_reg = 0xf004,
1175 .enable_mask = BIT(0),
1176 .hw.init = &(const struct clk_init_data) {
1177 .name = "cam_cc_icp_atb_clk",
1178 .ops = &clk_branch2_ops,
1179 },
1180 },
1181 };
1182
1183 static struct clk_branch cam_cc_icp_clk = {
1184 .halt_reg = 0xf02c,
1185 .halt_check = BRANCH_HALT,
1186 .clkr = {
1187 .enable_reg = 0xf02c,
1188 .enable_mask = BIT(0),
1189 .hw.init = &(const struct clk_init_data) {
1190 .name = "cam_cc_icp_clk",
1191 .parent_hws = (const struct clk_hw*[]) {
1192 &cam_cc_icp_clk_src.clkr.hw,
1193 },
1194 .num_parents = 1,
1195 .flags = CLK_SET_RATE_PARENT,
1196 .ops = &clk_branch2_ops,
1197 },
1198 },
1199 };
1200
1201 static struct clk_branch cam_cc_icp_cti_clk = {
1202 .halt_reg = 0xf008,
1203 .halt_check = BRANCH_HALT,
1204 .clkr = {
1205 .enable_reg = 0xf008,
1206 .enable_mask = BIT(0),
1207 .hw.init = &(const struct clk_init_data) {
1208 .name = "cam_cc_icp_cti_clk",
1209 .ops = &clk_branch2_ops,
1210 },
1211 },
1212 };
1213
1214 static struct clk_branch cam_cc_icp_ts_clk = {
1215 .halt_reg = 0xf00c,
1216 .halt_check = BRANCH_HALT,
1217 .clkr = {
1218 .enable_reg = 0xf00c,
1219 .enable_mask = BIT(0),
1220 .hw.init = &(const struct clk_init_data) {
1221 .name = "cam_cc_icp_ts_clk",
1222 .ops = &clk_branch2_ops,
1223 },
1224 },
1225 };
1226
1227 static struct clk_branch cam_cc_mclk0_clk = {
1228 .halt_reg = 0x801c,
1229 .halt_check = BRANCH_HALT,
1230 .clkr = {
1231 .enable_reg = 0x801c,
1232 .enable_mask = BIT(0),
1233 .hw.init = &(const struct clk_init_data) {
1234 .name = "cam_cc_mclk0_clk",
1235 .parent_hws = (const struct clk_hw*[]) {
1236 &cam_cc_mclk0_clk_src.clkr.hw,
1237 },
1238 .num_parents = 1,
1239 .flags = CLK_SET_RATE_PARENT,
1240 .ops = &clk_branch2_ops,
1241 },
1242 },
1243 };
1244
1245 static struct clk_branch cam_cc_mclk1_clk = {
1246 .halt_reg = 0x803c,
1247 .halt_check = BRANCH_HALT,
1248 .clkr = {
1249 .enable_reg = 0x803c,
1250 .enable_mask = BIT(0),
1251 .hw.init = &(const struct clk_init_data) {
1252 .name = "cam_cc_mclk1_clk",
1253 .parent_hws = (const struct clk_hw*[]) {
1254 &cam_cc_mclk1_clk_src.clkr.hw,
1255 },
1256 .num_parents = 1,
1257 .flags = CLK_SET_RATE_PARENT,
1258 .ops = &clk_branch2_ops,
1259 },
1260 },
1261 };
1262
1263 static struct clk_branch cam_cc_mclk2_clk = {
1264 .halt_reg = 0x805c,
1265 .halt_check = BRANCH_HALT,
1266 .clkr = {
1267 .enable_reg = 0x805c,
1268 .enable_mask = BIT(0),
1269 .hw.init = &(const struct clk_init_data) {
1270 .name = "cam_cc_mclk2_clk",
1271 .parent_hws = (const struct clk_hw*[]) {
1272 &cam_cc_mclk2_clk_src.clkr.hw,
1273 },
1274 .num_parents = 1,
1275 .flags = CLK_SET_RATE_PARENT,
1276 .ops = &clk_branch2_ops,
1277 },
1278 },
1279 };
1280
1281 static struct clk_branch cam_cc_mclk3_clk = {
1282 .halt_reg = 0x807c,
1283 .halt_check = BRANCH_HALT,
1284 .clkr = {
1285 .enable_reg = 0x807c,
1286 .enable_mask = BIT(0),
1287 .hw.init = &(const struct clk_init_data) {
1288 .name = "cam_cc_mclk3_clk",
1289 .parent_hws = (const struct clk_hw*[]) {
1290 &cam_cc_mclk3_clk_src.clkr.hw,
1291 },
1292 .num_parents = 1,
1293 .flags = CLK_SET_RATE_PARENT,
1294 .ops = &clk_branch2_ops,
1295 },
1296 },
1297 };
1298
1299 static struct clk_branch cam_cc_ope_0_ahb_clk = {
1300 .halt_reg = 0xb030,
1301 .halt_check = BRANCH_HALT,
1302 .clkr = {
1303 .enable_reg = 0xb030,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(const struct clk_init_data) {
1306 .name = "cam_cc_ope_0_ahb_clk",
1307 .parent_hws = (const struct clk_hw*[]) {
1308 &cam_cc_slow_ahb_clk_src.clkr.hw,
1309 },
1310 .num_parents = 1,
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1313 },
1314 },
1315 };
1316
1317 static struct clk_branch cam_cc_ope_0_areg_clk = {
1318 .halt_reg = 0xb02c,
1319 .halt_check = BRANCH_HALT,
1320 .clkr = {
1321 .enable_reg = 0xb02c,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(const struct clk_init_data) {
1324 .name = "cam_cc_ope_0_areg_clk",
1325 .parent_hws = (const struct clk_hw*[]) {
1326 &cam_cc_fast_ahb_clk_src.clkr.hw,
1327 },
1328 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1331 },
1332 },
1333 };
1334
1335 static struct clk_branch cam_cc_ope_0_clk = {
1336 .halt_reg = 0xb01c,
1337 .halt_check = BRANCH_HALT,
1338 .clkr = {
1339 .enable_reg = 0xb01c,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(const struct clk_init_data) {
1342 .name = "cam_cc_ope_0_clk",
1343 .parent_hws = (const struct clk_hw*[]) {
1344 &cam_cc_ope_0_clk_src.clkr.hw,
1345 },
1346 .num_parents = 1,
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1349 },
1350 },
1351 };
1352
1353 static struct clk_branch cam_cc_soc_ahb_clk = {
1354 .halt_reg = 0x14018,
1355 .halt_check = BRANCH_HALT,
1356 .clkr = {
1357 .enable_reg = 0x14018,
1358 .enable_mask = BIT(0),
1359 .hw.init = &(const struct clk_init_data) {
1360 .name = "cam_cc_soc_ahb_clk",
1361 .ops = &clk_branch2_ops,
1362 },
1363 },
1364 };
1365
1366 static struct clk_branch cam_cc_sys_tmr_clk = {
1367 .halt_reg = 0xf034,
1368 .halt_check = BRANCH_HALT,
1369 .clkr = {
1370 .enable_reg = 0xf034,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(const struct clk_init_data) {
1373 .name = "cam_cc_sys_tmr_clk",
1374 .ops = &clk_branch2_ops,
1375 },
1376 },
1377 };
1378
1379 static struct clk_branch cam_cc_tfe_0_ahb_clk = {
1380 .halt_reg = 0xc070,
1381 .halt_check = BRANCH_HALT,
1382 .clkr = {
1383 .enable_reg = 0xc070,
1384 .enable_mask = BIT(0),
1385 .hw.init = &(const struct clk_init_data) {
1386 .name = "cam_cc_tfe_0_ahb_clk",
1387 .parent_hws = (const struct clk_hw*[]) {
1388 &cam_cc_slow_ahb_clk_src.clkr.hw,
1389 },
1390 .num_parents = 1,
1391 .flags = CLK_SET_RATE_PARENT,
1392 .ops = &clk_branch2_ops,
1393 },
1394 },
1395 };
1396
1397 static struct clk_branch cam_cc_tfe_0_clk = {
1398 .halt_reg = 0xc01c,
1399 .halt_check = BRANCH_HALT,
1400 .clkr = {
1401 .enable_reg = 0xc01c,
1402 .enable_mask = BIT(0),
1403 .hw.init = &(const struct clk_init_data) {
1404 .name = "cam_cc_tfe_0_clk",
1405 .parent_hws = (const struct clk_hw*[]) {
1406 &cam_cc_tfe_0_clk_src.clkr.hw,
1407 },
1408 .num_parents = 1,
1409 .flags = CLK_SET_RATE_PARENT,
1410 .ops = &clk_branch2_ops,
1411 },
1412 },
1413 };
1414
1415 static struct clk_branch cam_cc_tfe_0_cphy_rx_clk = {
1416 .halt_reg = 0xc06c,
1417 .halt_check = BRANCH_HALT,
1418 .clkr = {
1419 .enable_reg = 0xc06c,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(const struct clk_init_data) {
1422 .name = "cam_cc_tfe_0_cphy_rx_clk",
1423 .parent_hws = (const struct clk_hw*[]) {
1424 &cam_cc_cphy_rx_clk_src.clkr.hw,
1425 },
1426 .num_parents = 1,
1427 .flags = CLK_SET_RATE_PARENT,
1428 .ops = &clk_branch2_ops,
1429 },
1430 },
1431 };
1432
1433 static struct clk_branch cam_cc_tfe_0_csid_clk = {
1434 .halt_reg = 0xc044,
1435 .halt_check = BRANCH_HALT,
1436 .clkr = {
1437 .enable_reg = 0xc044,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(const struct clk_init_data) {
1440 .name = "cam_cc_tfe_0_csid_clk",
1441 .parent_hws = (const struct clk_hw*[]) {
1442 &cam_cc_tfe_0_csid_clk_src.clkr.hw,
1443 },
1444 .num_parents = 1,
1445 .flags = CLK_SET_RATE_PARENT,
1446 .ops = &clk_branch2_ops,
1447 },
1448 },
1449 };
1450
1451 static struct clk_branch cam_cc_tfe_1_ahb_clk = {
1452 .halt_reg = 0xd048,
1453 .halt_check = BRANCH_HALT,
1454 .clkr = {
1455 .enable_reg = 0xd048,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(const struct clk_init_data) {
1458 .name = "cam_cc_tfe_1_ahb_clk",
1459 .parent_hws = (const struct clk_hw*[]) {
1460 &cam_cc_slow_ahb_clk_src.clkr.hw,
1461 },
1462 .num_parents = 1,
1463 .flags = CLK_SET_RATE_PARENT,
1464 .ops = &clk_branch2_ops,
1465 },
1466 },
1467 };
1468
1469 static struct clk_branch cam_cc_tfe_1_clk = {
1470 .halt_reg = 0xd01c,
1471 .halt_check = BRANCH_HALT,
1472 .clkr = {
1473 .enable_reg = 0xd01c,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(const struct clk_init_data) {
1476 .name = "cam_cc_tfe_1_clk",
1477 .parent_hws = (const struct clk_hw*[]) {
1478 &cam_cc_tfe_1_clk_src.clkr.hw,
1479 },
1480 .num_parents = 1,
1481 .flags = CLK_SET_RATE_PARENT,
1482 .ops = &clk_branch2_ops,
1483 },
1484 },
1485 };
1486
1487 static struct clk_branch cam_cc_tfe_1_cphy_rx_clk = {
1488 .halt_reg = 0xd044,
1489 .halt_check = BRANCH_HALT,
1490 .clkr = {
1491 .enable_reg = 0xd044,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(const struct clk_init_data) {
1494 .name = "cam_cc_tfe_1_cphy_rx_clk",
1495 .parent_hws = (const struct clk_hw*[]) {
1496 &cam_cc_cphy_rx_clk_src.clkr.hw,
1497 },
1498 .num_parents = 1,
1499 .flags = CLK_SET_RATE_PARENT,
1500 .ops = &clk_branch2_ops,
1501 },
1502 },
1503 };
1504
1505 static struct clk_branch cam_cc_tfe_1_csid_clk = {
1506 .halt_reg = 0xd03c,
1507 .halt_check = BRANCH_HALT,
1508 .clkr = {
1509 .enable_reg = 0xd03c,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(const struct clk_init_data) {
1512 .name = "cam_cc_tfe_1_csid_clk",
1513 .parent_hws = (const struct clk_hw*[]) {
1514 &cam_cc_tfe_1_csid_clk_src.clkr.hw,
1515 },
1516 .num_parents = 1,
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_branch2_ops,
1519 },
1520 },
1521 };
1522
1523 static struct gdsc cam_cc_camss_top_gdsc = {
1524 .gdscr = 0x14004,
1525 .en_rest_wait_val = 0x2,
1526 .en_few_wait_val = 0x2,
1527 .clk_dis_wait_val = 0xf,
1528 .pd = {
1529 .name = "cam_cc_camss_top_gdsc",
1530 },
1531 .pwrsts = PWRSTS_OFF_ON,
1532 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1533 };
1534
1535 static struct clk_regmap *cam_cc_sm4450_clocks[] = {
1536 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
1537 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
1538 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
1539 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
1540 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr,
1541 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1542 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
1543 [CAM_CC_CAMNOC_AXI_HF_CLK] = &cam_cc_camnoc_axi_hf_clk.clkr,
1544 [CAM_CC_CAMNOC_AXI_SF_CLK] = &cam_cc_camnoc_axi_sf_clk.clkr,
1545 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
1546 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
1547 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
1548 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
1549 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
1550 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1551 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1552 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
1553 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
1554 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
1555 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1556 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1557 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1558 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1559 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1560 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1561 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1562 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1563 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1564 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
1565 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr,
1566 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
1567 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
1568 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr,
1569 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr,
1570 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
1571 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
1572 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
1573 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
1574 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
1575 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
1576 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
1577 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
1578 [CAM_CC_OPE_0_AHB_CLK] = &cam_cc_ope_0_ahb_clk.clkr,
1579 [CAM_CC_OPE_0_AREG_CLK] = &cam_cc_ope_0_areg_clk.clkr,
1580 [CAM_CC_OPE_0_CLK] = &cam_cc_ope_0_clk.clkr,
1581 [CAM_CC_OPE_0_CLK_SRC] = &cam_cc_ope_0_clk_src.clkr,
1582 [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1583 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
1584 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
1585 [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
1586 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
1587 [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1588 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr,
1589 [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1590 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
1591 [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
1592 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
1593 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1594 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
1595 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
1596 [CAM_CC_TFE_0_AHB_CLK] = &cam_cc_tfe_0_ahb_clk.clkr,
1597 [CAM_CC_TFE_0_CLK] = &cam_cc_tfe_0_clk.clkr,
1598 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr,
1599 [CAM_CC_TFE_0_CPHY_RX_CLK] = &cam_cc_tfe_0_cphy_rx_clk.clkr,
1600 [CAM_CC_TFE_0_CSID_CLK] = &cam_cc_tfe_0_csid_clk.clkr,
1601 [CAM_CC_TFE_0_CSID_CLK_SRC] = &cam_cc_tfe_0_csid_clk_src.clkr,
1602 [CAM_CC_TFE_1_AHB_CLK] = &cam_cc_tfe_1_ahb_clk.clkr,
1603 [CAM_CC_TFE_1_CLK] = &cam_cc_tfe_1_clk.clkr,
1604 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr,
1605 [CAM_CC_TFE_1_CPHY_RX_CLK] = &cam_cc_tfe_1_cphy_rx_clk.clkr,
1606 [CAM_CC_TFE_1_CSID_CLK] = &cam_cc_tfe_1_csid_clk.clkr,
1607 [CAM_CC_TFE_1_CSID_CLK_SRC] = &cam_cc_tfe_1_csid_clk_src.clkr,
1608 };
1609
1610 static struct gdsc *cam_cc_sm4450_gdscs[] = {
1611 [CAM_CC_CAMSS_TOP_GDSC] = &cam_cc_camss_top_gdsc,
1612 };
1613
1614 static const struct qcom_reset_map cam_cc_sm4450_resets[] = {
1615 [CAM_CC_BPS_BCR] = { 0xa000 },
1616 [CAM_CC_CAMNOC_BCR] = { 0x13000 },
1617 [CAM_CC_CAMSS_TOP_BCR] = { 0x14000 },
1618 [CAM_CC_CCI_0_BCR] = { 0x10000 },
1619 [CAM_CC_CCI_1_BCR] = { 0x11000 },
1620 [CAM_CC_CPAS_BCR] = { 0x12000 },
1621 [CAM_CC_CRE_BCR] = { 0x16000 },
1622 [CAM_CC_CSI0PHY_BCR] = { 0x9000 },
1623 [CAM_CC_CSI1PHY_BCR] = { 0x9024 },
1624 [CAM_CC_CSI2PHY_BCR] = { 0x9048 },
1625 [CAM_CC_ICP_BCR] = { 0xf000 },
1626 [CAM_CC_MCLK0_BCR] = { 0x8000 },
1627 [CAM_CC_MCLK1_BCR] = { 0x8020 },
1628 [CAM_CC_MCLK2_BCR] = { 0x8040 },
1629 [CAM_CC_MCLK3_BCR] = { 0x8060 },
1630 [CAM_CC_OPE_0_BCR] = { 0xb000 },
1631 [CAM_CC_TFE_0_BCR] = { 0xc000 },
1632 [CAM_CC_TFE_1_BCR] = { 0xd000 },
1633 };
1634
1635 static const struct regmap_config cam_cc_sm4450_regmap_config = {
1636 .reg_bits = 32,
1637 .reg_stride = 4,
1638 .val_bits = 32,
1639 .max_register = 0x16024,
1640 .fast_io = true,
1641 };
1642
1643 static const struct qcom_cc_desc cam_cc_sm4450_desc = {
1644 .config = &cam_cc_sm4450_regmap_config,
1645 .clks = cam_cc_sm4450_clocks,
1646 .num_clks = ARRAY_SIZE(cam_cc_sm4450_clocks),
1647 .resets = cam_cc_sm4450_resets,
1648 .num_resets = ARRAY_SIZE(cam_cc_sm4450_resets),
1649 .gdscs = cam_cc_sm4450_gdscs,
1650 .num_gdscs = ARRAY_SIZE(cam_cc_sm4450_gdscs),
1651 };
1652
1653 static const struct of_device_id cam_cc_sm4450_match_table[] = {
1654 { .compatible = "qcom,sm4450-camcc" },
1655 { }
1656 };
1657 MODULE_DEVICE_TABLE(of, cam_cc_sm4450_match_table);
1658
cam_cc_sm4450_probe(struct platform_device * pdev)1659 static int cam_cc_sm4450_probe(struct platform_device *pdev)
1660 {
1661 struct regmap *regmap;
1662
1663 regmap = qcom_cc_map(pdev, &cam_cc_sm4450_desc);
1664 if (IS_ERR(regmap))
1665 return PTR_ERR(regmap);
1666
1667 clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
1668 clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
1669 clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
1670 clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
1671 clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
1672
1673 return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm4450_desc, regmap);
1674 }
1675
1676 static struct platform_driver cam_cc_sm4450_driver = {
1677 .probe = cam_cc_sm4450_probe,
1678 .driver = {
1679 .name = "camcc-sm4450",
1680 .of_match_table = cam_cc_sm4450_match_table,
1681 },
1682 };
1683
1684 module_platform_driver(cam_cc_sm4450_driver);
1685
1686 MODULE_DESCRIPTION("QTI CAMCC SM4450 Driver");
1687 MODULE_LICENSE("GPL");
1688