1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Register cache access API
4 //
5 // Copyright 2011 Wolfson Microelectronics plc
6 //
7 // Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8
9 #include <linux/bsearch.h>
10 #include <linux/device.h>
11 #include <linux/export.h>
12 #include <linux/slab.h>
13 #include <linux/sort.h>
14
15 #include "trace.h"
16 #include "internal.h"
17
18 static const struct regcache_ops *cache_types[] = {
19 ®cache_rbtree_ops,
20 ®cache_maple_ops,
21 ®cache_flat_ops,
22 };
23
regcache_defaults_cmp(const void * a,const void * b)24 static int regcache_defaults_cmp(const void *a, const void *b)
25 {
26 const struct reg_default *x = a;
27 const struct reg_default *y = b;
28
29 if (x->reg > y->reg)
30 return 1;
31 else if (x->reg < y->reg)
32 return -1;
33 else
34 return 0;
35 }
36
regcache_defaults_swap(void * a,void * b,int size)37 static void regcache_defaults_swap(void *a, void *b, int size)
38 {
39 struct reg_default *x = a;
40 struct reg_default *y = b;
41 struct reg_default tmp;
42
43 tmp = *x;
44 *x = *y;
45 *y = tmp;
46 }
47
regcache_sort_defaults(struct reg_default * defaults,unsigned int ndefaults)48 void regcache_sort_defaults(struct reg_default *defaults, unsigned int ndefaults)
49 {
50 sort(defaults, ndefaults, sizeof(*defaults),
51 regcache_defaults_cmp, regcache_defaults_swap);
52 }
53 EXPORT_SYMBOL_GPL(regcache_sort_defaults);
54
regcache_hw_init(struct regmap * map)55 static int regcache_hw_init(struct regmap *map)
56 {
57 int i, j;
58 int ret;
59 int count;
60 unsigned int reg, val;
61 void *tmp_buf;
62
63 if (!map->num_reg_defaults_raw)
64 return -EINVAL;
65
66 /* calculate the size of reg_defaults */
67 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
68 if (regmap_readable(map, i * map->reg_stride) &&
69 !regmap_volatile(map, i * map->reg_stride))
70 count++;
71
72 /* all registers are unreadable or volatile, so just bypass */
73 if (!count) {
74 map->cache_bypass = true;
75 return 0;
76 }
77
78 map->num_reg_defaults = count;
79 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
80 GFP_KERNEL);
81 if (!map->reg_defaults)
82 return -ENOMEM;
83
84 if (!map->reg_defaults_raw) {
85 bool cache_bypass = map->cache_bypass;
86 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
87
88 /* Bypass the cache access till data read from HW */
89 map->cache_bypass = true;
90 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
91 if (!tmp_buf) {
92 ret = -ENOMEM;
93 goto err_free;
94 }
95 ret = regmap_raw_read(map, 0, tmp_buf,
96 map->cache_size_raw);
97 map->cache_bypass = cache_bypass;
98 if (ret == 0) {
99 map->reg_defaults_raw = tmp_buf;
100 map->cache_free = true;
101 } else {
102 kfree(tmp_buf);
103 }
104 }
105
106 /* fill the reg_defaults */
107 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
108 reg = i * map->reg_stride;
109
110 if (!regmap_readable(map, reg))
111 continue;
112
113 if (regmap_volatile(map, reg))
114 continue;
115
116 if (map->reg_defaults_raw) {
117 val = regcache_get_val(map, map->reg_defaults_raw, i);
118 } else {
119 bool cache_bypass = map->cache_bypass;
120
121 map->cache_bypass = true;
122 ret = regmap_read(map, reg, &val);
123 map->cache_bypass = cache_bypass;
124 if (ret != 0) {
125 dev_err(map->dev, "Failed to read %d: %d\n",
126 reg, ret);
127 goto err_free;
128 }
129 }
130
131 map->reg_defaults[j].reg = reg;
132 map->reg_defaults[j].def = val;
133 j++;
134 }
135
136 return 0;
137
138 err_free:
139 kfree(map->reg_defaults);
140
141 return ret;
142 }
143
regcache_init(struct regmap * map,const struct regmap_config * config)144 int regcache_init(struct regmap *map, const struct regmap_config *config)
145 {
146 int ret;
147 int i;
148 void *tmp_buf;
149
150 if (map->cache_type == REGCACHE_NONE) {
151 if (config->reg_defaults || config->num_reg_defaults_raw)
152 dev_warn(map->dev,
153 "No cache used with register defaults set!\n");
154
155 map->cache_bypass = true;
156 return 0;
157 }
158
159 if (config->reg_defaults && !config->num_reg_defaults) {
160 dev_err(map->dev,
161 "Register defaults are set without the number!\n");
162 return -EINVAL;
163 }
164
165 if (config->num_reg_defaults && !config->reg_defaults) {
166 dev_err(map->dev,
167 "Register defaults number are set without the reg!\n");
168 return -EINVAL;
169 }
170
171 for (i = 0; i < config->num_reg_defaults; i++)
172 if (config->reg_defaults[i].reg % map->reg_stride)
173 return -EINVAL;
174
175 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
176 if (cache_types[i]->type == map->cache_type)
177 break;
178
179 if (i == ARRAY_SIZE(cache_types)) {
180 dev_err(map->dev, "Could not match cache type: %d\n",
181 map->cache_type);
182 return -EINVAL;
183 }
184
185 map->num_reg_defaults = config->num_reg_defaults;
186 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
187 map->reg_defaults_raw = config->reg_defaults_raw;
188 map->cache_word_size = BITS_TO_BYTES(config->val_bits);
189 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
190
191 map->cache = NULL;
192 map->cache_ops = cache_types[i];
193
194 if (!map->cache_ops->read ||
195 !map->cache_ops->write ||
196 !map->cache_ops->name)
197 return -EINVAL;
198
199 /* We still need to ensure that the reg_defaults
200 * won't vanish from under us. We'll need to make
201 * a copy of it.
202 */
203 if (config->reg_defaults) {
204 tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,
205 sizeof(*map->reg_defaults), GFP_KERNEL);
206 if (!tmp_buf)
207 return -ENOMEM;
208 map->reg_defaults = tmp_buf;
209 } else if (map->num_reg_defaults_raw) {
210 /* Some devices such as PMICs don't have cache defaults,
211 * we cope with this by reading back the HW registers and
212 * crafting the cache defaults by hand.
213 */
214 ret = regcache_hw_init(map);
215 if (ret < 0)
216 return ret;
217 if (map->cache_bypass)
218 return 0;
219 }
220
221 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
222 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
223 map->max_register_is_set = true;
224 }
225
226 if (map->cache_ops->init) {
227 dev_dbg(map->dev, "Initializing %s cache\n",
228 map->cache_ops->name);
229 map->lock(map->lock_arg);
230 ret = map->cache_ops->init(map);
231 map->unlock(map->lock_arg);
232 if (ret)
233 goto err_free;
234 }
235 return 0;
236
237 err_free:
238 kfree(map->reg_defaults);
239 if (map->cache_free)
240 kfree(map->reg_defaults_raw);
241
242 return ret;
243 }
244
regcache_exit(struct regmap * map)245 void regcache_exit(struct regmap *map)
246 {
247 if (map->cache_type == REGCACHE_NONE)
248 return;
249
250 BUG_ON(!map->cache_ops);
251
252 kfree(map->reg_defaults);
253 if (map->cache_free)
254 kfree(map->reg_defaults_raw);
255
256 if (map->cache_ops->exit) {
257 dev_dbg(map->dev, "Destroying %s cache\n",
258 map->cache_ops->name);
259 map->lock(map->lock_arg);
260 map->cache_ops->exit(map);
261 map->unlock(map->lock_arg);
262 }
263 }
264
265 /**
266 * regcache_read - Fetch the value of a given register from the cache.
267 *
268 * @map: map to configure.
269 * @reg: The register index.
270 * @value: The value to be returned.
271 *
272 * Return a negative value on failure, 0 on success.
273 */
regcache_read(struct regmap * map,unsigned int reg,unsigned int * value)274 int regcache_read(struct regmap *map,
275 unsigned int reg, unsigned int *value)
276 {
277 int ret;
278
279 if (map->cache_type == REGCACHE_NONE)
280 return -EINVAL;
281
282 BUG_ON(!map->cache_ops);
283
284 if (!regmap_volatile(map, reg)) {
285 ret = map->cache_ops->read(map, reg, value);
286
287 if (ret == 0)
288 trace_regmap_reg_read_cache(map, reg, *value);
289
290 return ret;
291 }
292
293 return -EINVAL;
294 }
295
296 /**
297 * regcache_write - Set the value of a given register in the cache.
298 *
299 * @map: map to configure.
300 * @reg: The register index.
301 * @value: The new register value.
302 *
303 * Return a negative value on failure, 0 on success.
304 */
regcache_write(struct regmap * map,unsigned int reg,unsigned int value)305 int regcache_write(struct regmap *map,
306 unsigned int reg, unsigned int value)
307 {
308 if (map->cache_type == REGCACHE_NONE)
309 return 0;
310
311 BUG_ON(!map->cache_ops);
312
313 if (!regmap_volatile(map, reg))
314 return map->cache_ops->write(map, reg, value);
315
316 return 0;
317 }
318
regcache_reg_needs_sync(struct regmap * map,unsigned int reg,unsigned int val)319 bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
320 unsigned int val)
321 {
322 int ret;
323
324 if (!regmap_writeable(map, reg))
325 return false;
326
327 /* If we don't know the chip just got reset, then sync everything. */
328 if (!map->no_sync_defaults)
329 return true;
330
331 /* Is this the hardware default? If so skip. */
332 ret = regcache_lookup_reg(map, reg);
333 if (ret >= 0 && val == map->reg_defaults[ret].def)
334 return false;
335 return true;
336 }
337
regcache_default_sync(struct regmap * map,unsigned int min,unsigned int max)338 static int regcache_default_sync(struct regmap *map, unsigned int min,
339 unsigned int max)
340 {
341 unsigned int reg;
342
343 for (reg = min; reg <= max; reg += map->reg_stride) {
344 unsigned int val;
345 int ret;
346
347 if (regmap_volatile(map, reg) ||
348 !regmap_writeable(map, reg))
349 continue;
350
351 ret = regcache_read(map, reg, &val);
352 if (ret == -ENOENT)
353 continue;
354 if (ret)
355 return ret;
356
357 if (!regcache_reg_needs_sync(map, reg, val))
358 continue;
359
360 map->cache_bypass = true;
361 ret = _regmap_write(map, reg, val);
362 map->cache_bypass = false;
363 if (ret) {
364 dev_err(map->dev, "Unable to sync register %#x. %d\n",
365 reg, ret);
366 return ret;
367 }
368 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
369 }
370
371 return 0;
372 }
373
rbtree_all(const void * key,const struct rb_node * node)374 static int rbtree_all(const void *key, const struct rb_node *node)
375 {
376 return 0;
377 }
378
379 /**
380 * regcache_sync - Sync the register cache with the hardware.
381 *
382 * @map: map to configure.
383 *
384 * Any registers that should not be synced should be marked as
385 * volatile. In general drivers can choose not to use the provided
386 * syncing functionality if they so require.
387 *
388 * Return a negative value on failure, 0 on success.
389 */
regcache_sync(struct regmap * map)390 int regcache_sync(struct regmap *map)
391 {
392 int ret = 0;
393 unsigned int i;
394 const char *name;
395 bool bypass;
396 struct rb_node *node;
397
398 if (WARN_ON(map->cache_type == REGCACHE_NONE))
399 return -EINVAL;
400
401 BUG_ON(!map->cache_ops);
402
403 map->lock(map->lock_arg);
404 /* Remember the initial bypass state */
405 bypass = map->cache_bypass;
406 dev_dbg(map->dev, "Syncing %s cache\n",
407 map->cache_ops->name);
408 name = map->cache_ops->name;
409 trace_regcache_sync(map, name, "start");
410
411 if (!map->cache_dirty)
412 goto out;
413
414 /* Apply any patch first */
415 map->cache_bypass = true;
416 for (i = 0; i < map->patch_regs; i++) {
417 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
418 if (ret != 0) {
419 dev_err(map->dev, "Failed to write %x = %x: %d\n",
420 map->patch[i].reg, map->patch[i].def, ret);
421 goto out;
422 }
423 }
424 map->cache_bypass = false;
425
426 if (map->cache_ops->sync)
427 ret = map->cache_ops->sync(map, 0, map->max_register);
428 else
429 ret = regcache_default_sync(map, 0, map->max_register);
430
431 if (ret == 0)
432 map->cache_dirty = false;
433
434 out:
435 /* Restore the bypass state */
436 map->cache_bypass = bypass;
437 map->no_sync_defaults = false;
438
439 /*
440 * If we did any paging with cache bypassed and a cached
441 * paging register then the register and cache state might
442 * have gone out of sync, force writes of all the paging
443 * registers.
444 */
445 rb_for_each(node, NULL, &map->range_tree, rbtree_all) {
446 struct regmap_range_node *this =
447 rb_entry(node, struct regmap_range_node, node);
448
449 /* If there's nothing in the cache there's nothing to sync */
450 if (regcache_read(map, this->selector_reg, &i) != 0)
451 continue;
452
453 ret = _regmap_write(map, this->selector_reg, i);
454 if (ret != 0) {
455 dev_err(map->dev, "Failed to write %x = %x: %d\n",
456 this->selector_reg, i, ret);
457 break;
458 }
459 }
460
461 map->unlock(map->lock_arg);
462
463 regmap_async_complete(map);
464
465 trace_regcache_sync(map, name, "stop");
466
467 return ret;
468 }
469 EXPORT_SYMBOL_GPL(regcache_sync);
470
471 /**
472 * regcache_sync_region - Sync part of the register cache with the hardware.
473 *
474 * @map: map to sync.
475 * @min: first register to sync
476 * @max: last register to sync
477 *
478 * Write all non-default register values in the specified region to
479 * the hardware.
480 *
481 * Return a negative value on failure, 0 on success.
482 */
regcache_sync_region(struct regmap * map,unsigned int min,unsigned int max)483 int regcache_sync_region(struct regmap *map, unsigned int min,
484 unsigned int max)
485 {
486 int ret = 0;
487 const char *name;
488 bool bypass;
489
490 if (WARN_ON(map->cache_type == REGCACHE_NONE))
491 return -EINVAL;
492
493 BUG_ON(!map->cache_ops);
494
495 map->lock(map->lock_arg);
496
497 /* Remember the initial bypass state */
498 bypass = map->cache_bypass;
499
500 name = map->cache_ops->name;
501 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
502
503 trace_regcache_sync(map, name, "start region");
504
505 if (!map->cache_dirty)
506 goto out;
507
508 map->async = true;
509
510 if (map->cache_ops->sync)
511 ret = map->cache_ops->sync(map, min, max);
512 else
513 ret = regcache_default_sync(map, min, max);
514
515 out:
516 /* Restore the bypass state */
517 map->cache_bypass = bypass;
518 map->async = false;
519 map->no_sync_defaults = false;
520 map->unlock(map->lock_arg);
521
522 regmap_async_complete(map);
523
524 trace_regcache_sync(map, name, "stop region");
525
526 return ret;
527 }
528 EXPORT_SYMBOL_GPL(regcache_sync_region);
529
530 /**
531 * regcache_drop_region - Discard part of the register cache
532 *
533 * @map: map to operate on
534 * @min: first register to discard
535 * @max: last register to discard
536 *
537 * Discard part of the register cache.
538 *
539 * Return a negative value on failure, 0 on success.
540 */
regcache_drop_region(struct regmap * map,unsigned int min,unsigned int max)541 int regcache_drop_region(struct regmap *map, unsigned int min,
542 unsigned int max)
543 {
544 int ret = 0;
545
546 if (!map->cache_ops || !map->cache_ops->drop)
547 return -EINVAL;
548
549 map->lock(map->lock_arg);
550
551 trace_regcache_drop_region(map, min, max);
552
553 ret = map->cache_ops->drop(map, min, max);
554
555 map->unlock(map->lock_arg);
556
557 return ret;
558 }
559 EXPORT_SYMBOL_GPL(regcache_drop_region);
560
561 /**
562 * regcache_cache_only - Put a register map into cache only mode
563 *
564 * @map: map to configure
565 * @enable: flag if changes should be written to the hardware
566 *
567 * When a register map is marked as cache only writes to the register
568 * map API will only update the register cache, they will not cause
569 * any hardware changes. This is useful for allowing portions of
570 * drivers to act as though the device were functioning as normal when
571 * it is disabled for power saving reasons.
572 */
regcache_cache_only(struct regmap * map,bool enable)573 void regcache_cache_only(struct regmap *map, bool enable)
574 {
575 map->lock(map->lock_arg);
576 WARN_ON(map->cache_type != REGCACHE_NONE &&
577 map->cache_bypass && enable);
578 map->cache_only = enable;
579 trace_regmap_cache_only(map, enable);
580 map->unlock(map->lock_arg);
581 }
582 EXPORT_SYMBOL_GPL(regcache_cache_only);
583
584 /**
585 * regcache_mark_dirty - Indicate that HW registers were reset to default values
586 *
587 * @map: map to mark
588 *
589 * Inform regcache that the device has been powered down or reset, so that
590 * on resume, regcache_sync() knows to write out all non-default values
591 * stored in the cache.
592 *
593 * If this function is not called, regcache_sync() will assume that
594 * the hardware state still matches the cache state, modulo any writes that
595 * happened when cache_only was true.
596 */
regcache_mark_dirty(struct regmap * map)597 void regcache_mark_dirty(struct regmap *map)
598 {
599 map->lock(map->lock_arg);
600 map->cache_dirty = true;
601 map->no_sync_defaults = true;
602 map->unlock(map->lock_arg);
603 }
604 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
605
606 /**
607 * regcache_cache_bypass - Put a register map into cache bypass mode
608 *
609 * @map: map to configure
610 * @enable: flag if changes should not be written to the cache
611 *
612 * When a register map is marked with the cache bypass option, writes
613 * to the register map API will only update the hardware and not
614 * the cache directly. This is useful when syncing the cache back to
615 * the hardware.
616 */
regcache_cache_bypass(struct regmap * map,bool enable)617 void regcache_cache_bypass(struct regmap *map, bool enable)
618 {
619 map->lock(map->lock_arg);
620 WARN_ON(map->cache_only && enable);
621 map->cache_bypass = enable;
622 trace_regmap_cache_bypass(map, enable);
623 map->unlock(map->lock_arg);
624 }
625 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
626
627 /**
628 * regcache_reg_cached - Check if a register is cached
629 *
630 * @map: map to check
631 * @reg: register to check
632 *
633 * Reports if a register is cached.
634 */
regcache_reg_cached(struct regmap * map,unsigned int reg)635 bool regcache_reg_cached(struct regmap *map, unsigned int reg)
636 {
637 unsigned int val;
638 int ret;
639
640 map->lock(map->lock_arg);
641
642 ret = regcache_read(map, reg, &val);
643
644 map->unlock(map->lock_arg);
645
646 return ret == 0;
647 }
648 EXPORT_SYMBOL_GPL(regcache_reg_cached);
649
regcache_set_val(struct regmap * map,void * base,unsigned int idx,unsigned int val)650 void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
651 unsigned int val)
652 {
653 /* Use device native format if possible */
654 if (map->format.format_val) {
655 map->format.format_val(base + (map->cache_word_size * idx),
656 val, 0);
657 return;
658 }
659
660 switch (map->cache_word_size) {
661 case 1: {
662 u8 *cache = base;
663
664 cache[idx] = val;
665 break;
666 }
667 case 2: {
668 u16 *cache = base;
669
670 cache[idx] = val;
671 break;
672 }
673 case 4: {
674 u32 *cache = base;
675
676 cache[idx] = val;
677 break;
678 }
679 default:
680 BUG();
681 }
682 }
683
regcache_get_val(struct regmap * map,const void * base,unsigned int idx)684 unsigned int regcache_get_val(struct regmap *map, const void *base,
685 unsigned int idx)
686 {
687 if (!base)
688 return -EINVAL;
689
690 /* Use device native format if possible */
691 if (map->format.parse_val)
692 return map->format.parse_val(regcache_get_val_addr(map, base,
693 idx));
694
695 switch (map->cache_word_size) {
696 case 1: {
697 const u8 *cache = base;
698
699 return cache[idx];
700 }
701 case 2: {
702 const u16 *cache = base;
703
704 return cache[idx];
705 }
706 case 4: {
707 const u32 *cache = base;
708
709 return cache[idx];
710 }
711 default:
712 BUG();
713 }
714 /* unreachable */
715 return -1;
716 }
717
regcache_default_cmp(const void * a,const void * b)718 static int regcache_default_cmp(const void *a, const void *b)
719 {
720 const struct reg_default *_a = a;
721 const struct reg_default *_b = b;
722
723 return _a->reg - _b->reg;
724 }
725
regcache_lookup_reg(struct regmap * map,unsigned int reg)726 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
727 {
728 struct reg_default key;
729 struct reg_default *r;
730
731 key.reg = reg;
732 key.def = 0;
733
734 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
735 sizeof(struct reg_default), regcache_default_cmp);
736
737 if (r)
738 return r - map->reg_defaults;
739 else
740 return -ENOENT;
741 }
742
regcache_reg_present(unsigned long * cache_present,unsigned int idx)743 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
744 {
745 if (!cache_present)
746 return true;
747
748 return test_bit(idx, cache_present);
749 }
750
regcache_sync_val(struct regmap * map,unsigned int reg,unsigned int val)751 int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
752 {
753 int ret;
754
755 if (!regcache_reg_needs_sync(map, reg, val))
756 return 0;
757
758 map->cache_bypass = true;
759
760 ret = _regmap_write(map, reg, val);
761
762 map->cache_bypass = false;
763
764 if (ret != 0) {
765 dev_err(map->dev, "Unable to sync register %#x. %d\n",
766 reg, ret);
767 return ret;
768 }
769 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
770 reg, val);
771
772 return 0;
773 }
774
regcache_sync_block_single(struct regmap * map,void * block,unsigned long * cache_present,unsigned int block_base,unsigned int start,unsigned int end)775 static int regcache_sync_block_single(struct regmap *map, void *block,
776 unsigned long *cache_present,
777 unsigned int block_base,
778 unsigned int start, unsigned int end)
779 {
780 unsigned int i, regtmp, val;
781 int ret;
782
783 for (i = start; i < end; i++) {
784 regtmp = block_base + (i * map->reg_stride);
785
786 if (!regcache_reg_present(cache_present, i) ||
787 !regmap_writeable(map, regtmp))
788 continue;
789
790 val = regcache_get_val(map, block, i);
791 ret = regcache_sync_val(map, regtmp, val);
792 if (ret != 0)
793 return ret;
794 }
795
796 return 0;
797 }
798
regcache_sync_block_raw_flush(struct regmap * map,const void ** data,unsigned int base,unsigned int cur)799 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
800 unsigned int base, unsigned int cur)
801 {
802 size_t val_bytes = map->format.val_bytes;
803 int ret, count;
804
805 if (*data == NULL)
806 return 0;
807
808 count = (cur - base) / map->reg_stride;
809
810 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
811 count * val_bytes, count, base, cur - map->reg_stride);
812
813 map->cache_bypass = true;
814
815 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
816 if (ret)
817 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
818 base, cur - map->reg_stride, ret);
819
820 map->cache_bypass = false;
821
822 *data = NULL;
823
824 return ret;
825 }
826
regcache_sync_block_raw(struct regmap * map,void * block,unsigned long * cache_present,unsigned int block_base,unsigned int start,unsigned int end)827 static int regcache_sync_block_raw(struct regmap *map, void *block,
828 unsigned long *cache_present,
829 unsigned int block_base, unsigned int start,
830 unsigned int end)
831 {
832 unsigned int i, val;
833 unsigned int regtmp = 0;
834 unsigned int base = 0;
835 const void *data = NULL;
836 int ret;
837
838 for (i = start; i < end; i++) {
839 regtmp = block_base + (i * map->reg_stride);
840
841 if (!regcache_reg_present(cache_present, i) ||
842 !regmap_writeable(map, regtmp)) {
843 ret = regcache_sync_block_raw_flush(map, &data,
844 base, regtmp);
845 if (ret != 0)
846 return ret;
847 continue;
848 }
849
850 val = regcache_get_val(map, block, i);
851 if (!regcache_reg_needs_sync(map, regtmp, val)) {
852 ret = regcache_sync_block_raw_flush(map, &data,
853 base, regtmp);
854 if (ret != 0)
855 return ret;
856 continue;
857 }
858
859 if (!data) {
860 data = regcache_get_val_addr(map, block, i);
861 base = regtmp;
862 }
863 }
864
865 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
866 map->reg_stride);
867 }
868
regcache_sync_block(struct regmap * map,void * block,unsigned long * cache_present,unsigned int block_base,unsigned int start,unsigned int end)869 int regcache_sync_block(struct regmap *map, void *block,
870 unsigned long *cache_present,
871 unsigned int block_base, unsigned int start,
872 unsigned int end)
873 {
874 if (regmap_can_raw_write(map) && !map->use_single_write)
875 return regcache_sync_block_raw(map, block, cache_present,
876 block_base, start, end);
877 else
878 return regcache_sync_block_single(map, block, cache_present,
879 block_base, start, end);
880 }
881