1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Core of Xen paravirt_ops implementation.
4  *
5  * This file contains the xen_paravirt_ops structure itself, and the
6  * implementations for:
7  * - privileged instructions
8  * - interrupt flags
9  * - segment operations
10  * - booting and setup
11  *
12  * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
13  */
14 
15 #include <linux/cpu.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/smp.h>
19 #include <linux/preempt.h>
20 #include <linux/hardirq.h>
21 #include <linux/percpu.h>
22 #include <linux/delay.h>
23 #include <linux/start_kernel.h>
24 #include <linux/sched.h>
25 #include <linux/kprobes.h>
26 #include <linux/kstrtox.h>
27 #include <linux/memblock.h>
28 #include <linux/export.h>
29 #include <linux/mm.h>
30 #include <linux/page-flags.h>
31 #include <linux/pci.h>
32 #include <linux/gfp.h>
33 #include <linux/edd.h>
34 #include <linux/reboot.h>
35 #include <linux/virtio_anchor.h>
36 #include <linux/stackprotector.h>
37 
38 #include <xen/xen.h>
39 #include <xen/events.h>
40 #include <xen/interface/xen.h>
41 #include <xen/interface/version.h>
42 #include <xen/interface/physdev.h>
43 #include <xen/interface/vcpu.h>
44 #include <xen/interface/memory.h>
45 #include <xen/interface/nmi.h>
46 #include <xen/interface/xen-mca.h>
47 #include <xen/features.h>
48 #include <xen/page.h>
49 #include <xen/hvc-console.h>
50 #include <xen/acpi.h>
51 
52 #include <asm/cpuid.h>
53 #include <asm/paravirt.h>
54 #include <asm/apic.h>
55 #include <asm/page.h>
56 #include <asm/xen/pci.h>
57 #include <asm/xen/hypercall.h>
58 #include <asm/xen/hypervisor.h>
59 #include <asm/xen/cpuid.h>
60 #include <asm/fixmap.h>
61 #include <asm/processor.h>
62 #include <asm/proto.h>
63 #include <asm/msr-index.h>
64 #include <asm/traps.h>
65 #include <asm/setup.h>
66 #include <asm/desc.h>
67 #include <asm/pgalloc.h>
68 #include <asm/tlbflush.h>
69 #include <asm/reboot.h>
70 #include <asm/hypervisor.h>
71 #include <asm/mach_traps.h>
72 #include <asm/mtrr.h>
73 #include <asm/mwait.h>
74 #include <asm/pci_x86.h>
75 #include <asm/cpu.h>
76 #include <asm/irq_stack.h>
77 #ifdef CONFIG_X86_IOPL_IOPERM
78 #include <asm/io_bitmap.h>
79 #endif
80 
81 #ifdef CONFIG_ACPI
82 #include <linux/acpi.h>
83 #include <asm/acpi.h>
84 #include <acpi/proc_cap_intel.h>
85 #include <acpi/processor.h>
86 #include <xen/interface/platform.h>
87 #endif
88 
89 #include "xen-ops.h"
90 
91 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */
92 
93 void *xen_initial_gdt;
94 
95 static int xen_cpu_up_prepare_pv(unsigned int cpu);
96 static int xen_cpu_dead_pv(unsigned int cpu);
97 
98 #ifndef CONFIG_PREEMPTION
99 /*
100  * Some hypercalls issued by the toolstack can take many 10s of
101  * seconds. Allow tasks running hypercalls via the privcmd driver to
102  * be voluntarily preempted even if full kernel preemption is
103  * disabled.
104  *
105  * Such preemptible hypercalls are bracketed by
106  * xen_preemptible_hcall_begin() and xen_preemptible_hcall_end()
107  * calls.
108  */
109 DEFINE_PER_CPU(bool, xen_in_preemptible_hcall);
110 EXPORT_SYMBOL_GPL(xen_in_preemptible_hcall);
111 
112 /*
113  * In case of scheduling the flag must be cleared and restored after
114  * returning from schedule as the task might move to a different CPU.
115  */
get_and_clear_inhcall(void)116 static __always_inline bool get_and_clear_inhcall(void)
117 {
118 	bool inhcall = __this_cpu_read(xen_in_preemptible_hcall);
119 
120 	__this_cpu_write(xen_in_preemptible_hcall, false);
121 	return inhcall;
122 }
123 
restore_inhcall(bool inhcall)124 static __always_inline void restore_inhcall(bool inhcall)
125 {
126 	__this_cpu_write(xen_in_preemptible_hcall, inhcall);
127 }
128 
129 #else
130 
get_and_clear_inhcall(void)131 static __always_inline bool get_and_clear_inhcall(void) { return false; }
restore_inhcall(bool inhcall)132 static __always_inline void restore_inhcall(bool inhcall) { }
133 
134 #endif
135 
136 struct tls_descs {
137 	struct desc_struct desc[3];
138 };
139 
140 DEFINE_PER_CPU(enum xen_lazy_mode, xen_lazy_mode) = XEN_LAZY_NONE;
141 
xen_get_lazy_mode(void)142 enum xen_lazy_mode xen_get_lazy_mode(void)
143 {
144 	if (in_interrupt())
145 		return XEN_LAZY_NONE;
146 
147 	return this_cpu_read(xen_lazy_mode);
148 }
149 
150 /*
151  * Updating the 3 TLS descriptors in the GDT on every task switch is
152  * surprisingly expensive so we avoid updating them if they haven't
153  * changed.  Since Xen writes different descriptors than the one
154  * passed in the update_descriptor hypercall we keep shadow copies to
155  * compare against.
156  */
157 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc);
158 
159 static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE);
160 
parse_xen_msr_safe(char * str)161 static int __init parse_xen_msr_safe(char *str)
162 {
163 	if (str)
164 		return kstrtobool(str, &xen_msr_safe);
165 	return -EINVAL;
166 }
167 early_param("xen_msr_safe", parse_xen_msr_safe);
168 
169 /* Get MTRR settings from Xen and put them into mtrr_state. */
xen_set_mtrr_data(void)170 static void __init xen_set_mtrr_data(void)
171 {
172 #ifdef CONFIG_MTRR
173 	struct xen_platform_op op = {
174 		.cmd = XENPF_read_memtype,
175 		.interface_version = XENPF_INTERFACE_VERSION,
176 	};
177 	unsigned int reg;
178 	unsigned long mask;
179 	uint32_t eax, width;
180 	static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata;
181 
182 	/* Get physical address width (only 64-bit cpus supported). */
183 	width = 36;
184 	eax = cpuid_eax(0x80000000);
185 	if ((eax >> 16) == 0x8000 && eax >= 0x80000008) {
186 		eax = cpuid_eax(0x80000008);
187 		width = eax & 0xff;
188 	}
189 
190 	for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) {
191 		op.u.read_memtype.reg = reg;
192 		if (HYPERVISOR_platform_op(&op))
193 			break;
194 
195 		/*
196 		 * Only called in dom0, which has all RAM PFNs mapped at
197 		 * RAM MFNs, and all PCI space etc. is identity mapped.
198 		 * This means we can treat MFN == PFN regarding MTRR settings.
199 		 */
200 		var[reg].base_lo = op.u.read_memtype.type;
201 		var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT;
202 		var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT);
203 		mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1);
204 		mask &= (1UL << width) - 1;
205 		if (mask)
206 			mask |= MTRR_PHYSMASK_V;
207 		var[reg].mask_lo = mask;
208 		var[reg].mask_hi = mask >> 32;
209 	}
210 
211 	/* Only overwrite MTRR state if any MTRR could be got from Xen. */
212 	if (reg)
213 		guest_force_mtrr_state(var, reg, MTRR_TYPE_UNCACHABLE);
214 #endif
215 }
216 
xen_pv_init_platform(void)217 static void __init xen_pv_init_platform(void)
218 {
219 	/* PV guests can't operate virtio devices without grants. */
220 	if (IS_ENABLED(CONFIG_XEN_VIRTIO))
221 		virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc);
222 
223 	populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP));
224 
225 	set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info);
226 	HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
227 
228 	/* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */
229 	xen_vcpu_info_reset(0);
230 
231 	/* pvclock is in shared info area */
232 	xen_init_time_ops();
233 
234 	if (xen_initial_domain())
235 		xen_set_mtrr_data();
236 	else
237 		guest_force_mtrr_state(NULL, 0, MTRR_TYPE_WRBACK);
238 
239 	/* Adjust nr_cpu_ids before "enumeration" happens */
240 	xen_smp_count_cpus();
241 }
242 
xen_pv_guest_late_init(void)243 static void __init xen_pv_guest_late_init(void)
244 {
245 #ifndef CONFIG_SMP
246 	/* Setup shared vcpu info for non-smp configurations */
247 	xen_setup_vcpu_info_placement();
248 #endif
249 }
250 
251 static __read_mostly unsigned int cpuid_leaf5_ecx_val;
252 static __read_mostly unsigned int cpuid_leaf5_edx_val;
253 
xen_cpuid(unsigned int * ax,unsigned int * bx,unsigned int * cx,unsigned int * dx)254 static void xen_cpuid(unsigned int *ax, unsigned int *bx,
255 		      unsigned int *cx, unsigned int *dx)
256 {
257 	unsigned int maskebx = ~0;
258 	unsigned int or_ebx = 0;
259 
260 	/*
261 	 * Mask out inconvenient features, to try and disable as many
262 	 * unsupported kernel subsystems as possible.
263 	 */
264 	switch (*ax) {
265 	case 0x1:
266 		/* Replace initial APIC ID in bits 24-31 of EBX. */
267 		/* See xen_pv_smp_config() for related topology preparations. */
268 		maskebx = 0x00ffffff;
269 		or_ebx = smp_processor_id() << 24;
270 		break;
271 
272 	case CPUID_LEAF_MWAIT:
273 		/* Synthesize the values.. */
274 		*ax = 0;
275 		*bx = 0;
276 		*cx = cpuid_leaf5_ecx_val;
277 		*dx = cpuid_leaf5_edx_val;
278 		return;
279 
280 	case 0xb:
281 		/* Suppress extended topology stuff */
282 		maskebx = 0;
283 		break;
284 	}
285 
286 	asm(XEN_EMULATE_PREFIX "cpuid"
287 		: "=a" (*ax),
288 		  "=b" (*bx),
289 		  "=c" (*cx),
290 		  "=d" (*dx)
291 		: "0" (*ax), "2" (*cx));
292 
293 	*bx &= maskebx;
294 	*bx |= or_ebx;
295 }
296 
xen_check_mwait(void)297 static bool __init xen_check_mwait(void)
298 {
299 #ifdef CONFIG_ACPI
300 	struct xen_platform_op op = {
301 		.cmd			= XENPF_set_processor_pminfo,
302 		.u.set_pminfo.id	= -1,
303 		.u.set_pminfo.type	= XEN_PM_PDC,
304 	};
305 	uint32_t buf[3];
306 	unsigned int ax, bx, cx, dx;
307 	unsigned int mwait_mask;
308 
309 	/* We need to determine whether it is OK to expose the MWAIT
310 	 * capability to the kernel to harvest deeper than C3 states from ACPI
311 	 * _CST using the processor_harvest_xen.c module. For this to work, we
312 	 * need to gather the MWAIT_LEAF values (which the cstate.c code
313 	 * checks against). The hypervisor won't expose the MWAIT flag because
314 	 * it would break backwards compatibility; so we will find out directly
315 	 * from the hardware and hypercall.
316 	 */
317 	if (!xen_initial_domain())
318 		return false;
319 
320 	/*
321 	 * When running under platform earlier than Xen4.2, do not expose
322 	 * mwait, to avoid the risk of loading native acpi pad driver
323 	 */
324 	if (!xen_running_on_version_or_later(4, 2))
325 		return false;
326 
327 	ax = 1;
328 	cx = 0;
329 
330 	native_cpuid(&ax, &bx, &cx, &dx);
331 
332 	mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
333 		     (1 << (X86_FEATURE_MWAIT % 32));
334 
335 	if ((cx & mwait_mask) != mwait_mask)
336 		return false;
337 
338 	/* We need to emulate the MWAIT_LEAF and for that we need both
339 	 * ecx and edx. The hypercall provides only partial information.
340 	 */
341 
342 	ax = CPUID_LEAF_MWAIT;
343 	bx = 0;
344 	cx = 0;
345 	dx = 0;
346 
347 	native_cpuid(&ax, &bx, &cx, &dx);
348 
349 	/* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so,
350 	 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3.
351 	 */
352 	buf[0] = ACPI_PDC_REVISION_ID;
353 	buf[1] = 1;
354 	buf[2] = (ACPI_PROC_CAP_C_CAPABILITY_SMP | ACPI_PROC_CAP_EST_CAPABILITY_SWSMP);
355 
356 	set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
357 
358 	if ((HYPERVISOR_platform_op(&op) == 0) &&
359 	    (buf[2] & (ACPI_PROC_CAP_C_C1_FFH | ACPI_PROC_CAP_C_C2C3_FFH))) {
360 		cpuid_leaf5_ecx_val = cx;
361 		cpuid_leaf5_edx_val = dx;
362 	}
363 	return true;
364 #else
365 	return false;
366 #endif
367 }
368 
xen_check_xsave(void)369 static bool __init xen_check_xsave(void)
370 {
371 	unsigned int cx, xsave_mask;
372 
373 	cx = cpuid_ecx(1);
374 
375 	xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) |
376 		     (1 << (X86_FEATURE_OSXSAVE % 32));
377 
378 	/* Xen will set CR4.OSXSAVE if supported and not disabled by force */
379 	return (cx & xsave_mask) == xsave_mask;
380 }
381 
xen_init_capabilities(void)382 static void __init xen_init_capabilities(void)
383 {
384 	setup_force_cpu_cap(X86_FEATURE_XENPV);
385 	setup_clear_cpu_cap(X86_FEATURE_DCA);
386 	setup_clear_cpu_cap(X86_FEATURE_APERFMPERF);
387 	setup_clear_cpu_cap(X86_FEATURE_MTRR);
388 	setup_clear_cpu_cap(X86_FEATURE_ACC);
389 	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
390 	setup_clear_cpu_cap(X86_FEATURE_SME);
391 	setup_clear_cpu_cap(X86_FEATURE_LKGS);
392 
393 	/*
394 	 * Xen PV would need some work to support PCID: CR3 handling as well
395 	 * as xen_flush_tlb_others() would need updating.
396 	 */
397 	setup_clear_cpu_cap(X86_FEATURE_PCID);
398 
399 	if (!xen_initial_domain())
400 		setup_clear_cpu_cap(X86_FEATURE_ACPI);
401 
402 	if (xen_check_mwait())
403 		setup_force_cpu_cap(X86_FEATURE_MWAIT);
404 	else
405 		setup_clear_cpu_cap(X86_FEATURE_MWAIT);
406 
407 	if (!xen_check_xsave()) {
408 		setup_clear_cpu_cap(X86_FEATURE_XSAVE);
409 		setup_clear_cpu_cap(X86_FEATURE_OSXSAVE);
410 	}
411 }
412 
xen_set_debugreg(int reg,unsigned long val)413 static noinstr void xen_set_debugreg(int reg, unsigned long val)
414 {
415 	HYPERVISOR_set_debugreg(reg, val);
416 }
417 
xen_get_debugreg(int reg)418 static noinstr unsigned long xen_get_debugreg(int reg)
419 {
420 	return HYPERVISOR_get_debugreg(reg);
421 }
422 
xen_start_context_switch(struct task_struct * prev)423 static void xen_start_context_switch(struct task_struct *prev)
424 {
425 	BUG_ON(preemptible());
426 
427 	if (this_cpu_read(xen_lazy_mode) == XEN_LAZY_MMU) {
428 		arch_leave_lazy_mmu_mode();
429 		set_ti_thread_flag(task_thread_info(prev), TIF_LAZY_MMU_UPDATES);
430 	}
431 	enter_lazy(XEN_LAZY_CPU);
432 }
433 
xen_end_context_switch(struct task_struct * next)434 static void xen_end_context_switch(struct task_struct *next)
435 {
436 	BUG_ON(preemptible());
437 
438 	xen_mc_flush();
439 	leave_lazy(XEN_LAZY_CPU);
440 	if (test_and_clear_ti_thread_flag(task_thread_info(next), TIF_LAZY_MMU_UPDATES))
441 		arch_enter_lazy_mmu_mode();
442 }
443 
xen_store_tr(void)444 static unsigned long xen_store_tr(void)
445 {
446 	return 0;
447 }
448 
449 /*
450  * Set the page permissions for a particular virtual address.  If the
451  * address is a vmalloc mapping (or other non-linear mapping), then
452  * find the linear mapping of the page and also set its protections to
453  * match.
454  */
set_aliased_prot(void * v,pgprot_t prot)455 static void set_aliased_prot(void *v, pgprot_t prot)
456 {
457 	int level;
458 	pte_t *ptep;
459 	pte_t pte;
460 	unsigned long pfn;
461 	unsigned char dummy;
462 	void *va;
463 
464 	ptep = lookup_address((unsigned long)v, &level);
465 	BUG_ON(ptep == NULL);
466 
467 	pfn = pte_pfn(*ptep);
468 	pte = pfn_pte(pfn, prot);
469 
470 	/*
471 	 * Careful: update_va_mapping() will fail if the virtual address
472 	 * we're poking isn't populated in the page tables.  We don't
473 	 * need to worry about the direct map (that's always in the page
474 	 * tables), but we need to be careful about vmap space.  In
475 	 * particular, the top level page table can lazily propagate
476 	 * entries between processes, so if we've switched mms since we
477 	 * vmapped the target in the first place, we might not have the
478 	 * top-level page table entry populated.
479 	 *
480 	 * We disable preemption because we want the same mm active when
481 	 * we probe the target and when we issue the hypercall.  We'll
482 	 * have the same nominal mm, but if we're a kernel thread, lazy
483 	 * mm dropping could change our pgd.
484 	 *
485 	 * Out of an abundance of caution, this uses __get_user() to fault
486 	 * in the target address just in case there's some obscure case
487 	 * in which the target address isn't readable.
488 	 */
489 
490 	preempt_disable();
491 
492 	copy_from_kernel_nofault(&dummy, v, 1);
493 
494 	if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
495 		BUG();
496 
497 	va = __va(PFN_PHYS(pfn));
498 
499 	if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
500 		BUG();
501 
502 	preempt_enable();
503 }
504 
xen_alloc_ldt(struct desc_struct * ldt,unsigned entries)505 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)
506 {
507 	const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
508 	int i;
509 
510 	/*
511 	 * We need to mark the all aliases of the LDT pages RO.  We
512 	 * don't need to call vm_flush_aliases(), though, since that's
513 	 * only responsible for flushing aliases out the TLBs, not the
514 	 * page tables, and Xen will flush the TLB for us if needed.
515 	 *
516 	 * To avoid confusing future readers: none of this is necessary
517 	 * to load the LDT.  The hypervisor only checks this when the
518 	 * LDT is faulted in due to subsequent descriptor access.
519 	 */
520 
521 	for (i = 0; i < entries; i += entries_per_page)
522 		set_aliased_prot(ldt + i, PAGE_KERNEL_RO);
523 }
524 
xen_free_ldt(struct desc_struct * ldt,unsigned entries)525 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries)
526 {
527 	const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
528 	int i;
529 
530 	for (i = 0; i < entries; i += entries_per_page)
531 		set_aliased_prot(ldt + i, PAGE_KERNEL);
532 }
533 
xen_set_ldt(const void * addr,unsigned entries)534 static void xen_set_ldt(const void *addr, unsigned entries)
535 {
536 	struct mmuext_op *op;
537 	struct multicall_space mcs = xen_mc_entry(sizeof(*op));
538 
539 	trace_xen_cpu_set_ldt(addr, entries);
540 
541 	op = mcs.args;
542 	op->cmd = MMUEXT_SET_LDT;
543 	op->arg1.linear_addr = (unsigned long)addr;
544 	op->arg2.nr_ents = entries;
545 
546 	MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
547 
548 	xen_mc_issue(XEN_LAZY_CPU);
549 }
550 
xen_load_gdt(const struct desc_ptr * dtr)551 static void xen_load_gdt(const struct desc_ptr *dtr)
552 {
553 	unsigned long va = dtr->address;
554 	unsigned int size = dtr->size + 1;
555 	unsigned long pfn, mfn;
556 	int level;
557 	pte_t *ptep;
558 	void *virt;
559 
560 	/* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */
561 	BUG_ON(size > PAGE_SIZE);
562 	BUG_ON(va & ~PAGE_MASK);
563 
564 	/*
565 	 * The GDT is per-cpu and is in the percpu data area.
566 	 * That can be virtually mapped, so we need to do a
567 	 * page-walk to get the underlying MFN for the
568 	 * hypercall.  The page can also be in the kernel's
569 	 * linear range, so we need to RO that mapping too.
570 	 */
571 	ptep = lookup_address(va, &level);
572 	BUG_ON(ptep == NULL);
573 
574 	pfn = pte_pfn(*ptep);
575 	mfn = pfn_to_mfn(pfn);
576 	virt = __va(PFN_PHYS(pfn));
577 
578 	make_lowmem_page_readonly((void *)va);
579 	make_lowmem_page_readonly(virt);
580 
581 	if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
582 		BUG();
583 }
584 
585 /*
586  * load_gdt for early boot, when the gdt is only mapped once
587  */
xen_load_gdt_boot(const struct desc_ptr * dtr)588 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
589 {
590 	unsigned long va = dtr->address;
591 	unsigned int size = dtr->size + 1;
592 	unsigned long pfn, mfn;
593 	pte_t pte;
594 
595 	/* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */
596 	BUG_ON(size > PAGE_SIZE);
597 	BUG_ON(va & ~PAGE_MASK);
598 
599 	pfn = virt_to_pfn((void *)va);
600 	mfn = pfn_to_mfn(pfn);
601 
602 	pte = pfn_pte(pfn, PAGE_KERNEL_RO);
603 
604 	if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
605 		BUG();
606 
607 	if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
608 		BUG();
609 }
610 
desc_equal(const struct desc_struct * d1,const struct desc_struct * d2)611 static inline bool desc_equal(const struct desc_struct *d1,
612 			      const struct desc_struct *d2)
613 {
614 	return !memcmp(d1, d2, sizeof(*d1));
615 }
616 
load_TLS_descriptor(struct thread_struct * t,unsigned int cpu,unsigned int i)617 static void load_TLS_descriptor(struct thread_struct *t,
618 				unsigned int cpu, unsigned int i)
619 {
620 	struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
621 	struct desc_struct *gdt;
622 	xmaddr_t maddr;
623 	struct multicall_space mc;
624 
625 	if (desc_equal(shadow, &t->tls_array[i]))
626 		return;
627 
628 	*shadow = t->tls_array[i];
629 
630 	gdt = get_cpu_gdt_rw(cpu);
631 	maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
632 	mc = __xen_mc_entry(0);
633 
634 	MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
635 }
636 
xen_load_tls(struct thread_struct * t,unsigned int cpu)637 static void xen_load_tls(struct thread_struct *t, unsigned int cpu)
638 {
639 	/*
640 	 * In lazy mode we need to zero %fs, otherwise we may get an
641 	 * exception between the new %fs descriptor being loaded and
642 	 * %fs being effectively cleared at __switch_to().
643 	 */
644 	if (xen_get_lazy_mode() == XEN_LAZY_CPU)
645 		loadsegment(fs, 0);
646 
647 	xen_mc_batch();
648 
649 	load_TLS_descriptor(t, cpu, 0);
650 	load_TLS_descriptor(t, cpu, 1);
651 	load_TLS_descriptor(t, cpu, 2);
652 
653 	xen_mc_issue(XEN_LAZY_CPU);
654 }
655 
xen_load_gs_index(unsigned int idx)656 static void xen_load_gs_index(unsigned int idx)
657 {
658 	if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx))
659 		BUG();
660 }
661 
xen_write_ldt_entry(struct desc_struct * dt,int entrynum,const void * ptr)662 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum,
663 				const void *ptr)
664 {
665 	xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]);
666 	u64 entry = *(u64 *)ptr;
667 
668 	trace_xen_cpu_write_ldt_entry(dt, entrynum, entry);
669 
670 	preempt_disable();
671 
672 	xen_mc_flush();
673 	if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry))
674 		BUG();
675 
676 	preempt_enable();
677 }
678 
679 void noist_exc_debug(struct pt_regs *regs);
680 
DEFINE_IDTENTRY_RAW(xenpv_exc_nmi)681 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi)
682 {
683 	/* On Xen PV, NMI doesn't use IST.  The C part is the same as native. */
684 	exc_nmi(regs);
685 }
686 
DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault)687 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault)
688 {
689 	/* On Xen PV, DF doesn't use IST.  The C part is the same as native. */
690 	exc_double_fault(regs, error_code);
691 }
692 
DEFINE_IDTENTRY_RAW(xenpv_exc_debug)693 DEFINE_IDTENTRY_RAW(xenpv_exc_debug)
694 {
695 	/*
696 	 * There's no IST on Xen PV, but we still need to dispatch
697 	 * to the correct handler.
698 	 */
699 	if (user_mode(regs))
700 		noist_exc_debug(regs);
701 	else
702 		exc_debug(regs);
703 }
704 
DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap)705 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap)
706 {
707 	/* This should never happen and there is no way to handle it. */
708 	instrumentation_begin();
709 	pr_err("Unknown trap in Xen PV mode.");
710 	BUG();
711 	instrumentation_end();
712 }
713 
714 #ifdef CONFIG_X86_MCE
DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check)715 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check)
716 {
717 	/*
718 	 * There's no IST on Xen PV, but we still need to dispatch
719 	 * to the correct handler.
720 	 */
721 	if (user_mode(regs))
722 		noist_exc_machine_check(regs);
723 	else
724 		exc_machine_check(regs);
725 }
726 #endif
727 
__xen_pv_evtchn_do_upcall(struct pt_regs * regs)728 static void __xen_pv_evtchn_do_upcall(struct pt_regs *regs)
729 {
730 	struct pt_regs *old_regs = set_irq_regs(regs);
731 
732 	inc_irq_stat(irq_hv_callback_count);
733 
734 	xen_evtchn_do_upcall();
735 
736 	set_irq_regs(old_regs);
737 }
738 
xen_pv_evtchn_do_upcall(struct pt_regs * regs)739 __visible noinstr void xen_pv_evtchn_do_upcall(struct pt_regs *regs)
740 {
741 	irqentry_state_t state = irqentry_enter(regs);
742 	bool inhcall;
743 
744 	instrumentation_begin();
745 	run_sysvec_on_irqstack_cond(__xen_pv_evtchn_do_upcall, regs);
746 
747 	inhcall = get_and_clear_inhcall();
748 	if (inhcall && !WARN_ON_ONCE(state.exit_rcu)) {
749 		irqentry_exit_cond_resched();
750 		instrumentation_end();
751 		restore_inhcall(inhcall);
752 	} else {
753 		instrumentation_end();
754 		irqentry_exit(regs, state);
755 	}
756 }
757 
758 struct trap_array_entry {
759 	void (*orig)(void);
760 	void (*xen)(void);
761 	bool ist_okay;
762 };
763 
764 #define TRAP_ENTRY(func, ist_ok) {			\
765 	.orig		= asm_##func,			\
766 	.xen		= xen_asm_##func,		\
767 	.ist_okay	= ist_ok }
768 
769 #define TRAP_ENTRY_REDIR(func, ist_ok) {		\
770 	.orig		= asm_##func,			\
771 	.xen		= xen_asm_xenpv_##func,		\
772 	.ist_okay	= ist_ok }
773 
774 static struct trap_array_entry trap_array[] = {
775 	TRAP_ENTRY_REDIR(exc_debug,			true  ),
776 	TRAP_ENTRY_REDIR(exc_double_fault,		true  ),
777 #ifdef CONFIG_X86_MCE
778 	TRAP_ENTRY_REDIR(exc_machine_check,		true  ),
779 #endif
780 	TRAP_ENTRY_REDIR(exc_nmi,			true  ),
781 	TRAP_ENTRY(exc_int3,				false ),
782 	TRAP_ENTRY(exc_overflow,			false ),
783 #ifdef CONFIG_IA32_EMULATION
784 	TRAP_ENTRY(int80_emulation,			false ),
785 #endif
786 	TRAP_ENTRY(exc_page_fault,			false ),
787 	TRAP_ENTRY(exc_divide_error,			false ),
788 	TRAP_ENTRY(exc_bounds,				false ),
789 	TRAP_ENTRY(exc_invalid_op,			false ),
790 	TRAP_ENTRY(exc_device_not_available,		false ),
791 	TRAP_ENTRY(exc_coproc_segment_overrun,		false ),
792 	TRAP_ENTRY(exc_invalid_tss,			false ),
793 	TRAP_ENTRY(exc_segment_not_present,		false ),
794 	TRAP_ENTRY(exc_stack_segment,			false ),
795 	TRAP_ENTRY(exc_general_protection,		false ),
796 	TRAP_ENTRY(exc_spurious_interrupt_bug,		false ),
797 	TRAP_ENTRY(exc_coprocessor_error,		false ),
798 	TRAP_ENTRY(exc_alignment_check,			false ),
799 	TRAP_ENTRY(exc_simd_coprocessor_error,		false ),
800 #ifdef CONFIG_X86_CET
801 	TRAP_ENTRY(exc_control_protection,		false ),
802 #endif
803 };
804 
get_trap_addr(void ** addr,unsigned int ist)805 static bool __ref get_trap_addr(void **addr, unsigned int ist)
806 {
807 	unsigned int nr;
808 	bool ist_okay = false;
809 	bool found = false;
810 
811 	/*
812 	 * Replace trap handler addresses by Xen specific ones.
813 	 * Check for known traps using IST and whitelist them.
814 	 * The debugger ones are the only ones we care about.
815 	 * Xen will handle faults like double_fault, so we should never see
816 	 * them.  Warn if there's an unexpected IST-using fault handler.
817 	 */
818 	for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) {
819 		struct trap_array_entry *entry = trap_array + nr;
820 
821 		if (*addr == entry->orig) {
822 			*addr = entry->xen;
823 			ist_okay = entry->ist_okay;
824 			found = true;
825 			break;
826 		}
827 	}
828 
829 	if (nr == ARRAY_SIZE(trap_array) &&
830 	    *addr >= (void *)early_idt_handler_array[0] &&
831 	    *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) {
832 		nr = (*addr - (void *)early_idt_handler_array[0]) /
833 		     EARLY_IDT_HANDLER_SIZE;
834 		*addr = (void *)xen_early_idt_handler_array[nr];
835 		found = true;
836 	}
837 
838 	if (!found)
839 		*addr = (void *)xen_asm_exc_xen_unknown_trap;
840 
841 	if (WARN_ON(found && ist != 0 && !ist_okay))
842 		return false;
843 
844 	return true;
845 }
846 
cvt_gate_to_trap(int vector,const gate_desc * val,struct trap_info * info)847 static int cvt_gate_to_trap(int vector, const gate_desc *val,
848 			    struct trap_info *info)
849 {
850 	unsigned long addr;
851 
852 	if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT)
853 		return 0;
854 
855 	info->vector = vector;
856 
857 	addr = gate_offset(val);
858 	if (!get_trap_addr((void **)&addr, val->bits.ist))
859 		return 0;
860 	info->address = addr;
861 
862 	info->cs = gate_segment(val);
863 	info->flags = val->bits.dpl;
864 	/* interrupt gates clear IF */
865 	if (val->bits.type == GATE_INTERRUPT)
866 		info->flags |= 1 << 2;
867 
868 	return 1;
869 }
870 
871 /* Locations of each CPU's IDT */
872 static DEFINE_PER_CPU(struct desc_ptr, idt_desc);
873 
874 /* Set an IDT entry.  If the entry is part of the current IDT, then
875    also update Xen. */
xen_write_idt_entry(gate_desc * dt,int entrynum,const gate_desc * g)876 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
877 {
878 	unsigned long p = (unsigned long)&dt[entrynum];
879 	unsigned long start, end;
880 
881 	trace_xen_cpu_write_idt_entry(dt, entrynum, g);
882 
883 	preempt_disable();
884 
885 	start = __this_cpu_read(idt_desc.address);
886 	end = start + __this_cpu_read(idt_desc.size) + 1;
887 
888 	xen_mc_flush();
889 
890 	native_write_idt_entry(dt, entrynum, g);
891 
892 	if (p >= start && (p + 8) <= end) {
893 		struct trap_info info[2];
894 
895 		info[1].address = 0;
896 
897 		if (cvt_gate_to_trap(entrynum, g, &info[0]))
898 			if (HYPERVISOR_set_trap_table(info))
899 				BUG();
900 	}
901 
902 	preempt_enable();
903 }
904 
xen_convert_trap_info(const struct desc_ptr * desc,struct trap_info * traps,bool full)905 static unsigned xen_convert_trap_info(const struct desc_ptr *desc,
906 				      struct trap_info *traps, bool full)
907 {
908 	unsigned in, out, count;
909 
910 	count = (desc->size+1) / sizeof(gate_desc);
911 	BUG_ON(count > 256);
912 
913 	for (in = out = 0; in < count; in++) {
914 		gate_desc *entry = (gate_desc *)(desc->address) + in;
915 
916 		if (cvt_gate_to_trap(in, entry, &traps[out]) || full)
917 			out++;
918 	}
919 
920 	return out;
921 }
922 
xen_copy_trap_info(struct trap_info * traps)923 void xen_copy_trap_info(struct trap_info *traps)
924 {
925 	const struct desc_ptr *desc = this_cpu_ptr(&idt_desc);
926 
927 	xen_convert_trap_info(desc, traps, true);
928 }
929 
930 /* Load a new IDT into Xen.  In principle this can be per-CPU, so we
931    hold a spinlock to protect the static traps[] array (static because
932    it avoids allocation, and saves stack space). */
xen_load_idt(const struct desc_ptr * desc)933 static void xen_load_idt(const struct desc_ptr *desc)
934 {
935 	static DEFINE_SPINLOCK(lock);
936 	static struct trap_info traps[257];
937 	static const struct trap_info zero = { };
938 	unsigned out;
939 
940 	trace_xen_cpu_load_idt(desc);
941 
942 	spin_lock(&lock);
943 
944 	memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
945 
946 	out = xen_convert_trap_info(desc, traps, false);
947 	traps[out] = zero;
948 
949 	xen_mc_flush();
950 	if (HYPERVISOR_set_trap_table(traps))
951 		BUG();
952 
953 	spin_unlock(&lock);
954 }
955 
956 /* Write a GDT descriptor entry.  Ignore LDT descriptors, since
957    they're handled differently. */
xen_write_gdt_entry(struct desc_struct * dt,int entry,const void * desc,int type)958 static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
959 				const void *desc, int type)
960 {
961 	trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
962 
963 	preempt_disable();
964 
965 	switch (type) {
966 	case DESC_LDT:
967 	case DESC_TSS:
968 		/* ignore */
969 		break;
970 
971 	default: {
972 		xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]);
973 
974 		xen_mc_flush();
975 		if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
976 			BUG();
977 	}
978 
979 	}
980 
981 	preempt_enable();
982 }
983 
984 /*
985  * Version of write_gdt_entry for use at early boot-time needed to
986  * update an entry as simply as possible.
987  */
xen_write_gdt_entry_boot(struct desc_struct * dt,int entry,const void * desc,int type)988 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
989 					    const void *desc, int type)
990 {
991 	trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
992 
993 	switch (type) {
994 	case DESC_LDT:
995 	case DESC_TSS:
996 		/* ignore */
997 		break;
998 
999 	default: {
1000 		xmaddr_t maddr = virt_to_machine(&dt[entry]);
1001 
1002 		if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
1003 			dt[entry] = *(struct desc_struct *)desc;
1004 	}
1005 
1006 	}
1007 }
1008 
xen_load_sp0(unsigned long sp0)1009 static void xen_load_sp0(unsigned long sp0)
1010 {
1011 	struct multicall_space mcs;
1012 
1013 	mcs = xen_mc_entry(0);
1014 	MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0);
1015 	xen_mc_issue(XEN_LAZY_CPU);
1016 	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
1017 }
1018 
1019 #ifdef CONFIG_X86_IOPL_IOPERM
xen_invalidate_io_bitmap(void)1020 static void xen_invalidate_io_bitmap(void)
1021 {
1022 	struct physdev_set_iobitmap iobitmap = {
1023 		.bitmap = NULL,
1024 		.nr_ports = 0,
1025 	};
1026 
1027 	native_tss_invalidate_io_bitmap();
1028 	HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
1029 }
1030 
xen_update_io_bitmap(void)1031 static void xen_update_io_bitmap(void)
1032 {
1033 	struct physdev_set_iobitmap iobitmap;
1034 	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1035 
1036 	native_tss_update_io_bitmap();
1037 
1038 	iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) +
1039 			  tss->x86_tss.io_bitmap_base;
1040 	if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID)
1041 		iobitmap.nr_ports = 0;
1042 	else
1043 		iobitmap.nr_ports = IO_BITMAP_BITS;
1044 
1045 	HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
1046 }
1047 #endif
1048 
xen_io_delay(void)1049 static void xen_io_delay(void)
1050 {
1051 }
1052 
1053 static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
1054 
xen_read_cr0(void)1055 static unsigned long xen_read_cr0(void)
1056 {
1057 	unsigned long cr0 = this_cpu_read(xen_cr0_value);
1058 
1059 	if (unlikely(cr0 == 0)) {
1060 		cr0 = native_read_cr0();
1061 		this_cpu_write(xen_cr0_value, cr0);
1062 	}
1063 
1064 	return cr0;
1065 }
1066 
xen_write_cr0(unsigned long cr0)1067 static void xen_write_cr0(unsigned long cr0)
1068 {
1069 	struct multicall_space mcs;
1070 
1071 	this_cpu_write(xen_cr0_value, cr0);
1072 
1073 	/* Only pay attention to cr0.TS; everything else is
1074 	   ignored. */
1075 	mcs = xen_mc_entry(0);
1076 
1077 	MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0);
1078 
1079 	xen_mc_issue(XEN_LAZY_CPU);
1080 }
1081 
xen_write_cr4(unsigned long cr4)1082 static void xen_write_cr4(unsigned long cr4)
1083 {
1084 	cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE);
1085 
1086 	native_write_cr4(cr4);
1087 }
1088 
xen_do_read_msr(unsigned int msr,int * err)1089 static u64 xen_do_read_msr(unsigned int msr, int *err)
1090 {
1091 	u64 val = 0;	/* Avoid uninitialized value for safe variant. */
1092 
1093 	if (pmu_msr_read(msr, &val, err))
1094 		return val;
1095 
1096 	if (err)
1097 		val = native_read_msr_safe(msr, err);
1098 	else
1099 		val = native_read_msr(msr);
1100 
1101 	switch (msr) {
1102 	case MSR_IA32_APICBASE:
1103 		val &= ~X2APIC_ENABLE;
1104 		if (smp_processor_id() == 0)
1105 			val |= MSR_IA32_APICBASE_BSP;
1106 		else
1107 			val &= ~MSR_IA32_APICBASE_BSP;
1108 		break;
1109 	}
1110 	return val;
1111 }
1112 
set_seg(unsigned int which,unsigned int low,unsigned int high,int * err)1113 static void set_seg(unsigned int which, unsigned int low, unsigned int high,
1114 		    int *err)
1115 {
1116 	u64 base = ((u64)high << 32) | low;
1117 
1118 	if (HYPERVISOR_set_segment_base(which, base) == 0)
1119 		return;
1120 
1121 	if (err)
1122 		*err = -EIO;
1123 	else
1124 		WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base);
1125 }
1126 
1127 /*
1128  * Support write_msr_safe() and write_msr() semantics.
1129  * With err == NULL write_msr() semantics are selected.
1130  * Supplying an err pointer requires err to be pre-initialized with 0.
1131  */
xen_do_write_msr(unsigned int msr,unsigned int low,unsigned int high,int * err)1132 static void xen_do_write_msr(unsigned int msr, unsigned int low,
1133 			     unsigned int high, int *err)
1134 {
1135 	switch (msr) {
1136 	case MSR_FS_BASE:
1137 		set_seg(SEGBASE_FS, low, high, err);
1138 		break;
1139 
1140 	case MSR_KERNEL_GS_BASE:
1141 		set_seg(SEGBASE_GS_USER, low, high, err);
1142 		break;
1143 
1144 	case MSR_GS_BASE:
1145 		set_seg(SEGBASE_GS_KERNEL, low, high, err);
1146 		break;
1147 
1148 	case MSR_STAR:
1149 	case MSR_CSTAR:
1150 	case MSR_LSTAR:
1151 	case MSR_SYSCALL_MASK:
1152 	case MSR_IA32_SYSENTER_CS:
1153 	case MSR_IA32_SYSENTER_ESP:
1154 	case MSR_IA32_SYSENTER_EIP:
1155 		/* Fast syscall setup is all done in hypercalls, so
1156 		   these are all ignored.  Stub them out here to stop
1157 		   Xen console noise. */
1158 		break;
1159 
1160 	default:
1161 		if (!pmu_msr_write(msr, low, high, err)) {
1162 			if (err)
1163 				*err = native_write_msr_safe(msr, low, high);
1164 			else
1165 				native_write_msr(msr, low, high);
1166 		}
1167 	}
1168 }
1169 
xen_read_msr_safe(unsigned int msr,int * err)1170 static u64 xen_read_msr_safe(unsigned int msr, int *err)
1171 {
1172 	return xen_do_read_msr(msr, err);
1173 }
1174 
xen_write_msr_safe(unsigned int msr,unsigned int low,unsigned int high)1175 static int xen_write_msr_safe(unsigned int msr, unsigned int low,
1176 			      unsigned int high)
1177 {
1178 	int err = 0;
1179 
1180 	xen_do_write_msr(msr, low, high, &err);
1181 
1182 	return err;
1183 }
1184 
xen_read_msr(unsigned int msr)1185 static u64 xen_read_msr(unsigned int msr)
1186 {
1187 	int err;
1188 
1189 	return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL);
1190 }
1191 
xen_write_msr(unsigned int msr,unsigned low,unsigned high)1192 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high)
1193 {
1194 	int err;
1195 
1196 	xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL);
1197 }
1198 
1199 /* This is called once we have the cpu_possible_mask */
xen_setup_vcpu_info_placement(void)1200 void __init xen_setup_vcpu_info_placement(void)
1201 {
1202 	int cpu;
1203 
1204 	for_each_possible_cpu(cpu) {
1205 		/* Set up direct vCPU id mapping for PV guests. */
1206 		per_cpu(xen_vcpu_id, cpu) = cpu;
1207 		xen_vcpu_setup(cpu);
1208 	}
1209 
1210 	pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct);
1211 	pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct);
1212 	pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct);
1213 	pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct);
1214 }
1215 
1216 static const struct pv_info xen_info __initconst = {
1217 	.extra_user_64bit_cs = FLAT_USER_CS64,
1218 	.name = "Xen",
1219 };
1220 
1221 static const typeof(pv_ops) xen_cpu_ops __initconst = {
1222 	.cpu = {
1223 		.cpuid = xen_cpuid,
1224 
1225 		.set_debugreg = xen_set_debugreg,
1226 		.get_debugreg = xen_get_debugreg,
1227 
1228 		.read_cr0 = xen_read_cr0,
1229 		.write_cr0 = xen_write_cr0,
1230 
1231 		.write_cr4 = xen_write_cr4,
1232 
1233 		.read_msr = xen_read_msr,
1234 		.write_msr = xen_write_msr,
1235 
1236 		.read_msr_safe = xen_read_msr_safe,
1237 		.write_msr_safe = xen_write_msr_safe,
1238 
1239 		.read_pmc = xen_read_pmc,
1240 
1241 		.load_tr_desc = paravirt_nop,
1242 		.set_ldt = xen_set_ldt,
1243 		.load_gdt = xen_load_gdt,
1244 		.load_idt = xen_load_idt,
1245 		.load_tls = xen_load_tls,
1246 		.load_gs_index = xen_load_gs_index,
1247 
1248 		.alloc_ldt = xen_alloc_ldt,
1249 		.free_ldt = xen_free_ldt,
1250 
1251 		.store_tr = xen_store_tr,
1252 
1253 		.write_ldt_entry = xen_write_ldt_entry,
1254 		.write_gdt_entry = xen_write_gdt_entry,
1255 		.write_idt_entry = xen_write_idt_entry,
1256 		.load_sp0 = xen_load_sp0,
1257 
1258 #ifdef CONFIG_X86_IOPL_IOPERM
1259 		.invalidate_io_bitmap = xen_invalidate_io_bitmap,
1260 		.update_io_bitmap = xen_update_io_bitmap,
1261 #endif
1262 		.io_delay = xen_io_delay,
1263 
1264 		.start_context_switch = xen_start_context_switch,
1265 		.end_context_switch = xen_end_context_switch,
1266 	},
1267 };
1268 
xen_restart(char * msg)1269 static void xen_restart(char *msg)
1270 {
1271 	xen_reboot(SHUTDOWN_reboot);
1272 }
1273 
xen_machine_halt(void)1274 static void xen_machine_halt(void)
1275 {
1276 	xen_reboot(SHUTDOWN_poweroff);
1277 }
1278 
xen_machine_power_off(void)1279 static void xen_machine_power_off(void)
1280 {
1281 	do_kernel_power_off();
1282 	xen_reboot(SHUTDOWN_poweroff);
1283 }
1284 
xen_crash_shutdown(struct pt_regs * regs)1285 static void xen_crash_shutdown(struct pt_regs *regs)
1286 {
1287 	xen_reboot(SHUTDOWN_crash);
1288 }
1289 
1290 static const struct machine_ops xen_machine_ops __initconst = {
1291 	.restart = xen_restart,
1292 	.halt = xen_machine_halt,
1293 	.power_off = xen_machine_power_off,
1294 	.shutdown = xen_machine_halt,
1295 	.crash_shutdown = xen_crash_shutdown,
1296 	.emergency_restart = xen_emergency_restart,
1297 };
1298 
xen_get_nmi_reason(void)1299 static unsigned char xen_get_nmi_reason(void)
1300 {
1301 	unsigned char reason = 0;
1302 
1303 	/* Construct a value which looks like it came from port 0x61. */
1304 	if (test_bit(_XEN_NMIREASON_io_error,
1305 		     &HYPERVISOR_shared_info->arch.nmi_reason))
1306 		reason |= NMI_REASON_IOCHK;
1307 	if (test_bit(_XEN_NMIREASON_pci_serr,
1308 		     &HYPERVISOR_shared_info->arch.nmi_reason))
1309 		reason |= NMI_REASON_SERR;
1310 
1311 	return reason;
1312 }
1313 
xen_boot_params_init_edd(void)1314 static void __init xen_boot_params_init_edd(void)
1315 {
1316 #if IS_ENABLED(CONFIG_EDD)
1317 	struct xen_platform_op op;
1318 	struct edd_info *edd_info;
1319 	u32 *mbr_signature;
1320 	unsigned nr;
1321 	int ret;
1322 
1323 	edd_info = boot_params.eddbuf;
1324 	mbr_signature = boot_params.edd_mbr_sig_buffer;
1325 
1326 	op.cmd = XENPF_firmware_info;
1327 
1328 	op.u.firmware_info.type = XEN_FW_DISK_INFO;
1329 	for (nr = 0; nr < EDDMAXNR; nr++) {
1330 		struct edd_info *info = edd_info + nr;
1331 
1332 		op.u.firmware_info.index = nr;
1333 		info->params.length = sizeof(info->params);
1334 		set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params,
1335 				     &info->params);
1336 		ret = HYPERVISOR_platform_op(&op);
1337 		if (ret)
1338 			break;
1339 
1340 #define C(x) info->x = op.u.firmware_info.u.disk_info.x
1341 		C(device);
1342 		C(version);
1343 		C(interface_support);
1344 		C(legacy_max_cylinder);
1345 		C(legacy_max_head);
1346 		C(legacy_sectors_per_track);
1347 #undef C
1348 	}
1349 	boot_params.eddbuf_entries = nr;
1350 
1351 	op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE;
1352 	for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) {
1353 		op.u.firmware_info.index = nr;
1354 		ret = HYPERVISOR_platform_op(&op);
1355 		if (ret)
1356 			break;
1357 		mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature;
1358 	}
1359 	boot_params.edd_mbr_sig_buf_entries = nr;
1360 #endif
1361 }
1362 
1363 /*
1364  * Set up the GDT and segment registers for -fstack-protector.  Until
1365  * we do this, we have to be careful not to call any stack-protected
1366  * function, which is most of the kernel.
1367  */
xen_setup_gdt(int cpu)1368 static void __init xen_setup_gdt(int cpu)
1369 {
1370 	pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot;
1371 	pv_ops.cpu.load_gdt = xen_load_gdt_boot;
1372 
1373 	switch_gdt_and_percpu_base(cpu);
1374 
1375 	pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry;
1376 	pv_ops.cpu.load_gdt = xen_load_gdt;
1377 }
1378 
xen_dom0_set_legacy_features(void)1379 static void __init xen_dom0_set_legacy_features(void)
1380 {
1381 	x86_platform.legacy.rtc = 1;
1382 }
1383 
xen_domu_set_legacy_features(void)1384 static void __init xen_domu_set_legacy_features(void)
1385 {
1386 	x86_platform.legacy.rtc = 0;
1387 }
1388 
1389 extern void early_xen_iret_patch(void);
1390 
1391 /* First C function to be called on Xen boot */
xen_start_kernel(struct start_info * si)1392 asmlinkage __visible void __init xen_start_kernel(struct start_info *si)
1393 {
1394 	struct physdev_set_iopl set_iopl;
1395 	unsigned long initrd_start = 0;
1396 	int rc;
1397 
1398 	if (!si)
1399 		return;
1400 
1401 	clear_bss();
1402 
1403 	xen_start_info = si;
1404 
1405 	__text_gen_insn(&early_xen_iret_patch,
1406 			JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret,
1407 			JMP32_INSN_SIZE);
1408 
1409 	xen_domain_type = XEN_PV_DOMAIN;
1410 	xen_start_flags = xen_start_info->flags;
1411 	/* Interrupts are guaranteed to be off initially. */
1412 	early_boot_irqs_disabled = true;
1413 	static_call_update_early(xen_hypercall, xen_hypercall_pv);
1414 
1415 	xen_setup_features();
1416 
1417 	/* Install Xen paravirt ops */
1418 	pv_info = xen_info;
1419 	pv_ops.cpu = xen_cpu_ops.cpu;
1420 	xen_init_irq_ops();
1421 
1422 	/*
1423 	 * Setup xen_vcpu early because it is needed for
1424 	 * local_irq_disable(), irqs_disabled(), e.g. in printk().
1425 	 *
1426 	 * Don't do the full vcpu_info placement stuff until we have
1427 	 * the cpu_possible_mask and a non-dummy shared_info.
1428 	 */
1429 	xen_vcpu_info_reset(0);
1430 
1431 	x86_platform.get_nmi_reason = xen_get_nmi_reason;
1432 	x86_platform.realmode_reserve = x86_init_noop;
1433 	x86_platform.realmode_init = x86_init_noop;
1434 
1435 	x86_init.resources.memory_setup = xen_memory_setup;
1436 	x86_init.irqs.intr_mode_select	= x86_init_noop;
1437 	x86_init.irqs.intr_mode_init	= x86_64_probe_apic;
1438 	x86_init.oem.arch_setup = xen_arch_setup;
1439 	x86_init.oem.banner = xen_banner;
1440 	x86_init.hyper.init_platform = xen_pv_init_platform;
1441 	x86_init.hyper.guest_late_init = xen_pv_guest_late_init;
1442 
1443 	/*
1444 	 * Set up some pagetable state before starting to set any ptes.
1445 	 */
1446 
1447 	xen_setup_machphys_mapping();
1448 	xen_init_mmu_ops();
1449 
1450 	/* Prevent unwanted bits from being set in PTEs. */
1451 	__supported_pte_mask &= ~_PAGE_GLOBAL;
1452 	__default_kernel_pte_mask &= ~_PAGE_GLOBAL;
1453 
1454 	/* Get mfn list */
1455 	xen_build_dynamic_phys_to_machine();
1456 
1457 	/* Work out if we support NX */
1458 	get_cpu_cap(&boot_cpu_data);
1459 	x86_configure_nx();
1460 
1461 	/*
1462 	 * Set up kernel GDT and segment registers, mainly so that
1463 	 * -fstack-protector code can be executed.
1464 	 */
1465 	xen_setup_gdt(0);
1466 
1467 	/* Determine virtual and physical address sizes */
1468 	get_cpu_address_sizes(&boot_cpu_data);
1469 
1470 	/* Let's presume PV guests always boot on vCPU with id 0. */
1471 	per_cpu(xen_vcpu_id, 0) = 0;
1472 
1473 	idt_setup_early_handler();
1474 
1475 	xen_init_capabilities();
1476 
1477 	/*
1478 	 * set up the basic apic ops.
1479 	 */
1480 	xen_init_apic();
1481 
1482 	machine_ops = xen_machine_ops;
1483 
1484 	/*
1485 	 * The only reliable way to retain the initial address of the
1486 	 * percpu gdt_page is to remember it here, so we can go and
1487 	 * mark it RW later, when the initial percpu area is freed.
1488 	 */
1489 	xen_initial_gdt = &per_cpu(gdt_page, 0);
1490 
1491 	xen_smp_init();
1492 
1493 #ifdef CONFIG_ACPI_NUMA
1494 	/*
1495 	 * The pages we from Xen are not related to machine pages, so
1496 	 * any NUMA information the kernel tries to get from ACPI will
1497 	 * be meaningless.  Prevent it from trying.
1498 	 */
1499 	disable_srat();
1500 #endif
1501 	WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv));
1502 
1503 	local_irq_disable();
1504 
1505 	xen_raw_console_write("mapping kernel into physical memory\n");
1506 	xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base,
1507 				   xen_start_info->nr_pages);
1508 	xen_reserve_special_pages();
1509 
1510 	/*
1511 	 * We used to do this in xen_arch_setup, but that is too late
1512 	 * on AMD were early_cpu_init (run before ->arch_setup()) calls
1513 	 * early_amd_init which pokes 0xcf8 port.
1514 	 */
1515 	set_iopl.iopl = 1;
1516 	rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
1517 	if (rc != 0)
1518 		xen_raw_printk("physdev_op failed %d\n", rc);
1519 
1520 
1521 	if (xen_start_info->mod_start) {
1522 	    if (xen_start_info->flags & SIF_MOD_START_PFN)
1523 		initrd_start = PFN_PHYS(xen_start_info->mod_start);
1524 	    else
1525 		initrd_start = __pa(xen_start_info->mod_start);
1526 	}
1527 
1528 	/* Poke various useful things into boot_params */
1529 	boot_params.hdr.type_of_loader = (9 << 4) | 0;
1530 	boot_params.hdr.ramdisk_image = initrd_start;
1531 	boot_params.hdr.ramdisk_size = xen_start_info->mod_len;
1532 	boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line);
1533 	boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN;
1534 
1535 	if (!xen_initial_domain()) {
1536 		if (pci_xen)
1537 			x86_init.pci.arch_init = pci_xen_init;
1538 		x86_platform.set_legacy_features =
1539 				xen_domu_set_legacy_features;
1540 	} else {
1541 		const struct dom0_vga_console_info *info =
1542 			(void *)((char *)xen_start_info +
1543 				 xen_start_info->console.dom0.info_off);
1544 		struct xen_platform_op op = {
1545 			.cmd = XENPF_firmware_info,
1546 			.interface_version = XENPF_INTERFACE_VERSION,
1547 			.u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS,
1548 		};
1549 
1550 		x86_platform.set_legacy_features =
1551 				xen_dom0_set_legacy_features;
1552 		xen_init_vga(info, xen_start_info->console.dom0.info_size,
1553 			     &boot_params.screen_info);
1554 		xen_start_info->console.domU.mfn = 0;
1555 		xen_start_info->console.domU.evtchn = 0;
1556 
1557 		if (HYPERVISOR_platform_op(&op) == 0)
1558 			boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags;
1559 
1560 		/* Make sure ACS will be enabled */
1561 		pci_request_acs();
1562 
1563 		xen_acpi_sleep_register();
1564 
1565 		xen_boot_params_init_edd();
1566 
1567 #ifdef CONFIG_ACPI
1568 		/*
1569 		 * Disable selecting "Firmware First mode" for correctable
1570 		 * memory errors, as this is the duty of the hypervisor to
1571 		 * decide.
1572 		 */
1573 		acpi_disable_cmcff = 1;
1574 #endif
1575 	}
1576 
1577 	xen_add_preferred_consoles();
1578 
1579 #ifdef CONFIG_PCI
1580 	/* PCI BIOS service won't work from a PV guest. */
1581 	pci_probe &= ~PCI_PROBE_BIOS;
1582 #endif
1583 	xen_raw_console_write("about to get started...\n");
1584 
1585 	/* We need this for printk timestamps */
1586 	xen_setup_runstate_info(0);
1587 
1588 	xen_efi_init(&boot_params);
1589 
1590 	/* Start the world */
1591 	cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */
1592 	x86_64_start_reservations((char *)__pa_symbol(&boot_params));
1593 }
1594 
xen_cpu_up_prepare_pv(unsigned int cpu)1595 static int xen_cpu_up_prepare_pv(unsigned int cpu)
1596 {
1597 	int rc;
1598 
1599 	if (per_cpu(xen_vcpu, cpu) == NULL)
1600 		return -ENODEV;
1601 
1602 	xen_setup_timer(cpu);
1603 
1604 	rc = xen_smp_intr_init(cpu);
1605 	if (rc) {
1606 		WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n",
1607 		     cpu, rc);
1608 		return rc;
1609 	}
1610 
1611 	rc = xen_smp_intr_init_pv(cpu);
1612 	if (rc) {
1613 		WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n",
1614 		     cpu, rc);
1615 		return rc;
1616 	}
1617 
1618 	return 0;
1619 }
1620 
xen_cpu_dead_pv(unsigned int cpu)1621 static int xen_cpu_dead_pv(unsigned int cpu)
1622 {
1623 	xen_smp_intr_free(cpu);
1624 	xen_smp_intr_free_pv(cpu);
1625 
1626 	xen_teardown_timer(cpu);
1627 
1628 	return 0;
1629 }
1630 
xen_platform_pv(void)1631 static uint32_t __init xen_platform_pv(void)
1632 {
1633 	if (xen_pv_domain())
1634 		return xen_cpuid_base();
1635 
1636 	return 0;
1637 }
1638 
1639 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = {
1640 	.name                   = "Xen PV",
1641 	.detect                 = xen_platform_pv,
1642 	.type			= X86_HYPER_XEN_PV,
1643 	.runtime.pin_vcpu       = xen_pin_vcpu,
1644 	.ignore_nopv		= true,
1645 };
1646