1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Copyright (C) 1994  Linus Torvalds
4  *
5  *  Cyrix stuff, June 1998 by:
6  *	- Rafael R. Reilova (moved everything from head.S),
7  *        <rreilova@ececs.uc.edu>
8  *	- Channing Corn (tests & fixes),
9  *	- Andrew D. Balsa (code cleanup).
10  */
11 #include <linux/init.h>
12 #include <linux/cpu.h>
13 #include <linux/module.h>
14 #include <linux/nospec.h>
15 #include <linux/prctl.h>
16 #include <linux/sched/smt.h>
17 #include <linux/pgtable.h>
18 #include <linux/bpf.h>
19 
20 #include <asm/spec-ctrl.h>
21 #include <asm/cmdline.h>
22 #include <asm/bugs.h>
23 #include <asm/processor.h>
24 #include <asm/processor-flags.h>
25 #include <asm/fpu/api.h>
26 #include <asm/msr.h>
27 #include <asm/vmx.h>
28 #include <asm/paravirt.h>
29 #include <asm/cpu_device_id.h>
30 #include <asm/e820/api.h>
31 #include <asm/hypervisor.h>
32 #include <asm/tlbflush.h>
33 #include <asm/cpu.h>
34 
35 #include "cpu.h"
36 
37 static void __init spectre_v1_select_mitigation(void);
38 static void __init spectre_v2_select_mitigation(void);
39 static void __init retbleed_select_mitigation(void);
40 static void __init spectre_v2_user_select_mitigation(void);
41 static void __init ssb_select_mitigation(void);
42 static void __init l1tf_select_mitigation(void);
43 static void __init mds_select_mitigation(void);
44 static void __init md_clear_update_mitigation(void);
45 static void __init md_clear_select_mitigation(void);
46 static void __init taa_select_mitigation(void);
47 static void __init mmio_select_mitigation(void);
48 static void __init srbds_select_mitigation(void);
49 static void __init l1d_flush_select_mitigation(void);
50 static void __init srso_select_mitigation(void);
51 static void __init gds_select_mitigation(void);
52 static void __init its_select_mitigation(void);
53 
54 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
55 u64 x86_spec_ctrl_base;
56 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
57 
58 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
59 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
60 EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current);
61 
62 u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB;
63 
64 static u64 __ro_after_init x86_arch_cap_msr;
65 
66 static DEFINE_MUTEX(spec_ctrl_mutex);
67 
68 void (*x86_return_thunk)(void) __ro_after_init = __x86_return_thunk;
69 
set_return_thunk(void * thunk)70 static void __init set_return_thunk(void *thunk)
71 {
72 	if (x86_return_thunk != __x86_return_thunk)
73 		pr_warn("x86/bugs: return thunk changed\n");
74 
75 	x86_return_thunk = thunk;
76 }
77 
78 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
update_spec_ctrl(u64 val)79 static void update_spec_ctrl(u64 val)
80 {
81 	this_cpu_write(x86_spec_ctrl_current, val);
82 	wrmsrl(MSR_IA32_SPEC_CTRL, val);
83 }
84 
85 /*
86  * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
87  * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
88  */
update_spec_ctrl_cond(u64 val)89 void update_spec_ctrl_cond(u64 val)
90 {
91 	if (this_cpu_read(x86_spec_ctrl_current) == val)
92 		return;
93 
94 	this_cpu_write(x86_spec_ctrl_current, val);
95 
96 	/*
97 	 * When KERNEL_IBRS this MSR is written on return-to-user, unless
98 	 * forced the update can be delayed until that time.
99 	 */
100 	if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
101 		wrmsrl(MSR_IA32_SPEC_CTRL, val);
102 }
103 
spec_ctrl_current(void)104 noinstr u64 spec_ctrl_current(void)
105 {
106 	return this_cpu_read(x86_spec_ctrl_current);
107 }
108 EXPORT_SYMBOL_GPL(spec_ctrl_current);
109 
110 /*
111  * AMD specific MSR info for Speculative Store Bypass control.
112  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
113  */
114 u64 __ro_after_init x86_amd_ls_cfg_base;
115 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
116 
117 /* Control conditional STIBP in switch_to() */
118 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
119 /* Control conditional IBPB in switch_mm() */
120 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
121 /* Control unconditional IBPB in switch_mm() */
122 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
123 
124 /* Control IBPB on vCPU load */
125 DEFINE_STATIC_KEY_FALSE(switch_vcpu_ibpb);
126 EXPORT_SYMBOL_GPL(switch_vcpu_ibpb);
127 
128 /* Control MDS CPU buffer clear before idling (halt, mwait) */
129 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
130 EXPORT_SYMBOL_GPL(mds_idle_clear);
131 
132 /*
133  * Controls whether l1d flush based mitigations are enabled,
134  * based on hw features and admin setting via boot parameter
135  * defaults to false
136  */
137 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
138 
139 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
140 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
141 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
142 
cpu_select_mitigations(void)143 void __init cpu_select_mitigations(void)
144 {
145 	/*
146 	 * Read the SPEC_CTRL MSR to account for reserved bits which may
147 	 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
148 	 * init code as it is not enumerated and depends on the family.
149 	 */
150 	if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
151 		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
152 
153 		/*
154 		 * Previously running kernel (kexec), may have some controls
155 		 * turned ON. Clear them and let the mitigations setup below
156 		 * rediscover them based on configuration.
157 		 */
158 		x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
159 	}
160 
161 	x86_arch_cap_msr = x86_read_arch_cap_msr();
162 
163 	/* Select the proper CPU mitigations before patching alternatives: */
164 	spectre_v1_select_mitigation();
165 	spectre_v2_select_mitigation();
166 	/*
167 	 * retbleed_select_mitigation() relies on the state set by
168 	 * spectre_v2_select_mitigation(); specifically it wants to know about
169 	 * spectre_v2=ibrs.
170 	 */
171 	retbleed_select_mitigation();
172 	/*
173 	 * spectre_v2_user_select_mitigation() relies on the state set by
174 	 * retbleed_select_mitigation(); specifically the STIBP selection is
175 	 * forced for UNRET or IBPB.
176 	 */
177 	spectre_v2_user_select_mitigation();
178 	ssb_select_mitigation();
179 	l1tf_select_mitigation();
180 	md_clear_select_mitigation();
181 	srbds_select_mitigation();
182 	l1d_flush_select_mitigation();
183 
184 	/*
185 	 * srso_select_mitigation() depends and must run after
186 	 * retbleed_select_mitigation().
187 	 */
188 	srso_select_mitigation();
189 	gds_select_mitigation();
190 	its_select_mitigation();
191 }
192 
193 /*
194  * NOTE: This function is *only* called for SVM, since Intel uses
195  * MSR_IA32_SPEC_CTRL for SSBD.
196  */
197 void
x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl,bool setguest)198 x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
199 {
200 	u64 guestval, hostval;
201 	struct thread_info *ti = current_thread_info();
202 
203 	/*
204 	 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
205 	 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
206 	 */
207 	if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
208 	    !static_cpu_has(X86_FEATURE_VIRT_SSBD))
209 		return;
210 
211 	/*
212 	 * If the host has SSBD mitigation enabled, force it in the host's
213 	 * virtual MSR value. If its not permanently enabled, evaluate
214 	 * current's TIF_SSBD thread flag.
215 	 */
216 	if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
217 		hostval = SPEC_CTRL_SSBD;
218 	else
219 		hostval = ssbd_tif_to_spec_ctrl(ti->flags);
220 
221 	/* Sanitize the guest value */
222 	guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
223 
224 	if (hostval != guestval) {
225 		unsigned long tif;
226 
227 		tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
228 				 ssbd_spec_ctrl_to_tif(hostval);
229 
230 		speculation_ctrl_update(tif);
231 	}
232 }
233 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
234 
x86_amd_ssb_disable(void)235 static void x86_amd_ssb_disable(void)
236 {
237 	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
238 
239 	if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
240 		wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
241 	else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
242 		wrmsrl(MSR_AMD64_LS_CFG, msrval);
243 }
244 
245 #undef pr_fmt
246 #define pr_fmt(fmt)	"MDS: " fmt
247 
248 /* Default mitigation for MDS-affected CPUs */
249 static enum mds_mitigations mds_mitigation __ro_after_init =
250 	IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_AUTO : MDS_MITIGATION_OFF;
251 static bool mds_nosmt __ro_after_init = false;
252 
253 static const char * const mds_strings[] = {
254 	[MDS_MITIGATION_OFF]	= "Vulnerable",
255 	[MDS_MITIGATION_FULL]	= "Mitigation: Clear CPU buffers",
256 	[MDS_MITIGATION_VMWERV]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
257 };
258 
259 enum taa_mitigations {
260 	TAA_MITIGATION_OFF,
261 	TAA_MITIGATION_AUTO,
262 	TAA_MITIGATION_UCODE_NEEDED,
263 	TAA_MITIGATION_VERW,
264 	TAA_MITIGATION_TSX_DISABLED,
265 };
266 
267 /* Default mitigation for TAA-affected CPUs */
268 static enum taa_mitigations taa_mitigation __ro_after_init =
269 	IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_AUTO : TAA_MITIGATION_OFF;
270 
271 enum mmio_mitigations {
272 	MMIO_MITIGATION_OFF,
273 	MMIO_MITIGATION_AUTO,
274 	MMIO_MITIGATION_UCODE_NEEDED,
275 	MMIO_MITIGATION_VERW,
276 };
277 
278 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
279 static enum mmio_mitigations mmio_mitigation __ro_after_init =
280 	IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ?	MMIO_MITIGATION_AUTO : MMIO_MITIGATION_OFF;
281 
282 enum rfds_mitigations {
283 	RFDS_MITIGATION_OFF,
284 	RFDS_MITIGATION_AUTO,
285 	RFDS_MITIGATION_VERW,
286 	RFDS_MITIGATION_UCODE_NEEDED,
287 };
288 
289 /* Default mitigation for Register File Data Sampling */
290 static enum rfds_mitigations rfds_mitigation __ro_after_init =
291 	IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_AUTO : RFDS_MITIGATION_OFF;
292 
mds_select_mitigation(void)293 static void __init mds_select_mitigation(void)
294 {
295 	if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
296 		mds_mitigation = MDS_MITIGATION_OFF;
297 		return;
298 	}
299 
300 	if (mds_mitigation == MDS_MITIGATION_AUTO)
301 		mds_mitigation = MDS_MITIGATION_FULL;
302 
303 	if (mds_mitigation == MDS_MITIGATION_FULL) {
304 		if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
305 			mds_mitigation = MDS_MITIGATION_VMWERV;
306 
307 		setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF);
308 
309 		if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
310 		    (mds_nosmt || cpu_mitigations_auto_nosmt()))
311 			cpu_smt_disable(false);
312 	}
313 }
314 
mds_cmdline(char * str)315 static int __init mds_cmdline(char *str)
316 {
317 	if (!boot_cpu_has_bug(X86_BUG_MDS))
318 		return 0;
319 
320 	if (!str)
321 		return -EINVAL;
322 
323 	if (!strcmp(str, "off"))
324 		mds_mitigation = MDS_MITIGATION_OFF;
325 	else if (!strcmp(str, "full"))
326 		mds_mitigation = MDS_MITIGATION_FULL;
327 	else if (!strcmp(str, "full,nosmt")) {
328 		mds_mitigation = MDS_MITIGATION_FULL;
329 		mds_nosmt = true;
330 	}
331 
332 	return 0;
333 }
334 early_param("mds", mds_cmdline);
335 
336 #undef pr_fmt
337 #define pr_fmt(fmt)	"TAA: " fmt
338 
339 static bool taa_nosmt __ro_after_init;
340 
341 static const char * const taa_strings[] = {
342 	[TAA_MITIGATION_OFF]		= "Vulnerable",
343 	[TAA_MITIGATION_UCODE_NEEDED]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
344 	[TAA_MITIGATION_VERW]		= "Mitigation: Clear CPU buffers",
345 	[TAA_MITIGATION_TSX_DISABLED]	= "Mitigation: TSX disabled",
346 };
347 
taa_select_mitigation(void)348 static void __init taa_select_mitigation(void)
349 {
350 	if (!boot_cpu_has_bug(X86_BUG_TAA)) {
351 		taa_mitigation = TAA_MITIGATION_OFF;
352 		return;
353 	}
354 
355 	/* TSX previously disabled by tsx=off */
356 	if (!boot_cpu_has(X86_FEATURE_RTM)) {
357 		taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
358 		return;
359 	}
360 
361 	if (cpu_mitigations_off()) {
362 		taa_mitigation = TAA_MITIGATION_OFF;
363 		return;
364 	}
365 
366 	/*
367 	 * TAA mitigation via VERW is turned off if both
368 	 * tsx_async_abort=off and mds=off are specified.
369 	 */
370 	if (taa_mitigation == TAA_MITIGATION_OFF &&
371 	    mds_mitigation == MDS_MITIGATION_OFF)
372 		return;
373 
374 	if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
375 		taa_mitigation = TAA_MITIGATION_VERW;
376 	else
377 		taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
378 
379 	/*
380 	 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
381 	 * A microcode update fixes this behavior to clear CPU buffers. It also
382 	 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
383 	 * ARCH_CAP_TSX_CTRL_MSR bit.
384 	 *
385 	 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
386 	 * update is required.
387 	 */
388 	if ( (x86_arch_cap_msr & ARCH_CAP_MDS_NO) &&
389 	    !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))
390 		taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
391 
392 	/*
393 	 * TSX is enabled, select alternate mitigation for TAA which is
394 	 * the same as MDS. Enable MDS static branch to clear CPU buffers.
395 	 *
396 	 * For guests that can't determine whether the correct microcode is
397 	 * present on host, enable the mitigation for UCODE_NEEDED as well.
398 	 */
399 	setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF);
400 
401 	if (taa_nosmt || cpu_mitigations_auto_nosmt())
402 		cpu_smt_disable(false);
403 }
404 
tsx_async_abort_parse_cmdline(char * str)405 static int __init tsx_async_abort_parse_cmdline(char *str)
406 {
407 	if (!boot_cpu_has_bug(X86_BUG_TAA))
408 		return 0;
409 
410 	if (!str)
411 		return -EINVAL;
412 
413 	if (!strcmp(str, "off")) {
414 		taa_mitigation = TAA_MITIGATION_OFF;
415 	} else if (!strcmp(str, "full")) {
416 		taa_mitigation = TAA_MITIGATION_VERW;
417 	} else if (!strcmp(str, "full,nosmt")) {
418 		taa_mitigation = TAA_MITIGATION_VERW;
419 		taa_nosmt = true;
420 	}
421 
422 	return 0;
423 }
424 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
425 
426 #undef pr_fmt
427 #define pr_fmt(fmt)	"MMIO Stale Data: " fmt
428 
429 static bool mmio_nosmt __ro_after_init = false;
430 
431 static const char * const mmio_strings[] = {
432 	[MMIO_MITIGATION_OFF]		= "Vulnerable",
433 	[MMIO_MITIGATION_UCODE_NEEDED]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
434 	[MMIO_MITIGATION_VERW]		= "Mitigation: Clear CPU buffers",
435 };
436 
mmio_select_mitigation(void)437 static void __init mmio_select_mitigation(void)
438 {
439 	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
440 	     boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
441 	     cpu_mitigations_off()) {
442 		mmio_mitigation = MMIO_MITIGATION_OFF;
443 		return;
444 	}
445 
446 	if (mmio_mitigation == MMIO_MITIGATION_OFF)
447 		return;
448 
449 	/*
450 	 * Enable CPU buffer clear mitigation for host and VMM, if also affected
451 	 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
452 	 */
453 	if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
454 					      boot_cpu_has(X86_FEATURE_RTM)))
455 		setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF);
456 
457 	/*
458 	 * X86_FEATURE_CLEAR_CPU_BUF could be enabled by other VERW based
459 	 * mitigations, disable KVM-only mitigation in that case.
460 	 */
461 	if (boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF))
462 		static_branch_disable(&mmio_stale_data_clear);
463 	else
464 		static_branch_enable(&mmio_stale_data_clear);
465 
466 	/*
467 	 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
468 	 * be propagated to uncore buffers, clearing the Fill buffers on idle
469 	 * is required irrespective of SMT state.
470 	 */
471 	if (!(x86_arch_cap_msr & ARCH_CAP_FBSDP_NO))
472 		static_branch_enable(&mds_idle_clear);
473 
474 	/*
475 	 * Check if the system has the right microcode.
476 	 *
477 	 * CPU Fill buffer clear mitigation is enumerated by either an explicit
478 	 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
479 	 * affected systems.
480 	 */
481 	if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) ||
482 	    (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
483 	     boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
484 	     !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)))
485 		mmio_mitigation = MMIO_MITIGATION_VERW;
486 	else
487 		mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
488 
489 	if (mmio_nosmt || cpu_mitigations_auto_nosmt())
490 		cpu_smt_disable(false);
491 }
492 
mmio_stale_data_parse_cmdline(char * str)493 static int __init mmio_stale_data_parse_cmdline(char *str)
494 {
495 	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
496 		return 0;
497 
498 	if (!str)
499 		return -EINVAL;
500 
501 	if (!strcmp(str, "off")) {
502 		mmio_mitigation = MMIO_MITIGATION_OFF;
503 	} else if (!strcmp(str, "full")) {
504 		mmio_mitigation = MMIO_MITIGATION_VERW;
505 	} else if (!strcmp(str, "full,nosmt")) {
506 		mmio_mitigation = MMIO_MITIGATION_VERW;
507 		mmio_nosmt = true;
508 	}
509 
510 	return 0;
511 }
512 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
513 
514 #undef pr_fmt
515 #define pr_fmt(fmt)	"Register File Data Sampling: " fmt
516 
517 static const char * const rfds_strings[] = {
518 	[RFDS_MITIGATION_OFF]			= "Vulnerable",
519 	[RFDS_MITIGATION_VERW]			= "Mitigation: Clear Register File",
520 	[RFDS_MITIGATION_UCODE_NEEDED]		= "Vulnerable: No microcode",
521 };
522 
rfds_select_mitigation(void)523 static void __init rfds_select_mitigation(void)
524 {
525 	if (!boot_cpu_has_bug(X86_BUG_RFDS) || cpu_mitigations_off()) {
526 		rfds_mitigation = RFDS_MITIGATION_OFF;
527 		return;
528 	}
529 	if (rfds_mitigation == RFDS_MITIGATION_OFF)
530 		return;
531 
532 	if (rfds_mitigation == RFDS_MITIGATION_AUTO)
533 		rfds_mitigation = RFDS_MITIGATION_VERW;
534 
535 	if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)
536 		setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF);
537 	else
538 		rfds_mitigation = RFDS_MITIGATION_UCODE_NEEDED;
539 }
540 
rfds_parse_cmdline(char * str)541 static __init int rfds_parse_cmdline(char *str)
542 {
543 	if (!str)
544 		return -EINVAL;
545 
546 	if (!boot_cpu_has_bug(X86_BUG_RFDS))
547 		return 0;
548 
549 	if (!strcmp(str, "off"))
550 		rfds_mitigation = RFDS_MITIGATION_OFF;
551 	else if (!strcmp(str, "on"))
552 		rfds_mitigation = RFDS_MITIGATION_VERW;
553 
554 	return 0;
555 }
556 early_param("reg_file_data_sampling", rfds_parse_cmdline);
557 
558 #undef pr_fmt
559 #define pr_fmt(fmt)     "" fmt
560 
md_clear_update_mitigation(void)561 static void __init md_clear_update_mitigation(void)
562 {
563 	if (cpu_mitigations_off())
564 		return;
565 
566 	if (!boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF))
567 		goto out;
568 
569 	/*
570 	 * X86_FEATURE_CLEAR_CPU_BUF is now enabled. Update MDS, TAA and MMIO
571 	 * Stale Data mitigation, if necessary.
572 	 */
573 	if (mds_mitigation == MDS_MITIGATION_OFF &&
574 	    boot_cpu_has_bug(X86_BUG_MDS)) {
575 		mds_mitigation = MDS_MITIGATION_FULL;
576 		mds_select_mitigation();
577 	}
578 	if (taa_mitigation == TAA_MITIGATION_OFF &&
579 	    boot_cpu_has_bug(X86_BUG_TAA)) {
580 		taa_mitigation = TAA_MITIGATION_VERW;
581 		taa_select_mitigation();
582 	}
583 	/*
584 	 * MMIO_MITIGATION_OFF is not checked here so that mmio_stale_data_clear
585 	 * gets updated correctly as per X86_FEATURE_CLEAR_CPU_BUF state.
586 	 */
587 	if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
588 		mmio_mitigation = MMIO_MITIGATION_VERW;
589 		mmio_select_mitigation();
590 	}
591 	if (rfds_mitigation == RFDS_MITIGATION_OFF &&
592 	    boot_cpu_has_bug(X86_BUG_RFDS)) {
593 		rfds_mitigation = RFDS_MITIGATION_VERW;
594 		rfds_select_mitigation();
595 	}
596 out:
597 	if (boot_cpu_has_bug(X86_BUG_MDS))
598 		pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
599 	if (boot_cpu_has_bug(X86_BUG_TAA))
600 		pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
601 	if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
602 		pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
603 	else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
604 		pr_info("MMIO Stale Data: Unknown: No mitigations\n");
605 	if (boot_cpu_has_bug(X86_BUG_RFDS))
606 		pr_info("Register File Data Sampling: %s\n", rfds_strings[rfds_mitigation]);
607 }
608 
md_clear_select_mitigation(void)609 static void __init md_clear_select_mitigation(void)
610 {
611 	mds_select_mitigation();
612 	taa_select_mitigation();
613 	mmio_select_mitigation();
614 	rfds_select_mitigation();
615 
616 	/*
617 	 * As these mitigations are inter-related and rely on VERW instruction
618 	 * to clear the microarchitural buffers, update and print their status
619 	 * after mitigation selection is done for each of these vulnerabilities.
620 	 */
621 	md_clear_update_mitigation();
622 }
623 
624 #undef pr_fmt
625 #define pr_fmt(fmt)	"SRBDS: " fmt
626 
627 enum srbds_mitigations {
628 	SRBDS_MITIGATION_OFF,
629 	SRBDS_MITIGATION_UCODE_NEEDED,
630 	SRBDS_MITIGATION_FULL,
631 	SRBDS_MITIGATION_TSX_OFF,
632 	SRBDS_MITIGATION_HYPERVISOR,
633 };
634 
635 static enum srbds_mitigations srbds_mitigation __ro_after_init =
636 	IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_FULL : SRBDS_MITIGATION_OFF;
637 
638 static const char * const srbds_strings[] = {
639 	[SRBDS_MITIGATION_OFF]		= "Vulnerable",
640 	[SRBDS_MITIGATION_UCODE_NEEDED]	= "Vulnerable: No microcode",
641 	[SRBDS_MITIGATION_FULL]		= "Mitigation: Microcode",
642 	[SRBDS_MITIGATION_TSX_OFF]	= "Mitigation: TSX disabled",
643 	[SRBDS_MITIGATION_HYPERVISOR]	= "Unknown: Dependent on hypervisor status",
644 };
645 
646 static bool srbds_off;
647 
update_srbds_msr(void)648 void update_srbds_msr(void)
649 {
650 	u64 mcu_ctrl;
651 
652 	if (!boot_cpu_has_bug(X86_BUG_SRBDS))
653 		return;
654 
655 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
656 		return;
657 
658 	if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
659 		return;
660 
661 	/*
662 	 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
663 	 * being disabled and it hasn't received the SRBDS MSR microcode.
664 	 */
665 	if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
666 		return;
667 
668 	rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
669 
670 	switch (srbds_mitigation) {
671 	case SRBDS_MITIGATION_OFF:
672 	case SRBDS_MITIGATION_TSX_OFF:
673 		mcu_ctrl |= RNGDS_MITG_DIS;
674 		break;
675 	case SRBDS_MITIGATION_FULL:
676 		mcu_ctrl &= ~RNGDS_MITG_DIS;
677 		break;
678 	default:
679 		break;
680 	}
681 
682 	wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
683 }
684 
srbds_select_mitigation(void)685 static void __init srbds_select_mitigation(void)
686 {
687 	if (!boot_cpu_has_bug(X86_BUG_SRBDS))
688 		return;
689 
690 	/*
691 	 * Check to see if this is one of the MDS_NO systems supporting TSX that
692 	 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
693 	 * by Processor MMIO Stale Data vulnerability.
694 	 */
695 	if ((x86_arch_cap_msr & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
696 	    !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
697 		srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
698 	else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
699 		srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
700 	else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
701 		srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
702 	else if (cpu_mitigations_off() || srbds_off)
703 		srbds_mitigation = SRBDS_MITIGATION_OFF;
704 
705 	update_srbds_msr();
706 	pr_info("%s\n", srbds_strings[srbds_mitigation]);
707 }
708 
srbds_parse_cmdline(char * str)709 static int __init srbds_parse_cmdline(char *str)
710 {
711 	if (!str)
712 		return -EINVAL;
713 
714 	if (!boot_cpu_has_bug(X86_BUG_SRBDS))
715 		return 0;
716 
717 	srbds_off = !strcmp(str, "off");
718 	return 0;
719 }
720 early_param("srbds", srbds_parse_cmdline);
721 
722 #undef pr_fmt
723 #define pr_fmt(fmt)     "L1D Flush : " fmt
724 
725 enum l1d_flush_mitigations {
726 	L1D_FLUSH_OFF = 0,
727 	L1D_FLUSH_ON,
728 };
729 
730 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
731 
l1d_flush_select_mitigation(void)732 static void __init l1d_flush_select_mitigation(void)
733 {
734 	if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
735 		return;
736 
737 	static_branch_enable(&switch_mm_cond_l1d_flush);
738 	pr_info("Conditional flush on switch_mm() enabled\n");
739 }
740 
l1d_flush_parse_cmdline(char * str)741 static int __init l1d_flush_parse_cmdline(char *str)
742 {
743 	if (!strcmp(str, "on"))
744 		l1d_flush_mitigation = L1D_FLUSH_ON;
745 
746 	return 0;
747 }
748 early_param("l1d_flush", l1d_flush_parse_cmdline);
749 
750 #undef pr_fmt
751 #define pr_fmt(fmt)	"GDS: " fmt
752 
753 enum gds_mitigations {
754 	GDS_MITIGATION_OFF,
755 	GDS_MITIGATION_UCODE_NEEDED,
756 	GDS_MITIGATION_FORCE,
757 	GDS_MITIGATION_FULL,
758 	GDS_MITIGATION_FULL_LOCKED,
759 	GDS_MITIGATION_HYPERVISOR,
760 };
761 
762 static enum gds_mitigations gds_mitigation __ro_after_init =
763 	IS_ENABLED(CONFIG_MITIGATION_GDS) ? GDS_MITIGATION_FULL : GDS_MITIGATION_OFF;
764 
765 static const char * const gds_strings[] = {
766 	[GDS_MITIGATION_OFF]		= "Vulnerable",
767 	[GDS_MITIGATION_UCODE_NEEDED]	= "Vulnerable: No microcode",
768 	[GDS_MITIGATION_FORCE]		= "Mitigation: AVX disabled, no microcode",
769 	[GDS_MITIGATION_FULL]		= "Mitigation: Microcode",
770 	[GDS_MITIGATION_FULL_LOCKED]	= "Mitigation: Microcode (locked)",
771 	[GDS_MITIGATION_HYPERVISOR]	= "Unknown: Dependent on hypervisor status",
772 };
773 
gds_ucode_mitigated(void)774 bool gds_ucode_mitigated(void)
775 {
776 	return (gds_mitigation == GDS_MITIGATION_FULL ||
777 		gds_mitigation == GDS_MITIGATION_FULL_LOCKED);
778 }
779 EXPORT_SYMBOL_GPL(gds_ucode_mitigated);
780 
update_gds_msr(void)781 void update_gds_msr(void)
782 {
783 	u64 mcu_ctrl_after;
784 	u64 mcu_ctrl;
785 
786 	switch (gds_mitigation) {
787 	case GDS_MITIGATION_OFF:
788 		rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
789 		mcu_ctrl |= GDS_MITG_DIS;
790 		break;
791 	case GDS_MITIGATION_FULL_LOCKED:
792 		/*
793 		 * The LOCKED state comes from the boot CPU. APs might not have
794 		 * the same state. Make sure the mitigation is enabled on all
795 		 * CPUs.
796 		 */
797 	case GDS_MITIGATION_FULL:
798 		rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
799 		mcu_ctrl &= ~GDS_MITG_DIS;
800 		break;
801 	case GDS_MITIGATION_FORCE:
802 	case GDS_MITIGATION_UCODE_NEEDED:
803 	case GDS_MITIGATION_HYPERVISOR:
804 		return;
805 	}
806 
807 	wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
808 
809 	/*
810 	 * Check to make sure that the WRMSR value was not ignored. Writes to
811 	 * GDS_MITG_DIS will be ignored if this processor is locked but the boot
812 	 * processor was not.
813 	 */
814 	rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after);
815 	WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after);
816 }
817 
gds_select_mitigation(void)818 static void __init gds_select_mitigation(void)
819 {
820 	u64 mcu_ctrl;
821 
822 	if (!boot_cpu_has_bug(X86_BUG_GDS))
823 		return;
824 
825 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
826 		gds_mitigation = GDS_MITIGATION_HYPERVISOR;
827 		goto out;
828 	}
829 
830 	if (cpu_mitigations_off())
831 		gds_mitigation = GDS_MITIGATION_OFF;
832 	/* Will verify below that mitigation _can_ be disabled */
833 
834 	/* No microcode */
835 	if (!(x86_arch_cap_msr & ARCH_CAP_GDS_CTRL)) {
836 		if (gds_mitigation == GDS_MITIGATION_FORCE) {
837 			/*
838 			 * This only needs to be done on the boot CPU so do it
839 			 * here rather than in update_gds_msr()
840 			 */
841 			setup_clear_cpu_cap(X86_FEATURE_AVX);
842 			pr_warn("Microcode update needed! Disabling AVX as mitigation.\n");
843 		} else {
844 			gds_mitigation = GDS_MITIGATION_UCODE_NEEDED;
845 		}
846 		goto out;
847 	}
848 
849 	/* Microcode has mitigation, use it */
850 	if (gds_mitigation == GDS_MITIGATION_FORCE)
851 		gds_mitigation = GDS_MITIGATION_FULL;
852 
853 	rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
854 	if (mcu_ctrl & GDS_MITG_LOCKED) {
855 		if (gds_mitigation == GDS_MITIGATION_OFF)
856 			pr_warn("Mitigation locked. Disable failed.\n");
857 
858 		/*
859 		 * The mitigation is selected from the boot CPU. All other CPUs
860 		 * _should_ have the same state. If the boot CPU isn't locked
861 		 * but others are then update_gds_msr() will WARN() of the state
862 		 * mismatch. If the boot CPU is locked update_gds_msr() will
863 		 * ensure the other CPUs have the mitigation enabled.
864 		 */
865 		gds_mitigation = GDS_MITIGATION_FULL_LOCKED;
866 	}
867 
868 	update_gds_msr();
869 out:
870 	pr_info("%s\n", gds_strings[gds_mitigation]);
871 }
872 
gds_parse_cmdline(char * str)873 static int __init gds_parse_cmdline(char *str)
874 {
875 	if (!str)
876 		return -EINVAL;
877 
878 	if (!boot_cpu_has_bug(X86_BUG_GDS))
879 		return 0;
880 
881 	if (!strcmp(str, "off"))
882 		gds_mitigation = GDS_MITIGATION_OFF;
883 	else if (!strcmp(str, "force"))
884 		gds_mitigation = GDS_MITIGATION_FORCE;
885 
886 	return 0;
887 }
888 early_param("gather_data_sampling", gds_parse_cmdline);
889 
890 #undef pr_fmt
891 #define pr_fmt(fmt)     "Spectre V1 : " fmt
892 
893 enum spectre_v1_mitigation {
894 	SPECTRE_V1_MITIGATION_NONE,
895 	SPECTRE_V1_MITIGATION_AUTO,
896 };
897 
898 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
899 	IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V1) ?
900 		SPECTRE_V1_MITIGATION_AUTO : SPECTRE_V1_MITIGATION_NONE;
901 
902 static const char * const spectre_v1_strings[] = {
903 	[SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
904 	[SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
905 };
906 
907 /*
908  * Does SMAP provide full mitigation against speculative kernel access to
909  * userspace?
910  */
smap_works_speculatively(void)911 static bool smap_works_speculatively(void)
912 {
913 	if (!boot_cpu_has(X86_FEATURE_SMAP))
914 		return false;
915 
916 	/*
917 	 * On CPUs which are vulnerable to Meltdown, SMAP does not
918 	 * prevent speculative access to user data in the L1 cache.
919 	 * Consider SMAP to be non-functional as a mitigation on these
920 	 * CPUs.
921 	 */
922 	if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
923 		return false;
924 
925 	return true;
926 }
927 
spectre_v1_select_mitigation(void)928 static void __init spectre_v1_select_mitigation(void)
929 {
930 	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
931 		spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
932 		return;
933 	}
934 
935 	if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
936 		/*
937 		 * With Spectre v1, a user can speculatively control either
938 		 * path of a conditional swapgs with a user-controlled GS
939 		 * value.  The mitigation is to add lfences to both code paths.
940 		 *
941 		 * If FSGSBASE is enabled, the user can put a kernel address in
942 		 * GS, in which case SMAP provides no protection.
943 		 *
944 		 * If FSGSBASE is disabled, the user can only put a user space
945 		 * address in GS.  That makes an attack harder, but still
946 		 * possible if there's no SMAP protection.
947 		 */
948 		if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
949 		    !smap_works_speculatively()) {
950 			/*
951 			 * Mitigation can be provided from SWAPGS itself or
952 			 * PTI as the CR3 write in the Meltdown mitigation
953 			 * is serializing.
954 			 *
955 			 * If neither is there, mitigate with an LFENCE to
956 			 * stop speculation through swapgs.
957 			 */
958 			if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
959 			    !boot_cpu_has(X86_FEATURE_PTI))
960 				setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
961 
962 			/*
963 			 * Enable lfences in the kernel entry (non-swapgs)
964 			 * paths, to prevent user entry from speculatively
965 			 * skipping swapgs.
966 			 */
967 			setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
968 		}
969 	}
970 
971 	pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
972 }
973 
nospectre_v1_cmdline(char * str)974 static int __init nospectre_v1_cmdline(char *str)
975 {
976 	spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
977 	return 0;
978 }
979 early_param("nospectre_v1", nospectre_v1_cmdline);
980 
981 enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = SPECTRE_V2_NONE;
982 
983 #undef pr_fmt
984 #define pr_fmt(fmt)     "RETBleed: " fmt
985 
986 enum retbleed_mitigation {
987 	RETBLEED_MITIGATION_NONE,
988 	RETBLEED_MITIGATION_UNRET,
989 	RETBLEED_MITIGATION_IBPB,
990 	RETBLEED_MITIGATION_IBRS,
991 	RETBLEED_MITIGATION_EIBRS,
992 	RETBLEED_MITIGATION_STUFF,
993 };
994 
995 enum retbleed_mitigation_cmd {
996 	RETBLEED_CMD_OFF,
997 	RETBLEED_CMD_AUTO,
998 	RETBLEED_CMD_UNRET,
999 	RETBLEED_CMD_IBPB,
1000 	RETBLEED_CMD_STUFF,
1001 };
1002 
1003 static const char * const retbleed_strings[] = {
1004 	[RETBLEED_MITIGATION_NONE]	= "Vulnerable",
1005 	[RETBLEED_MITIGATION_UNRET]	= "Mitigation: untrained return thunk",
1006 	[RETBLEED_MITIGATION_IBPB]	= "Mitigation: IBPB",
1007 	[RETBLEED_MITIGATION_IBRS]	= "Mitigation: IBRS",
1008 	[RETBLEED_MITIGATION_EIBRS]	= "Mitigation: Enhanced IBRS",
1009 	[RETBLEED_MITIGATION_STUFF]	= "Mitigation: Stuffing",
1010 };
1011 
1012 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
1013 	RETBLEED_MITIGATION_NONE;
1014 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
1015 	IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_CMD_AUTO : RETBLEED_CMD_OFF;
1016 
1017 static int __ro_after_init retbleed_nosmt = false;
1018 
retbleed_parse_cmdline(char * str)1019 static int __init retbleed_parse_cmdline(char *str)
1020 {
1021 	if (!str)
1022 		return -EINVAL;
1023 
1024 	while (str) {
1025 		char *next = strchr(str, ',');
1026 		if (next) {
1027 			*next = 0;
1028 			next++;
1029 		}
1030 
1031 		if (!strcmp(str, "off")) {
1032 			retbleed_cmd = RETBLEED_CMD_OFF;
1033 		} else if (!strcmp(str, "auto")) {
1034 			retbleed_cmd = RETBLEED_CMD_AUTO;
1035 		} else if (!strcmp(str, "unret")) {
1036 			retbleed_cmd = RETBLEED_CMD_UNRET;
1037 		} else if (!strcmp(str, "ibpb")) {
1038 			retbleed_cmd = RETBLEED_CMD_IBPB;
1039 		} else if (!strcmp(str, "stuff")) {
1040 			retbleed_cmd = RETBLEED_CMD_STUFF;
1041 		} else if (!strcmp(str, "nosmt")) {
1042 			retbleed_nosmt = true;
1043 		} else if (!strcmp(str, "force")) {
1044 			setup_force_cpu_bug(X86_BUG_RETBLEED);
1045 		} else {
1046 			pr_err("Ignoring unknown retbleed option (%s).", str);
1047 		}
1048 
1049 		str = next;
1050 	}
1051 
1052 	return 0;
1053 }
1054 early_param("retbleed", retbleed_parse_cmdline);
1055 
1056 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
1057 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
1058 
retbleed_select_mitigation(void)1059 static void __init retbleed_select_mitigation(void)
1060 {
1061 	bool mitigate_smt = false;
1062 
1063 	if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
1064 		return;
1065 
1066 	switch (retbleed_cmd) {
1067 	case RETBLEED_CMD_OFF:
1068 		return;
1069 
1070 	case RETBLEED_CMD_UNRET:
1071 		if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) {
1072 			retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
1073 		} else {
1074 			pr_err("WARNING: kernel not compiled with MITIGATION_UNRET_ENTRY.\n");
1075 			goto do_cmd_auto;
1076 		}
1077 		break;
1078 
1079 	case RETBLEED_CMD_IBPB:
1080 		if (!boot_cpu_has(X86_FEATURE_IBPB)) {
1081 			pr_err("WARNING: CPU does not support IBPB.\n");
1082 			goto do_cmd_auto;
1083 		} else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) {
1084 			retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
1085 		} else {
1086 			pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n");
1087 			goto do_cmd_auto;
1088 		}
1089 		break;
1090 
1091 	case RETBLEED_CMD_STUFF:
1092 		if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) &&
1093 		    spectre_v2_enabled == SPECTRE_V2_RETPOLINE) {
1094 			retbleed_mitigation = RETBLEED_MITIGATION_STUFF;
1095 
1096 		} else {
1097 			if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING))
1098 				pr_err("WARNING: retbleed=stuff depends on spectre_v2=retpoline\n");
1099 			else
1100 				pr_err("WARNING: kernel not compiled with MITIGATION_CALL_DEPTH_TRACKING.\n");
1101 
1102 			goto do_cmd_auto;
1103 		}
1104 		break;
1105 
1106 do_cmd_auto:
1107 	case RETBLEED_CMD_AUTO:
1108 		if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1109 		    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
1110 			if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY))
1111 				retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
1112 			else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY) &&
1113 				 boot_cpu_has(X86_FEATURE_IBPB))
1114 				retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
1115 		}
1116 
1117 		/*
1118 		 * The Intel mitigation (IBRS or eIBRS) was already selected in
1119 		 * spectre_v2_select_mitigation().  'retbleed_mitigation' will
1120 		 * be set accordingly below.
1121 		 */
1122 
1123 		break;
1124 	}
1125 
1126 	switch (retbleed_mitigation) {
1127 	case RETBLEED_MITIGATION_UNRET:
1128 		setup_force_cpu_cap(X86_FEATURE_RETHUNK);
1129 		setup_force_cpu_cap(X86_FEATURE_UNRET);
1130 
1131 		set_return_thunk(retbleed_return_thunk);
1132 
1133 		if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
1134 		    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
1135 			pr_err(RETBLEED_UNTRAIN_MSG);
1136 
1137 		mitigate_smt = true;
1138 		break;
1139 
1140 	case RETBLEED_MITIGATION_IBPB:
1141 		setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
1142 		setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT);
1143 		mitigate_smt = true;
1144 
1145 		/*
1146 		 * IBPB on entry already obviates the need for
1147 		 * software-based untraining so clear those in case some
1148 		 * other mitigation like SRSO has selected them.
1149 		 */
1150 		setup_clear_cpu_cap(X86_FEATURE_UNRET);
1151 		setup_clear_cpu_cap(X86_FEATURE_RETHUNK);
1152 
1153 		/*
1154 		 * There is no need for RSB filling: write_ibpb() ensures
1155 		 * all predictions, including the RSB, are invalidated,
1156 		 * regardless of IBPB implementation.
1157 		 */
1158 		setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1159 
1160 		break;
1161 
1162 	case RETBLEED_MITIGATION_STUFF:
1163 		setup_force_cpu_cap(X86_FEATURE_RETHUNK);
1164 		setup_force_cpu_cap(X86_FEATURE_CALL_DEPTH);
1165 
1166 		set_return_thunk(call_depth_return_thunk);
1167 		break;
1168 
1169 	default:
1170 		break;
1171 	}
1172 
1173 	if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
1174 	    (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
1175 		cpu_smt_disable(false);
1176 
1177 	/*
1178 	 * Let IBRS trump all on Intel without affecting the effects of the
1179 	 * retbleed= cmdline option except for call depth based stuffing
1180 	 */
1181 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1182 		switch (spectre_v2_enabled) {
1183 		case SPECTRE_V2_IBRS:
1184 			retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
1185 			break;
1186 		case SPECTRE_V2_EIBRS:
1187 		case SPECTRE_V2_EIBRS_RETPOLINE:
1188 		case SPECTRE_V2_EIBRS_LFENCE:
1189 			retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
1190 			break;
1191 		default:
1192 			if (retbleed_mitigation != RETBLEED_MITIGATION_STUFF)
1193 				pr_err(RETBLEED_INTEL_MSG);
1194 		}
1195 	}
1196 
1197 	pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
1198 }
1199 
1200 #undef pr_fmt
1201 #define pr_fmt(fmt)     "ITS: " fmt
1202 
1203 enum its_mitigation_cmd {
1204 	ITS_CMD_OFF,
1205 	ITS_CMD_ON,
1206 	ITS_CMD_VMEXIT,
1207 	ITS_CMD_RSB_STUFF,
1208 };
1209 
1210 enum its_mitigation {
1211 	ITS_MITIGATION_OFF,
1212 	ITS_MITIGATION_VMEXIT_ONLY,
1213 	ITS_MITIGATION_ALIGNED_THUNKS,
1214 	ITS_MITIGATION_RETPOLINE_STUFF,
1215 };
1216 
1217 static const char * const its_strings[] = {
1218 	[ITS_MITIGATION_OFF]			= "Vulnerable",
1219 	[ITS_MITIGATION_VMEXIT_ONLY]		= "Mitigation: Vulnerable, KVM: Not affected",
1220 	[ITS_MITIGATION_ALIGNED_THUNKS]		= "Mitigation: Aligned branch/return thunks",
1221 	[ITS_MITIGATION_RETPOLINE_STUFF]	= "Mitigation: Retpolines, Stuffing RSB",
1222 };
1223 
1224 static enum its_mitigation its_mitigation __ro_after_init = ITS_MITIGATION_ALIGNED_THUNKS;
1225 
1226 static enum its_mitigation_cmd its_cmd __ro_after_init =
1227 	IS_ENABLED(CONFIG_MITIGATION_ITS) ? ITS_CMD_ON : ITS_CMD_OFF;
1228 
its_parse_cmdline(char * str)1229 static int __init its_parse_cmdline(char *str)
1230 {
1231 	if (!str)
1232 		return -EINVAL;
1233 
1234 	if (!IS_ENABLED(CONFIG_MITIGATION_ITS)) {
1235 		pr_err("Mitigation disabled at compile time, ignoring option (%s)", str);
1236 		return 0;
1237 	}
1238 
1239 	if (!strcmp(str, "off")) {
1240 		its_cmd = ITS_CMD_OFF;
1241 	} else if (!strcmp(str, "on")) {
1242 		its_cmd = ITS_CMD_ON;
1243 	} else if (!strcmp(str, "force")) {
1244 		its_cmd = ITS_CMD_ON;
1245 		setup_force_cpu_bug(X86_BUG_ITS);
1246 	} else if (!strcmp(str, "vmexit")) {
1247 		its_cmd = ITS_CMD_VMEXIT;
1248 	} else if (!strcmp(str, "stuff")) {
1249 		its_cmd = ITS_CMD_RSB_STUFF;
1250 	} else {
1251 		pr_err("Ignoring unknown indirect_target_selection option (%s).", str);
1252 	}
1253 
1254 	return 0;
1255 }
1256 early_param("indirect_target_selection", its_parse_cmdline);
1257 
its_select_mitigation(void)1258 static void __init its_select_mitigation(void)
1259 {
1260 	enum its_mitigation_cmd cmd = its_cmd;
1261 
1262 	if (!boot_cpu_has_bug(X86_BUG_ITS) || cpu_mitigations_off()) {
1263 		its_mitigation = ITS_MITIGATION_OFF;
1264 		return;
1265 	}
1266 
1267 	/* Retpoline+CDT mitigates ITS, bail out */
1268 	if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
1269 	    boot_cpu_has(X86_FEATURE_CALL_DEPTH)) {
1270 		its_mitigation = ITS_MITIGATION_RETPOLINE_STUFF;
1271 		goto out;
1272 	}
1273 
1274 	/* Exit early to avoid irrelevant warnings */
1275 	if (cmd == ITS_CMD_OFF) {
1276 		its_mitigation = ITS_MITIGATION_OFF;
1277 		goto out;
1278 	}
1279 	if (spectre_v2_enabled == SPECTRE_V2_NONE) {
1280 		pr_err("WARNING: Spectre-v2 mitigation is off, disabling ITS\n");
1281 		its_mitigation = ITS_MITIGATION_OFF;
1282 		goto out;
1283 	}
1284 	if (!IS_ENABLED(CONFIG_MITIGATION_RETPOLINE) ||
1285 	    !IS_ENABLED(CONFIG_MITIGATION_RETHUNK)) {
1286 		pr_err("WARNING: ITS mitigation depends on retpoline and rethunk support\n");
1287 		its_mitigation = ITS_MITIGATION_OFF;
1288 		goto out;
1289 	}
1290 	if (IS_ENABLED(CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B)) {
1291 		pr_err("WARNING: ITS mitigation is not compatible with CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B\n");
1292 		its_mitigation = ITS_MITIGATION_OFF;
1293 		goto out;
1294 	}
1295 	if (boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE)) {
1296 		pr_err("WARNING: ITS mitigation is not compatible with lfence mitigation\n");
1297 		its_mitigation = ITS_MITIGATION_OFF;
1298 		goto out;
1299 	}
1300 
1301 	if (cmd == ITS_CMD_RSB_STUFF &&
1302 	    (!boot_cpu_has(X86_FEATURE_RETPOLINE) || !IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING))) {
1303 		pr_err("RSB stuff mitigation not supported, using default\n");
1304 		cmd = ITS_CMD_ON;
1305 	}
1306 
1307 	switch (cmd) {
1308 	case ITS_CMD_OFF:
1309 		its_mitigation = ITS_MITIGATION_OFF;
1310 		break;
1311 	case ITS_CMD_VMEXIT:
1312 		if (boot_cpu_has_bug(X86_BUG_ITS_NATIVE_ONLY)) {
1313 			its_mitigation = ITS_MITIGATION_VMEXIT_ONLY;
1314 			goto out;
1315 		}
1316 		fallthrough;
1317 	case ITS_CMD_ON:
1318 		its_mitigation = ITS_MITIGATION_ALIGNED_THUNKS;
1319 		if (!boot_cpu_has(X86_FEATURE_RETPOLINE))
1320 			setup_force_cpu_cap(X86_FEATURE_INDIRECT_THUNK_ITS);
1321 		setup_force_cpu_cap(X86_FEATURE_RETHUNK);
1322 		set_return_thunk(its_return_thunk);
1323 		break;
1324 	case ITS_CMD_RSB_STUFF:
1325 		its_mitigation = ITS_MITIGATION_RETPOLINE_STUFF;
1326 		setup_force_cpu_cap(X86_FEATURE_RETHUNK);
1327 		setup_force_cpu_cap(X86_FEATURE_CALL_DEPTH);
1328 		set_return_thunk(call_depth_return_thunk);
1329 		if (retbleed_mitigation == RETBLEED_MITIGATION_NONE) {
1330 			retbleed_mitigation = RETBLEED_MITIGATION_STUFF;
1331 			pr_info("Retbleed mitigation updated to stuffing\n");
1332 		}
1333 		break;
1334 	}
1335 out:
1336 	pr_info("%s\n", its_strings[its_mitigation]);
1337 }
1338 
1339 #undef pr_fmt
1340 #define pr_fmt(fmt)     "Spectre V2 : " fmt
1341 
1342 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
1343 	SPECTRE_V2_USER_NONE;
1344 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
1345 	SPECTRE_V2_USER_NONE;
1346 
1347 #ifdef CONFIG_MITIGATION_RETPOLINE
1348 static bool spectre_v2_bad_module;
1349 
retpoline_module_ok(bool has_retpoline)1350 bool retpoline_module_ok(bool has_retpoline)
1351 {
1352 	if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
1353 		return true;
1354 
1355 	pr_err("System may be vulnerable to spectre v2\n");
1356 	spectre_v2_bad_module = true;
1357 	return false;
1358 }
1359 
spectre_v2_module_string(void)1360 static inline const char *spectre_v2_module_string(void)
1361 {
1362 	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
1363 }
1364 #else
spectre_v2_module_string(void)1365 static inline const char *spectre_v2_module_string(void) { return ""; }
1366 #endif
1367 
1368 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
1369 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
1370 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
1371 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
1372 
1373 #ifdef CONFIG_BPF_SYSCALL
unpriv_ebpf_notify(int new_state)1374 void unpriv_ebpf_notify(int new_state)
1375 {
1376 	if (new_state)
1377 		return;
1378 
1379 	/* Unprivileged eBPF is enabled */
1380 
1381 	switch (spectre_v2_enabled) {
1382 	case SPECTRE_V2_EIBRS:
1383 		pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1384 		break;
1385 	case SPECTRE_V2_EIBRS_LFENCE:
1386 		if (sched_smt_active())
1387 			pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1388 		break;
1389 	default:
1390 		break;
1391 	}
1392 }
1393 #endif
1394 
match_option(const char * arg,int arglen,const char * opt)1395 static inline bool match_option(const char *arg, int arglen, const char *opt)
1396 {
1397 	int len = strlen(opt);
1398 
1399 	return len == arglen && !strncmp(arg, opt, len);
1400 }
1401 
1402 /* The kernel command line selection for spectre v2 */
1403 enum spectre_v2_mitigation_cmd {
1404 	SPECTRE_V2_CMD_NONE,
1405 	SPECTRE_V2_CMD_AUTO,
1406 	SPECTRE_V2_CMD_FORCE,
1407 	SPECTRE_V2_CMD_RETPOLINE,
1408 	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1409 	SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1410 	SPECTRE_V2_CMD_EIBRS,
1411 	SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1412 	SPECTRE_V2_CMD_EIBRS_LFENCE,
1413 	SPECTRE_V2_CMD_IBRS,
1414 };
1415 
1416 enum spectre_v2_user_cmd {
1417 	SPECTRE_V2_USER_CMD_NONE,
1418 	SPECTRE_V2_USER_CMD_AUTO,
1419 	SPECTRE_V2_USER_CMD_FORCE,
1420 	SPECTRE_V2_USER_CMD_PRCTL,
1421 	SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1422 	SPECTRE_V2_USER_CMD_SECCOMP,
1423 	SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1424 };
1425 
1426 static const char * const spectre_v2_user_strings[] = {
1427 	[SPECTRE_V2_USER_NONE]			= "User space: Vulnerable",
1428 	[SPECTRE_V2_USER_STRICT]		= "User space: Mitigation: STIBP protection",
1429 	[SPECTRE_V2_USER_STRICT_PREFERRED]	= "User space: Mitigation: STIBP always-on protection",
1430 	[SPECTRE_V2_USER_PRCTL]			= "User space: Mitigation: STIBP via prctl",
1431 	[SPECTRE_V2_USER_SECCOMP]		= "User space: Mitigation: STIBP via seccomp and prctl",
1432 };
1433 
1434 static const struct {
1435 	const char			*option;
1436 	enum spectre_v2_user_cmd	cmd;
1437 	bool				secure;
1438 } v2_user_options[] __initconst = {
1439 	{ "auto",		SPECTRE_V2_USER_CMD_AUTO,		false },
1440 	{ "off",		SPECTRE_V2_USER_CMD_NONE,		false },
1441 	{ "on",			SPECTRE_V2_USER_CMD_FORCE,		true  },
1442 	{ "prctl",		SPECTRE_V2_USER_CMD_PRCTL,		false },
1443 	{ "prctl,ibpb",		SPECTRE_V2_USER_CMD_PRCTL_IBPB,		false },
1444 	{ "seccomp",		SPECTRE_V2_USER_CMD_SECCOMP,		false },
1445 	{ "seccomp,ibpb",	SPECTRE_V2_USER_CMD_SECCOMP_IBPB,	false },
1446 };
1447 
spec_v2_user_print_cond(const char * reason,bool secure)1448 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1449 {
1450 	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1451 		pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1452 }
1453 
1454 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1455 
1456 static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(void)1457 spectre_v2_parse_user_cmdline(void)
1458 {
1459 	enum spectre_v2_user_cmd mode;
1460 	char arg[20];
1461 	int ret, i;
1462 
1463 	mode = IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ?
1464 		SPECTRE_V2_USER_CMD_AUTO : SPECTRE_V2_USER_CMD_NONE;
1465 
1466 	switch (spectre_v2_cmd) {
1467 	case SPECTRE_V2_CMD_NONE:
1468 		return SPECTRE_V2_USER_CMD_NONE;
1469 	case SPECTRE_V2_CMD_FORCE:
1470 		return SPECTRE_V2_USER_CMD_FORCE;
1471 	default:
1472 		break;
1473 	}
1474 
1475 	ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1476 				  arg, sizeof(arg));
1477 	if (ret < 0)
1478 		return mode;
1479 
1480 	for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1481 		if (match_option(arg, ret, v2_user_options[i].option)) {
1482 			spec_v2_user_print_cond(v2_user_options[i].option,
1483 						v2_user_options[i].secure);
1484 			return v2_user_options[i].cmd;
1485 		}
1486 	}
1487 
1488 	pr_err("Unknown user space protection option (%s). Switching to default\n", arg);
1489 	return mode;
1490 }
1491 
spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)1492 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1493 {
1494 	return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
1495 }
1496 
1497 static void __init
spectre_v2_user_select_mitigation(void)1498 spectre_v2_user_select_mitigation(void)
1499 {
1500 	enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1501 	enum spectre_v2_user_cmd cmd;
1502 
1503 	if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1504 		return;
1505 
1506 	cmd = spectre_v2_parse_user_cmdline();
1507 	switch (cmd) {
1508 	case SPECTRE_V2_USER_CMD_NONE:
1509 		goto set_mode;
1510 	case SPECTRE_V2_USER_CMD_FORCE:
1511 		mode = SPECTRE_V2_USER_STRICT;
1512 		break;
1513 	case SPECTRE_V2_USER_CMD_AUTO:
1514 	case SPECTRE_V2_USER_CMD_PRCTL:
1515 	case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1516 		mode = SPECTRE_V2_USER_PRCTL;
1517 		break;
1518 	case SPECTRE_V2_USER_CMD_SECCOMP:
1519 	case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1520 		if (IS_ENABLED(CONFIG_SECCOMP))
1521 			mode = SPECTRE_V2_USER_SECCOMP;
1522 		else
1523 			mode = SPECTRE_V2_USER_PRCTL;
1524 		break;
1525 	}
1526 
1527 	/* Initialize Indirect Branch Prediction Barrier */
1528 	if (boot_cpu_has(X86_FEATURE_IBPB)) {
1529 		static_branch_enable(&switch_vcpu_ibpb);
1530 
1531 		spectre_v2_user_ibpb = mode;
1532 		switch (cmd) {
1533 		case SPECTRE_V2_USER_CMD_NONE:
1534 			break;
1535 		case SPECTRE_V2_USER_CMD_FORCE:
1536 		case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1537 		case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1538 			static_branch_enable(&switch_mm_always_ibpb);
1539 			spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1540 			break;
1541 		case SPECTRE_V2_USER_CMD_PRCTL:
1542 		case SPECTRE_V2_USER_CMD_AUTO:
1543 		case SPECTRE_V2_USER_CMD_SECCOMP:
1544 			static_branch_enable(&switch_mm_cond_ibpb);
1545 			break;
1546 		}
1547 
1548 		pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1549 			static_key_enabled(&switch_mm_always_ibpb) ?
1550 			"always-on" : "conditional");
1551 	}
1552 
1553 	/*
1554 	 * If no STIBP, Intel enhanced IBRS is enabled, or SMT impossible, STIBP
1555 	 * is not required.
1556 	 *
1557 	 * Intel's Enhanced IBRS also protects against cross-thread branch target
1558 	 * injection in user-mode as the IBRS bit remains always set which
1559 	 * implicitly enables cross-thread protections.  However, in legacy IBRS
1560 	 * mode, the IBRS bit is set only on kernel entry and cleared on return
1561 	 * to userspace.  AMD Automatic IBRS also does not protect userspace.
1562 	 * These modes therefore disable the implicit cross-thread protection,
1563 	 * so allow for STIBP to be selected in those cases.
1564 	 */
1565 	if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1566 	    !cpu_smt_possible() ||
1567 	    (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
1568 	     !boot_cpu_has(X86_FEATURE_AUTOIBRS)))
1569 		return;
1570 
1571 	/*
1572 	 * At this point, an STIBP mode other than "off" has been set.
1573 	 * If STIBP support is not being forced, check if STIBP always-on
1574 	 * is preferred.
1575 	 */
1576 	if (mode != SPECTRE_V2_USER_STRICT &&
1577 	    boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1578 		mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1579 
1580 	if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1581 	    retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1582 		if (mode != SPECTRE_V2_USER_STRICT &&
1583 		    mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1584 			pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1585 		mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1586 	}
1587 
1588 	spectre_v2_user_stibp = mode;
1589 
1590 set_mode:
1591 	pr_info("%s\n", spectre_v2_user_strings[mode]);
1592 }
1593 
1594 static const char * const spectre_v2_strings[] = {
1595 	[SPECTRE_V2_NONE]			= "Vulnerable",
1596 	[SPECTRE_V2_RETPOLINE]			= "Mitigation: Retpolines",
1597 	[SPECTRE_V2_LFENCE]			= "Mitigation: LFENCE",
1598 	[SPECTRE_V2_EIBRS]			= "Mitigation: Enhanced / Automatic IBRS",
1599 	[SPECTRE_V2_EIBRS_LFENCE]		= "Mitigation: Enhanced / Automatic IBRS + LFENCE",
1600 	[SPECTRE_V2_EIBRS_RETPOLINE]		= "Mitigation: Enhanced / Automatic IBRS + Retpolines",
1601 	[SPECTRE_V2_IBRS]			= "Mitigation: IBRS",
1602 };
1603 
1604 static const struct {
1605 	const char *option;
1606 	enum spectre_v2_mitigation_cmd cmd;
1607 	bool secure;
1608 } mitigation_options[] __initconst = {
1609 	{ "off",		SPECTRE_V2_CMD_NONE,		  false },
1610 	{ "on",			SPECTRE_V2_CMD_FORCE,		  true  },
1611 	{ "retpoline",		SPECTRE_V2_CMD_RETPOLINE,	  false },
1612 	{ "retpoline,amd",	SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1613 	{ "retpoline,lfence",	SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1614 	{ "retpoline,generic",	SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1615 	{ "eibrs",		SPECTRE_V2_CMD_EIBRS,		  false },
1616 	{ "eibrs,lfence",	SPECTRE_V2_CMD_EIBRS_LFENCE,	  false },
1617 	{ "eibrs,retpoline",	SPECTRE_V2_CMD_EIBRS_RETPOLINE,	  false },
1618 	{ "auto",		SPECTRE_V2_CMD_AUTO,		  false },
1619 	{ "ibrs",		SPECTRE_V2_CMD_IBRS,              false },
1620 };
1621 
spec_v2_print_cond(const char * reason,bool secure)1622 static void __init spec_v2_print_cond(const char *reason, bool secure)
1623 {
1624 	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1625 		pr_info("%s selected on command line.\n", reason);
1626 }
1627 
spectre_v2_parse_cmdline(void)1628 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1629 {
1630 	enum spectre_v2_mitigation_cmd cmd;
1631 	char arg[20];
1632 	int ret, i;
1633 
1634 	cmd = IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ?  SPECTRE_V2_CMD_AUTO : SPECTRE_V2_CMD_NONE;
1635 	if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1636 	    cpu_mitigations_off())
1637 		return SPECTRE_V2_CMD_NONE;
1638 
1639 	ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1640 	if (ret < 0)
1641 		return cmd;
1642 
1643 	for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1644 		if (!match_option(arg, ret, mitigation_options[i].option))
1645 			continue;
1646 		cmd = mitigation_options[i].cmd;
1647 		break;
1648 	}
1649 
1650 	if (i >= ARRAY_SIZE(mitigation_options)) {
1651 		pr_err("unknown option (%s). Switching to default mode\n", arg);
1652 		return cmd;
1653 	}
1654 
1655 	if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1656 	     cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1657 	     cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1658 	     cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1659 	     cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1660 	    !IS_ENABLED(CONFIG_MITIGATION_RETPOLINE)) {
1661 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1662 		       mitigation_options[i].option);
1663 		return SPECTRE_V2_CMD_AUTO;
1664 	}
1665 
1666 	if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1667 	     cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1668 	     cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1669 	    !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1670 		pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n",
1671 		       mitigation_options[i].option);
1672 		return SPECTRE_V2_CMD_AUTO;
1673 	}
1674 
1675 	if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1676 	     cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1677 	    !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1678 		pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1679 		       mitigation_options[i].option);
1680 		return SPECTRE_V2_CMD_AUTO;
1681 	}
1682 
1683 	if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY)) {
1684 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1685 		       mitigation_options[i].option);
1686 		return SPECTRE_V2_CMD_AUTO;
1687 	}
1688 
1689 	if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1690 		pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1691 		       mitigation_options[i].option);
1692 		return SPECTRE_V2_CMD_AUTO;
1693 	}
1694 
1695 	if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1696 		pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1697 		       mitigation_options[i].option);
1698 		return SPECTRE_V2_CMD_AUTO;
1699 	}
1700 
1701 	if (cmd == SPECTRE_V2_CMD_IBRS && cpu_feature_enabled(X86_FEATURE_XENPV)) {
1702 		pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1703 		       mitigation_options[i].option);
1704 		return SPECTRE_V2_CMD_AUTO;
1705 	}
1706 
1707 	spec_v2_print_cond(mitigation_options[i].option,
1708 			   mitigation_options[i].secure);
1709 	return cmd;
1710 }
1711 
spectre_v2_select_retpoline(void)1712 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1713 {
1714 	if (!IS_ENABLED(CONFIG_MITIGATION_RETPOLINE)) {
1715 		pr_err("Kernel not compiled with retpoline; no mitigation available!");
1716 		return SPECTRE_V2_NONE;
1717 	}
1718 
1719 	return SPECTRE_V2_RETPOLINE;
1720 }
1721 
1722 static bool __ro_after_init rrsba_disabled;
1723 
1724 /* Disable in-kernel use of non-RSB RET predictors */
spec_ctrl_disable_kernel_rrsba(void)1725 static void __init spec_ctrl_disable_kernel_rrsba(void)
1726 {
1727 	if (rrsba_disabled)
1728 		return;
1729 
1730 	if (!(x86_arch_cap_msr & ARCH_CAP_RRSBA)) {
1731 		rrsba_disabled = true;
1732 		return;
1733 	}
1734 
1735 	if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1736 		return;
1737 
1738 	x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1739 	update_spec_ctrl(x86_spec_ctrl_base);
1740 	rrsba_disabled = true;
1741 }
1742 
spectre_v2_select_rsb_mitigation(enum spectre_v2_mitigation mode)1743 static void __init spectre_v2_select_rsb_mitigation(enum spectre_v2_mitigation mode)
1744 {
1745 	/*
1746 	 * WARNING! There are many subtleties to consider when changing *any*
1747 	 * code related to RSB-related mitigations.  Before doing so, carefully
1748 	 * read the following document, and update if necessary:
1749 	 *
1750 	 *   Documentation/admin-guide/hw-vuln/rsb.rst
1751 	 *
1752 	 * In an overly simplified nutshell:
1753 	 *
1754 	 *   - User->user RSB attacks are conditionally mitigated during
1755 	 *     context switches by cond_mitigation -> write_ibpb().
1756 	 *
1757 	 *   - User->kernel and guest->host attacks are mitigated by eIBRS or
1758 	 *     RSB filling.
1759 	 *
1760 	 *     Though, depending on config, note that other alternative
1761 	 *     mitigations may end up getting used instead, e.g., IBPB on
1762 	 *     entry/vmexit, call depth tracking, or return thunks.
1763 	 */
1764 
1765 	switch (mode) {
1766 	case SPECTRE_V2_NONE:
1767 		break;
1768 
1769 	case SPECTRE_V2_EIBRS:
1770 	case SPECTRE_V2_EIBRS_LFENCE:
1771 	case SPECTRE_V2_EIBRS_RETPOLINE:
1772 		if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1773 			pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1774 			setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1775 		}
1776 		break;
1777 
1778 	case SPECTRE_V2_RETPOLINE:
1779 	case SPECTRE_V2_LFENCE:
1780 	case SPECTRE_V2_IBRS:
1781 		pr_info("Spectre v2 / SpectreRSB: Filling RSB on context switch and VMEXIT\n");
1782 		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1783 		setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1784 		break;
1785 
1786 	default:
1787 		pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation\n");
1788 		dump_stack();
1789 		break;
1790 	}
1791 }
1792 
1793 /*
1794  * Set BHI_DIS_S to prevent indirect branches in kernel to be influenced by
1795  * branch history in userspace. Not needed if BHI_NO is set.
1796  */
spec_ctrl_bhi_dis(void)1797 static bool __init spec_ctrl_bhi_dis(void)
1798 {
1799 	if (!boot_cpu_has(X86_FEATURE_BHI_CTRL))
1800 		return false;
1801 
1802 	x86_spec_ctrl_base |= SPEC_CTRL_BHI_DIS_S;
1803 	update_spec_ctrl(x86_spec_ctrl_base);
1804 	setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_HW);
1805 
1806 	return true;
1807 }
1808 
1809 enum bhi_mitigations {
1810 	BHI_MITIGATION_OFF,
1811 	BHI_MITIGATION_ON,
1812 	BHI_MITIGATION_VMEXIT_ONLY,
1813 };
1814 
1815 static enum bhi_mitigations bhi_mitigation __ro_after_init =
1816 	IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? BHI_MITIGATION_ON : BHI_MITIGATION_OFF;
1817 
spectre_bhi_parse_cmdline(char * str)1818 static int __init spectre_bhi_parse_cmdline(char *str)
1819 {
1820 	if (!str)
1821 		return -EINVAL;
1822 
1823 	if (!strcmp(str, "off"))
1824 		bhi_mitigation = BHI_MITIGATION_OFF;
1825 	else if (!strcmp(str, "on"))
1826 		bhi_mitigation = BHI_MITIGATION_ON;
1827 	else if (!strcmp(str, "vmexit"))
1828 		bhi_mitigation = BHI_MITIGATION_VMEXIT_ONLY;
1829 	else
1830 		pr_err("Ignoring unknown spectre_bhi option (%s)", str);
1831 
1832 	return 0;
1833 }
1834 early_param("spectre_bhi", spectre_bhi_parse_cmdline);
1835 
bhi_select_mitigation(void)1836 static void __init bhi_select_mitigation(void)
1837 {
1838 	if (bhi_mitigation == BHI_MITIGATION_OFF)
1839 		return;
1840 
1841 	/* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */
1842 	if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
1843 	    !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE)) {
1844 		spec_ctrl_disable_kernel_rrsba();
1845 		if (rrsba_disabled)
1846 			return;
1847 	}
1848 
1849 	if (!IS_ENABLED(CONFIG_X86_64))
1850 		return;
1851 
1852 	/* Mitigate in hardware if supported */
1853 	if (spec_ctrl_bhi_dis())
1854 		return;
1855 
1856 	if (bhi_mitigation == BHI_MITIGATION_VMEXIT_ONLY) {
1857 		pr_info("Spectre BHI mitigation: SW BHB clearing on VM exit only\n");
1858 		setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT);
1859 		return;
1860 	}
1861 
1862 	pr_info("Spectre BHI mitigation: SW BHB clearing on syscall and VM exit\n");
1863 	setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP);
1864 	setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT);
1865 }
1866 
spectre_v2_select_mitigation(void)1867 static void __init spectre_v2_select_mitigation(void)
1868 {
1869 	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1870 	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1871 
1872 	/*
1873 	 * If the CPU is not affected and the command line mode is NONE or AUTO
1874 	 * then nothing to do.
1875 	 */
1876 	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1877 	    (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1878 		return;
1879 
1880 	switch (cmd) {
1881 	case SPECTRE_V2_CMD_NONE:
1882 		return;
1883 
1884 	case SPECTRE_V2_CMD_FORCE:
1885 	case SPECTRE_V2_CMD_AUTO:
1886 		if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1887 			mode = SPECTRE_V2_EIBRS;
1888 			break;
1889 		}
1890 
1891 		if (IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY) &&
1892 		    boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1893 		    retbleed_cmd != RETBLEED_CMD_OFF &&
1894 		    retbleed_cmd != RETBLEED_CMD_STUFF &&
1895 		    boot_cpu_has(X86_FEATURE_IBRS) &&
1896 		    boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1897 			mode = SPECTRE_V2_IBRS;
1898 			break;
1899 		}
1900 
1901 		mode = spectre_v2_select_retpoline();
1902 		break;
1903 
1904 	case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1905 		pr_err(SPECTRE_V2_LFENCE_MSG);
1906 		mode = SPECTRE_V2_LFENCE;
1907 		break;
1908 
1909 	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1910 		mode = SPECTRE_V2_RETPOLINE;
1911 		break;
1912 
1913 	case SPECTRE_V2_CMD_RETPOLINE:
1914 		mode = spectre_v2_select_retpoline();
1915 		break;
1916 
1917 	case SPECTRE_V2_CMD_IBRS:
1918 		mode = SPECTRE_V2_IBRS;
1919 		break;
1920 
1921 	case SPECTRE_V2_CMD_EIBRS:
1922 		mode = SPECTRE_V2_EIBRS;
1923 		break;
1924 
1925 	case SPECTRE_V2_CMD_EIBRS_LFENCE:
1926 		mode = SPECTRE_V2_EIBRS_LFENCE;
1927 		break;
1928 
1929 	case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1930 		mode = SPECTRE_V2_EIBRS_RETPOLINE;
1931 		break;
1932 	}
1933 
1934 	if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1935 		pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1936 
1937 	if (spectre_v2_in_ibrs_mode(mode)) {
1938 		if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) {
1939 			msr_set_bit(MSR_EFER, _EFER_AUTOIBRS);
1940 		} else {
1941 			x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1942 			update_spec_ctrl(x86_spec_ctrl_base);
1943 		}
1944 	}
1945 
1946 	switch (mode) {
1947 	case SPECTRE_V2_NONE:
1948 	case SPECTRE_V2_EIBRS:
1949 		break;
1950 
1951 	case SPECTRE_V2_IBRS:
1952 		setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1953 		if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1954 			pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1955 		break;
1956 
1957 	case SPECTRE_V2_LFENCE:
1958 	case SPECTRE_V2_EIBRS_LFENCE:
1959 		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1960 		fallthrough;
1961 
1962 	case SPECTRE_V2_RETPOLINE:
1963 	case SPECTRE_V2_EIBRS_RETPOLINE:
1964 		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1965 		break;
1966 	}
1967 
1968 	/*
1969 	 * Disable alternate RSB predictions in kernel when indirect CALLs and
1970 	 * JMPs gets protection against BHI and Intramode-BTI, but RET
1971 	 * prediction from a non-RSB predictor is still a risk.
1972 	 */
1973 	if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1974 	    mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1975 	    mode == SPECTRE_V2_RETPOLINE)
1976 		spec_ctrl_disable_kernel_rrsba();
1977 
1978 	if (boot_cpu_has(X86_BUG_BHI))
1979 		bhi_select_mitigation();
1980 
1981 	spectre_v2_enabled = mode;
1982 	pr_info("%s\n", spectre_v2_strings[mode]);
1983 
1984 	spectre_v2_select_rsb_mitigation(mode);
1985 
1986 	/*
1987 	 * Retpoline protects the kernel, but doesn't protect firmware.  IBRS
1988 	 * and Enhanced IBRS protect firmware too, so enable IBRS around
1989 	 * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't
1990 	 * otherwise enabled.
1991 	 *
1992 	 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1993 	 * the user might select retpoline on the kernel command line and if
1994 	 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1995 	 * enable IBRS around firmware calls.
1996 	 */
1997 	if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1998 	    boot_cpu_has(X86_FEATURE_IBPB) &&
1999 	    (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2000 	     boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
2001 
2002 		if (retbleed_cmd != RETBLEED_CMD_IBPB) {
2003 			setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
2004 			pr_info("Enabling Speculation Barrier for firmware calls\n");
2005 		}
2006 
2007 	} else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
2008 		setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
2009 		pr_info("Enabling Restricted Speculation for firmware calls\n");
2010 	}
2011 
2012 	/* Set up IBPB and STIBP depending on the general spectre V2 command */
2013 	spectre_v2_cmd = cmd;
2014 }
2015 
update_stibp_msr(void * __unused)2016 static void update_stibp_msr(void * __unused)
2017 {
2018 	u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
2019 	update_spec_ctrl(val);
2020 }
2021 
2022 /* Update x86_spec_ctrl_base in case SMT state changed. */
update_stibp_strict(void)2023 static void update_stibp_strict(void)
2024 {
2025 	u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
2026 
2027 	if (sched_smt_active())
2028 		mask |= SPEC_CTRL_STIBP;
2029 
2030 	if (mask == x86_spec_ctrl_base)
2031 		return;
2032 
2033 	pr_info("Update user space SMT mitigation: STIBP %s\n",
2034 		mask & SPEC_CTRL_STIBP ? "always-on" : "off");
2035 	x86_spec_ctrl_base = mask;
2036 	on_each_cpu(update_stibp_msr, NULL, 1);
2037 }
2038 
2039 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
update_indir_branch_cond(void)2040 static void update_indir_branch_cond(void)
2041 {
2042 	if (sched_smt_active())
2043 		static_branch_enable(&switch_to_cond_stibp);
2044 	else
2045 		static_branch_disable(&switch_to_cond_stibp);
2046 }
2047 
2048 #undef pr_fmt
2049 #define pr_fmt(fmt) fmt
2050 
2051 /* Update the static key controlling the MDS CPU buffer clear in idle */
update_mds_branch_idle(void)2052 static void update_mds_branch_idle(void)
2053 {
2054 	/*
2055 	 * Enable the idle clearing if SMT is active on CPUs which are
2056 	 * affected only by MSBDS and not any other MDS variant.
2057 	 *
2058 	 * The other variants cannot be mitigated when SMT is enabled, so
2059 	 * clearing the buffers on idle just to prevent the Store Buffer
2060 	 * repartitioning leak would be a window dressing exercise.
2061 	 */
2062 	if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
2063 		return;
2064 
2065 	if (sched_smt_active()) {
2066 		static_branch_enable(&mds_idle_clear);
2067 	} else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
2068 		   (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO)) {
2069 		static_branch_disable(&mds_idle_clear);
2070 	}
2071 }
2072 
2073 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
2074 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
2075 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
2076 
cpu_bugs_smt_update(void)2077 void cpu_bugs_smt_update(void)
2078 {
2079 	mutex_lock(&spec_ctrl_mutex);
2080 
2081 	if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2082 	    spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2083 		pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
2084 
2085 	switch (spectre_v2_user_stibp) {
2086 	case SPECTRE_V2_USER_NONE:
2087 		break;
2088 	case SPECTRE_V2_USER_STRICT:
2089 	case SPECTRE_V2_USER_STRICT_PREFERRED:
2090 		update_stibp_strict();
2091 		break;
2092 	case SPECTRE_V2_USER_PRCTL:
2093 	case SPECTRE_V2_USER_SECCOMP:
2094 		update_indir_branch_cond();
2095 		break;
2096 	}
2097 
2098 	switch (mds_mitigation) {
2099 	case MDS_MITIGATION_FULL:
2100 	case MDS_MITIGATION_AUTO:
2101 	case MDS_MITIGATION_VMWERV:
2102 		if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
2103 			pr_warn_once(MDS_MSG_SMT);
2104 		update_mds_branch_idle();
2105 		break;
2106 	case MDS_MITIGATION_OFF:
2107 		break;
2108 	}
2109 
2110 	switch (taa_mitigation) {
2111 	case TAA_MITIGATION_VERW:
2112 	case TAA_MITIGATION_AUTO:
2113 	case TAA_MITIGATION_UCODE_NEEDED:
2114 		if (sched_smt_active())
2115 			pr_warn_once(TAA_MSG_SMT);
2116 		break;
2117 	case TAA_MITIGATION_TSX_DISABLED:
2118 	case TAA_MITIGATION_OFF:
2119 		break;
2120 	}
2121 
2122 	switch (mmio_mitigation) {
2123 	case MMIO_MITIGATION_VERW:
2124 	case MMIO_MITIGATION_AUTO:
2125 	case MMIO_MITIGATION_UCODE_NEEDED:
2126 		if (sched_smt_active())
2127 			pr_warn_once(MMIO_MSG_SMT);
2128 		break;
2129 	case MMIO_MITIGATION_OFF:
2130 		break;
2131 	}
2132 
2133 	mutex_unlock(&spec_ctrl_mutex);
2134 }
2135 
2136 #undef pr_fmt
2137 #define pr_fmt(fmt)	"Speculative Store Bypass: " fmt
2138 
2139 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
2140 
2141 /* The kernel command line selection */
2142 enum ssb_mitigation_cmd {
2143 	SPEC_STORE_BYPASS_CMD_NONE,
2144 	SPEC_STORE_BYPASS_CMD_AUTO,
2145 	SPEC_STORE_BYPASS_CMD_ON,
2146 	SPEC_STORE_BYPASS_CMD_PRCTL,
2147 	SPEC_STORE_BYPASS_CMD_SECCOMP,
2148 };
2149 
2150 static const char * const ssb_strings[] = {
2151 	[SPEC_STORE_BYPASS_NONE]	= "Vulnerable",
2152 	[SPEC_STORE_BYPASS_DISABLE]	= "Mitigation: Speculative Store Bypass disabled",
2153 	[SPEC_STORE_BYPASS_PRCTL]	= "Mitigation: Speculative Store Bypass disabled via prctl",
2154 	[SPEC_STORE_BYPASS_SECCOMP]	= "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
2155 };
2156 
2157 static const struct {
2158 	const char *option;
2159 	enum ssb_mitigation_cmd cmd;
2160 } ssb_mitigation_options[]  __initconst = {
2161 	{ "auto",	SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
2162 	{ "on",		SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
2163 	{ "off",	SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
2164 	{ "prctl",	SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
2165 	{ "seccomp",	SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
2166 };
2167 
ssb_parse_cmdline(void)2168 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
2169 {
2170 	enum ssb_mitigation_cmd cmd;
2171 	char arg[20];
2172 	int ret, i;
2173 
2174 	cmd = IS_ENABLED(CONFIG_MITIGATION_SSB) ?
2175 		SPEC_STORE_BYPASS_CMD_AUTO : SPEC_STORE_BYPASS_CMD_NONE;
2176 	if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
2177 	    cpu_mitigations_off()) {
2178 		return SPEC_STORE_BYPASS_CMD_NONE;
2179 	} else {
2180 		ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
2181 					  arg, sizeof(arg));
2182 		if (ret < 0)
2183 			return cmd;
2184 
2185 		for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
2186 			if (!match_option(arg, ret, ssb_mitigation_options[i].option))
2187 				continue;
2188 
2189 			cmd = ssb_mitigation_options[i].cmd;
2190 			break;
2191 		}
2192 
2193 		if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
2194 			pr_err("unknown option (%s). Switching to default mode\n", arg);
2195 			return cmd;
2196 		}
2197 	}
2198 
2199 	return cmd;
2200 }
2201 
__ssb_select_mitigation(void)2202 static enum ssb_mitigation __init __ssb_select_mitigation(void)
2203 {
2204 	enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
2205 	enum ssb_mitigation_cmd cmd;
2206 
2207 	if (!boot_cpu_has(X86_FEATURE_SSBD))
2208 		return mode;
2209 
2210 	cmd = ssb_parse_cmdline();
2211 	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
2212 	    (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
2213 	     cmd == SPEC_STORE_BYPASS_CMD_AUTO))
2214 		return mode;
2215 
2216 	switch (cmd) {
2217 	case SPEC_STORE_BYPASS_CMD_SECCOMP:
2218 		/*
2219 		 * Choose prctl+seccomp as the default mode if seccomp is
2220 		 * enabled.
2221 		 */
2222 		if (IS_ENABLED(CONFIG_SECCOMP))
2223 			mode = SPEC_STORE_BYPASS_SECCOMP;
2224 		else
2225 			mode = SPEC_STORE_BYPASS_PRCTL;
2226 		break;
2227 	case SPEC_STORE_BYPASS_CMD_ON:
2228 		mode = SPEC_STORE_BYPASS_DISABLE;
2229 		break;
2230 	case SPEC_STORE_BYPASS_CMD_AUTO:
2231 	case SPEC_STORE_BYPASS_CMD_PRCTL:
2232 		mode = SPEC_STORE_BYPASS_PRCTL;
2233 		break;
2234 	case SPEC_STORE_BYPASS_CMD_NONE:
2235 		break;
2236 	}
2237 
2238 	/*
2239 	 * We have three CPU feature flags that are in play here:
2240 	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
2241 	 *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
2242 	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
2243 	 */
2244 	if (mode == SPEC_STORE_BYPASS_DISABLE) {
2245 		setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
2246 		/*
2247 		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
2248 		 * use a completely different MSR and bit dependent on family.
2249 		 */
2250 		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
2251 		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
2252 			x86_amd_ssb_disable();
2253 		} else {
2254 			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
2255 			update_spec_ctrl(x86_spec_ctrl_base);
2256 		}
2257 	}
2258 
2259 	return mode;
2260 }
2261 
ssb_select_mitigation(void)2262 static void ssb_select_mitigation(void)
2263 {
2264 	ssb_mode = __ssb_select_mitigation();
2265 
2266 	if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
2267 		pr_info("%s\n", ssb_strings[ssb_mode]);
2268 }
2269 
2270 #undef pr_fmt
2271 #define pr_fmt(fmt)     "Speculation prctl: " fmt
2272 
task_update_spec_tif(struct task_struct * tsk)2273 static void task_update_spec_tif(struct task_struct *tsk)
2274 {
2275 	/* Force the update of the real TIF bits */
2276 	set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
2277 
2278 	/*
2279 	 * Immediately update the speculation control MSRs for the current
2280 	 * task, but for a non-current task delay setting the CPU
2281 	 * mitigation until it is scheduled next.
2282 	 *
2283 	 * This can only happen for SECCOMP mitigation. For PRCTL it's
2284 	 * always the current task.
2285 	 */
2286 	if (tsk == current)
2287 		speculation_ctrl_update_current();
2288 }
2289 
l1d_flush_prctl_set(struct task_struct * task,unsigned long ctrl)2290 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
2291 {
2292 
2293 	if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
2294 		return -EPERM;
2295 
2296 	switch (ctrl) {
2297 	case PR_SPEC_ENABLE:
2298 		set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
2299 		return 0;
2300 	case PR_SPEC_DISABLE:
2301 		clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
2302 		return 0;
2303 	default:
2304 		return -ERANGE;
2305 	}
2306 }
2307 
ssb_prctl_set(struct task_struct * task,unsigned long ctrl)2308 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
2309 {
2310 	if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
2311 	    ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
2312 		return -ENXIO;
2313 
2314 	switch (ctrl) {
2315 	case PR_SPEC_ENABLE:
2316 		/* If speculation is force disabled, enable is not allowed */
2317 		if (task_spec_ssb_force_disable(task))
2318 			return -EPERM;
2319 		task_clear_spec_ssb_disable(task);
2320 		task_clear_spec_ssb_noexec(task);
2321 		task_update_spec_tif(task);
2322 		break;
2323 	case PR_SPEC_DISABLE:
2324 		task_set_spec_ssb_disable(task);
2325 		task_clear_spec_ssb_noexec(task);
2326 		task_update_spec_tif(task);
2327 		break;
2328 	case PR_SPEC_FORCE_DISABLE:
2329 		task_set_spec_ssb_disable(task);
2330 		task_set_spec_ssb_force_disable(task);
2331 		task_clear_spec_ssb_noexec(task);
2332 		task_update_spec_tif(task);
2333 		break;
2334 	case PR_SPEC_DISABLE_NOEXEC:
2335 		if (task_spec_ssb_force_disable(task))
2336 			return -EPERM;
2337 		task_set_spec_ssb_disable(task);
2338 		task_set_spec_ssb_noexec(task);
2339 		task_update_spec_tif(task);
2340 		break;
2341 	default:
2342 		return -ERANGE;
2343 	}
2344 	return 0;
2345 }
2346 
is_spec_ib_user_controlled(void)2347 static bool is_spec_ib_user_controlled(void)
2348 {
2349 	return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
2350 		spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
2351 		spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
2352 		spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
2353 }
2354 
ib_prctl_set(struct task_struct * task,unsigned long ctrl)2355 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
2356 {
2357 	switch (ctrl) {
2358 	case PR_SPEC_ENABLE:
2359 		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2360 		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2361 			return 0;
2362 
2363 		/*
2364 		 * With strict mode for both IBPB and STIBP, the instruction
2365 		 * code paths avoid checking this task flag and instead,
2366 		 * unconditionally run the instruction. However, STIBP and IBPB
2367 		 * are independent and either can be set to conditionally
2368 		 * enabled regardless of the mode of the other.
2369 		 *
2370 		 * If either is set to conditional, allow the task flag to be
2371 		 * updated, unless it was force-disabled by a previous prctl
2372 		 * call. Currently, this is possible on an AMD CPU which has the
2373 		 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
2374 		 * kernel is booted with 'spectre_v2_user=seccomp', then
2375 		 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
2376 		 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
2377 		 */
2378 		if (!is_spec_ib_user_controlled() ||
2379 		    task_spec_ib_force_disable(task))
2380 			return -EPERM;
2381 
2382 		task_clear_spec_ib_disable(task);
2383 		task_update_spec_tif(task);
2384 		break;
2385 	case PR_SPEC_DISABLE:
2386 	case PR_SPEC_FORCE_DISABLE:
2387 		/*
2388 		 * Indirect branch speculation is always allowed when
2389 		 * mitigation is force disabled.
2390 		 */
2391 		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2392 		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2393 			return -EPERM;
2394 
2395 		if (!is_spec_ib_user_controlled())
2396 			return 0;
2397 
2398 		task_set_spec_ib_disable(task);
2399 		if (ctrl == PR_SPEC_FORCE_DISABLE)
2400 			task_set_spec_ib_force_disable(task);
2401 		task_update_spec_tif(task);
2402 		if (task == current)
2403 			indirect_branch_prediction_barrier();
2404 		break;
2405 	default:
2406 		return -ERANGE;
2407 	}
2408 	return 0;
2409 }
2410 
arch_prctl_spec_ctrl_set(struct task_struct * task,unsigned long which,unsigned long ctrl)2411 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
2412 			     unsigned long ctrl)
2413 {
2414 	switch (which) {
2415 	case PR_SPEC_STORE_BYPASS:
2416 		return ssb_prctl_set(task, ctrl);
2417 	case PR_SPEC_INDIRECT_BRANCH:
2418 		return ib_prctl_set(task, ctrl);
2419 	case PR_SPEC_L1D_FLUSH:
2420 		return l1d_flush_prctl_set(task, ctrl);
2421 	default:
2422 		return -ENODEV;
2423 	}
2424 }
2425 
2426 #ifdef CONFIG_SECCOMP
arch_seccomp_spec_mitigate(struct task_struct * task)2427 void arch_seccomp_spec_mitigate(struct task_struct *task)
2428 {
2429 	if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
2430 		ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
2431 	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
2432 	    spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
2433 		ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
2434 }
2435 #endif
2436 
l1d_flush_prctl_get(struct task_struct * task)2437 static int l1d_flush_prctl_get(struct task_struct *task)
2438 {
2439 	if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
2440 		return PR_SPEC_FORCE_DISABLE;
2441 
2442 	if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
2443 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2444 	else
2445 		return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2446 }
2447 
ssb_prctl_get(struct task_struct * task)2448 static int ssb_prctl_get(struct task_struct *task)
2449 {
2450 	switch (ssb_mode) {
2451 	case SPEC_STORE_BYPASS_NONE:
2452 		if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
2453 			return PR_SPEC_ENABLE;
2454 		return PR_SPEC_NOT_AFFECTED;
2455 	case SPEC_STORE_BYPASS_DISABLE:
2456 		return PR_SPEC_DISABLE;
2457 	case SPEC_STORE_BYPASS_SECCOMP:
2458 	case SPEC_STORE_BYPASS_PRCTL:
2459 		if (task_spec_ssb_force_disable(task))
2460 			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2461 		if (task_spec_ssb_noexec(task))
2462 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
2463 		if (task_spec_ssb_disable(task))
2464 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2465 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2466 	}
2467 	BUG();
2468 }
2469 
ib_prctl_get(struct task_struct * task)2470 static int ib_prctl_get(struct task_struct *task)
2471 {
2472 	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
2473 		return PR_SPEC_NOT_AFFECTED;
2474 
2475 	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2476 	    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2477 		return PR_SPEC_ENABLE;
2478 	else if (is_spec_ib_user_controlled()) {
2479 		if (task_spec_ib_force_disable(task))
2480 			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2481 		if (task_spec_ib_disable(task))
2482 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2483 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2484 	} else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
2485 	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2486 	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
2487 		return PR_SPEC_DISABLE;
2488 	else
2489 		return PR_SPEC_NOT_AFFECTED;
2490 }
2491 
arch_prctl_spec_ctrl_get(struct task_struct * task,unsigned long which)2492 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2493 {
2494 	switch (which) {
2495 	case PR_SPEC_STORE_BYPASS:
2496 		return ssb_prctl_get(task);
2497 	case PR_SPEC_INDIRECT_BRANCH:
2498 		return ib_prctl_get(task);
2499 	case PR_SPEC_L1D_FLUSH:
2500 		return l1d_flush_prctl_get(task);
2501 	default:
2502 		return -ENODEV;
2503 	}
2504 }
2505 
x86_spec_ctrl_setup_ap(void)2506 void x86_spec_ctrl_setup_ap(void)
2507 {
2508 	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2509 		update_spec_ctrl(x86_spec_ctrl_base);
2510 
2511 	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2512 		x86_amd_ssb_disable();
2513 }
2514 
2515 bool itlb_multihit_kvm_mitigation;
2516 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2517 
2518 #undef pr_fmt
2519 #define pr_fmt(fmt)	"L1TF: " fmt
2520 
2521 /* Default mitigation for L1TF-affected CPUs */
2522 enum l1tf_mitigations l1tf_mitigation __ro_after_init =
2523 	IS_ENABLED(CONFIG_MITIGATION_L1TF) ? L1TF_MITIGATION_FLUSH : L1TF_MITIGATION_OFF;
2524 #if IS_ENABLED(CONFIG_KVM_INTEL)
2525 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2526 #endif
2527 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2528 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2529 
2530 /*
2531  * These CPUs all support 44bits physical address space internally in the
2532  * cache but CPUID can report a smaller number of physical address bits.
2533  *
2534  * The L1TF mitigation uses the top most address bit for the inversion of
2535  * non present PTEs. When the installed memory reaches into the top most
2536  * address bit due to memory holes, which has been observed on machines
2537  * which report 36bits physical address bits and have 32G RAM installed,
2538  * then the mitigation range check in l1tf_select_mitigation() triggers.
2539  * This is a false positive because the mitigation is still possible due to
2540  * the fact that the cache uses 44bit internally. Use the cache bits
2541  * instead of the reported physical bits and adjust them on the affected
2542  * machines to 44bit if the reported bits are less than 44.
2543  */
override_cache_bits(struct cpuinfo_x86 * c)2544 static void override_cache_bits(struct cpuinfo_x86 *c)
2545 {
2546 	if (c->x86 != 6)
2547 		return;
2548 
2549 	switch (c->x86_vfm) {
2550 	case INTEL_NEHALEM:
2551 	case INTEL_WESTMERE:
2552 	case INTEL_SANDYBRIDGE:
2553 	case INTEL_IVYBRIDGE:
2554 	case INTEL_HASWELL:
2555 	case INTEL_HASWELL_L:
2556 	case INTEL_HASWELL_G:
2557 	case INTEL_BROADWELL:
2558 	case INTEL_BROADWELL_G:
2559 	case INTEL_SKYLAKE_L:
2560 	case INTEL_SKYLAKE:
2561 	case INTEL_KABYLAKE_L:
2562 	case INTEL_KABYLAKE:
2563 		if (c->x86_cache_bits < 44)
2564 			c->x86_cache_bits = 44;
2565 		break;
2566 	}
2567 }
2568 
l1tf_select_mitigation(void)2569 static void __init l1tf_select_mitigation(void)
2570 {
2571 	u64 half_pa;
2572 
2573 	if (!boot_cpu_has_bug(X86_BUG_L1TF))
2574 		return;
2575 
2576 	if (cpu_mitigations_off())
2577 		l1tf_mitigation = L1TF_MITIGATION_OFF;
2578 	else if (cpu_mitigations_auto_nosmt())
2579 		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2580 
2581 	override_cache_bits(&boot_cpu_data);
2582 
2583 	switch (l1tf_mitigation) {
2584 	case L1TF_MITIGATION_OFF:
2585 	case L1TF_MITIGATION_FLUSH_NOWARN:
2586 	case L1TF_MITIGATION_FLUSH:
2587 		break;
2588 	case L1TF_MITIGATION_FLUSH_NOSMT:
2589 	case L1TF_MITIGATION_FULL:
2590 		cpu_smt_disable(false);
2591 		break;
2592 	case L1TF_MITIGATION_FULL_FORCE:
2593 		cpu_smt_disable(true);
2594 		break;
2595 	}
2596 
2597 #if CONFIG_PGTABLE_LEVELS == 2
2598 	pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2599 	return;
2600 #endif
2601 
2602 	half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2603 	if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2604 			e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2605 		pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2606 		pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2607 				half_pa);
2608 		pr_info("However, doing so will make a part of your RAM unusable.\n");
2609 		pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2610 		return;
2611 	}
2612 
2613 	setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2614 }
2615 
l1tf_cmdline(char * str)2616 static int __init l1tf_cmdline(char *str)
2617 {
2618 	if (!boot_cpu_has_bug(X86_BUG_L1TF))
2619 		return 0;
2620 
2621 	if (!str)
2622 		return -EINVAL;
2623 
2624 	if (!strcmp(str, "off"))
2625 		l1tf_mitigation = L1TF_MITIGATION_OFF;
2626 	else if (!strcmp(str, "flush,nowarn"))
2627 		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2628 	else if (!strcmp(str, "flush"))
2629 		l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2630 	else if (!strcmp(str, "flush,nosmt"))
2631 		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2632 	else if (!strcmp(str, "full"))
2633 		l1tf_mitigation = L1TF_MITIGATION_FULL;
2634 	else if (!strcmp(str, "full,force"))
2635 		l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2636 
2637 	return 0;
2638 }
2639 early_param("l1tf", l1tf_cmdline);
2640 
2641 #undef pr_fmt
2642 #define pr_fmt(fmt)	"Speculative Return Stack Overflow: " fmt
2643 
2644 enum srso_mitigation {
2645 	SRSO_MITIGATION_NONE,
2646 	SRSO_MITIGATION_UCODE_NEEDED,
2647 	SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED,
2648 	SRSO_MITIGATION_MICROCODE,
2649 	SRSO_MITIGATION_SAFE_RET,
2650 	SRSO_MITIGATION_IBPB,
2651 	SRSO_MITIGATION_IBPB_ON_VMEXIT,
2652 	SRSO_MITIGATION_BP_SPEC_REDUCE,
2653 };
2654 
2655 enum srso_mitigation_cmd {
2656 	SRSO_CMD_OFF,
2657 	SRSO_CMD_MICROCODE,
2658 	SRSO_CMD_SAFE_RET,
2659 	SRSO_CMD_IBPB,
2660 	SRSO_CMD_IBPB_ON_VMEXIT,
2661 };
2662 
2663 static const char * const srso_strings[] = {
2664 	[SRSO_MITIGATION_NONE]			= "Vulnerable",
2665 	[SRSO_MITIGATION_UCODE_NEEDED]		= "Vulnerable: No microcode",
2666 	[SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED]	= "Vulnerable: Safe RET, no microcode",
2667 	[SRSO_MITIGATION_MICROCODE]		= "Vulnerable: Microcode, no safe RET",
2668 	[SRSO_MITIGATION_SAFE_RET]		= "Mitigation: Safe RET",
2669 	[SRSO_MITIGATION_IBPB]			= "Mitigation: IBPB",
2670 	[SRSO_MITIGATION_IBPB_ON_VMEXIT]	= "Mitigation: IBPB on VMEXIT only",
2671 	[SRSO_MITIGATION_BP_SPEC_REDUCE]	= "Mitigation: Reduced Speculation"
2672 };
2673 
2674 static enum srso_mitigation srso_mitigation __ro_after_init = SRSO_MITIGATION_NONE;
2675 static enum srso_mitigation_cmd srso_cmd __ro_after_init = SRSO_CMD_SAFE_RET;
2676 
srso_parse_cmdline(char * str)2677 static int __init srso_parse_cmdline(char *str)
2678 {
2679 	if (!str)
2680 		return -EINVAL;
2681 
2682 	if (!strcmp(str, "off"))
2683 		srso_cmd = SRSO_CMD_OFF;
2684 	else if (!strcmp(str, "microcode"))
2685 		srso_cmd = SRSO_CMD_MICROCODE;
2686 	else if (!strcmp(str, "safe-ret"))
2687 		srso_cmd = SRSO_CMD_SAFE_RET;
2688 	else if (!strcmp(str, "ibpb"))
2689 		srso_cmd = SRSO_CMD_IBPB;
2690 	else if (!strcmp(str, "ibpb-vmexit"))
2691 		srso_cmd = SRSO_CMD_IBPB_ON_VMEXIT;
2692 	else
2693 		pr_err("Ignoring unknown SRSO option (%s).", str);
2694 
2695 	return 0;
2696 }
2697 early_param("spec_rstack_overflow", srso_parse_cmdline);
2698 
2699 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html for mitigation options."
2700 
srso_select_mitigation(void)2701 static void __init srso_select_mitigation(void)
2702 {
2703 	bool has_microcode = boot_cpu_has(X86_FEATURE_IBPB_BRTYPE);
2704 
2705 	if (!boot_cpu_has_bug(X86_BUG_SRSO) ||
2706 	    cpu_mitigations_off() ||
2707 	    srso_cmd == SRSO_CMD_OFF) {
2708 		if (boot_cpu_has(X86_FEATURE_SBPB))
2709 			x86_pred_cmd = PRED_CMD_SBPB;
2710 		goto out;
2711 	}
2712 
2713 	if (has_microcode) {
2714 		/*
2715 		 * Zen1/2 with SMT off aren't vulnerable after the right
2716 		 * IBPB microcode has been applied.
2717 		 *
2718 		 * Zen1/2 don't have SBPB, no need to try to enable it here.
2719 		 */
2720 		if (boot_cpu_data.x86 < 0x19 && !cpu_smt_possible()) {
2721 			setup_force_cpu_cap(X86_FEATURE_SRSO_NO);
2722 			goto out;
2723 		}
2724 
2725 		if (retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2726 			srso_mitigation = SRSO_MITIGATION_IBPB;
2727 			goto out;
2728 		}
2729 	} else {
2730 		pr_warn("IBPB-extending microcode not applied!\n");
2731 		pr_warn(SRSO_NOTICE);
2732 
2733 		/* may be overwritten by SRSO_CMD_SAFE_RET below */
2734 		srso_mitigation = SRSO_MITIGATION_UCODE_NEEDED;
2735 	}
2736 
2737 	switch (srso_cmd) {
2738 	case SRSO_CMD_MICROCODE:
2739 		if (has_microcode) {
2740 			srso_mitigation = SRSO_MITIGATION_MICROCODE;
2741 			pr_warn(SRSO_NOTICE);
2742 		}
2743 		break;
2744 
2745 	case SRSO_CMD_SAFE_RET:
2746 		if (boot_cpu_has(X86_FEATURE_SRSO_USER_KERNEL_NO))
2747 			goto ibpb_on_vmexit;
2748 
2749 		if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) {
2750 			/*
2751 			 * Enable the return thunk for generated code
2752 			 * like ftrace, static_call, etc.
2753 			 */
2754 			setup_force_cpu_cap(X86_FEATURE_RETHUNK);
2755 			setup_force_cpu_cap(X86_FEATURE_UNRET);
2756 
2757 			if (boot_cpu_data.x86 == 0x19) {
2758 				setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS);
2759 				set_return_thunk(srso_alias_return_thunk);
2760 			} else {
2761 				setup_force_cpu_cap(X86_FEATURE_SRSO);
2762 				set_return_thunk(srso_return_thunk);
2763 			}
2764 			if (has_microcode)
2765 				srso_mitigation = SRSO_MITIGATION_SAFE_RET;
2766 			else
2767 				srso_mitigation = SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED;
2768 		} else {
2769 			pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n");
2770 		}
2771 		break;
2772 
2773 	case SRSO_CMD_IBPB:
2774 		if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) {
2775 			if (has_microcode) {
2776 				setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
2777 				setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT);
2778 				srso_mitigation = SRSO_MITIGATION_IBPB;
2779 
2780 				/*
2781 				 * IBPB on entry already obviates the need for
2782 				 * software-based untraining so clear those in case some
2783 				 * other mitigation like Retbleed has selected them.
2784 				 */
2785 				setup_clear_cpu_cap(X86_FEATURE_UNRET);
2786 				setup_clear_cpu_cap(X86_FEATURE_RETHUNK);
2787 
2788 				/*
2789 				 * There is no need for RSB filling: write_ibpb() ensures
2790 				 * all predictions, including the RSB, are invalidated,
2791 				 * regardless of IBPB implementation.
2792 				 */
2793 				setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT);
2794 			}
2795 		} else {
2796 			pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n");
2797 		}
2798 		break;
2799 
2800 ibpb_on_vmexit:
2801 	case SRSO_CMD_IBPB_ON_VMEXIT:
2802 		if (boot_cpu_has(X86_FEATURE_SRSO_BP_SPEC_REDUCE)) {
2803 			pr_notice("Reducing speculation to address VM/HV SRSO attack vector.\n");
2804 			srso_mitigation = SRSO_MITIGATION_BP_SPEC_REDUCE;
2805 			break;
2806 		}
2807 
2808 		if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) {
2809 			if (has_microcode) {
2810 				setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT);
2811 				srso_mitigation = SRSO_MITIGATION_IBPB_ON_VMEXIT;
2812 
2813 				/*
2814 				 * There is no need for RSB filling: write_ibpb() ensures
2815 				 * all predictions, including the RSB, are invalidated,
2816 				 * regardless of IBPB implementation.
2817 				 */
2818 				setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT);
2819 			}
2820 		} else {
2821 			pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n");
2822 		}
2823 		break;
2824 	default:
2825 		break;
2826 	}
2827 
2828 out:
2829 	/*
2830 	 * Clear the feature flag if this mitigation is not selected as that
2831 	 * feature flag controls the BpSpecReduce MSR bit toggling in KVM.
2832 	 */
2833 	if (srso_mitigation != SRSO_MITIGATION_BP_SPEC_REDUCE)
2834 		setup_clear_cpu_cap(X86_FEATURE_SRSO_BP_SPEC_REDUCE);
2835 
2836 	if (srso_mitigation != SRSO_MITIGATION_NONE)
2837 		pr_info("%s\n", srso_strings[srso_mitigation]);
2838 }
2839 
2840 #undef pr_fmt
2841 #define pr_fmt(fmt) fmt
2842 
2843 #ifdef CONFIG_SYSFS
2844 
2845 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2846 
2847 #if IS_ENABLED(CONFIG_KVM_INTEL)
2848 static const char * const l1tf_vmx_states[] = {
2849 	[VMENTER_L1D_FLUSH_AUTO]		= "auto",
2850 	[VMENTER_L1D_FLUSH_NEVER]		= "vulnerable",
2851 	[VMENTER_L1D_FLUSH_COND]		= "conditional cache flushes",
2852 	[VMENTER_L1D_FLUSH_ALWAYS]		= "cache flushes",
2853 	[VMENTER_L1D_FLUSH_EPT_DISABLED]	= "EPT disabled",
2854 	[VMENTER_L1D_FLUSH_NOT_REQUIRED]	= "flush not necessary"
2855 };
2856 
l1tf_show_state(char * buf)2857 static ssize_t l1tf_show_state(char *buf)
2858 {
2859 	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2860 		return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG);
2861 
2862 	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2863 	    (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2864 	     sched_smt_active())) {
2865 		return sysfs_emit(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2866 				  l1tf_vmx_states[l1tf_vmx_mitigation]);
2867 	}
2868 
2869 	return sysfs_emit(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2870 			  l1tf_vmx_states[l1tf_vmx_mitigation],
2871 			  sched_smt_active() ? "vulnerable" : "disabled");
2872 }
2873 
itlb_multihit_show_state(char * buf)2874 static ssize_t itlb_multihit_show_state(char *buf)
2875 {
2876 	if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2877 	    !boot_cpu_has(X86_FEATURE_VMX))
2878 		return sysfs_emit(buf, "KVM: Mitigation: VMX unsupported\n");
2879 	else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2880 		return sysfs_emit(buf, "KVM: Mitigation: VMX disabled\n");
2881 	else if (itlb_multihit_kvm_mitigation)
2882 		return sysfs_emit(buf, "KVM: Mitigation: Split huge pages\n");
2883 	else
2884 		return sysfs_emit(buf, "KVM: Vulnerable\n");
2885 }
2886 #else
l1tf_show_state(char * buf)2887 static ssize_t l1tf_show_state(char *buf)
2888 {
2889 	return sysfs_emit(buf, "%s\n", L1TF_DEFAULT_MSG);
2890 }
2891 
itlb_multihit_show_state(char * buf)2892 static ssize_t itlb_multihit_show_state(char *buf)
2893 {
2894 	return sysfs_emit(buf, "Processor vulnerable\n");
2895 }
2896 #endif
2897 
mds_show_state(char * buf)2898 static ssize_t mds_show_state(char *buf)
2899 {
2900 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2901 		return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2902 				  mds_strings[mds_mitigation]);
2903 	}
2904 
2905 	if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2906 		return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2907 				  (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2908 				   sched_smt_active() ? "mitigated" : "disabled"));
2909 	}
2910 
2911 	return sysfs_emit(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2912 			  sched_smt_active() ? "vulnerable" : "disabled");
2913 }
2914 
tsx_async_abort_show_state(char * buf)2915 static ssize_t tsx_async_abort_show_state(char *buf)
2916 {
2917 	if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2918 	    (taa_mitigation == TAA_MITIGATION_OFF))
2919 		return sysfs_emit(buf, "%s\n", taa_strings[taa_mitigation]);
2920 
2921 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2922 		return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2923 				  taa_strings[taa_mitigation]);
2924 	}
2925 
2926 	return sysfs_emit(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2927 			  sched_smt_active() ? "vulnerable" : "disabled");
2928 }
2929 
mmio_stale_data_show_state(char * buf)2930 static ssize_t mmio_stale_data_show_state(char *buf)
2931 {
2932 	if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2933 		return sysfs_emit(buf, "Unknown: No mitigations\n");
2934 
2935 	if (mmio_mitigation == MMIO_MITIGATION_OFF)
2936 		return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2937 
2938 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2939 		return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2940 				  mmio_strings[mmio_mitigation]);
2941 	}
2942 
2943 	return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2944 			  sched_smt_active() ? "vulnerable" : "disabled");
2945 }
2946 
rfds_show_state(char * buf)2947 static ssize_t rfds_show_state(char *buf)
2948 {
2949 	return sysfs_emit(buf, "%s\n", rfds_strings[rfds_mitigation]);
2950 }
2951 
its_show_state(char * buf)2952 static ssize_t its_show_state(char *buf)
2953 {
2954 	return sysfs_emit(buf, "%s\n", its_strings[its_mitigation]);
2955 }
2956 
stibp_state(void)2957 static char *stibp_state(void)
2958 {
2959 	if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
2960 	    !boot_cpu_has(X86_FEATURE_AUTOIBRS))
2961 		return "";
2962 
2963 	switch (spectre_v2_user_stibp) {
2964 	case SPECTRE_V2_USER_NONE:
2965 		return "; STIBP: disabled";
2966 	case SPECTRE_V2_USER_STRICT:
2967 		return "; STIBP: forced";
2968 	case SPECTRE_V2_USER_STRICT_PREFERRED:
2969 		return "; STIBP: always-on";
2970 	case SPECTRE_V2_USER_PRCTL:
2971 	case SPECTRE_V2_USER_SECCOMP:
2972 		if (static_key_enabled(&switch_to_cond_stibp))
2973 			return "; STIBP: conditional";
2974 	}
2975 	return "";
2976 }
2977 
ibpb_state(void)2978 static char *ibpb_state(void)
2979 {
2980 	if (boot_cpu_has(X86_FEATURE_IBPB)) {
2981 		if (static_key_enabled(&switch_mm_always_ibpb))
2982 			return "; IBPB: always-on";
2983 		if (static_key_enabled(&switch_mm_cond_ibpb))
2984 			return "; IBPB: conditional";
2985 		return "; IBPB: disabled";
2986 	}
2987 	return "";
2988 }
2989 
pbrsb_eibrs_state(void)2990 static char *pbrsb_eibrs_state(void)
2991 {
2992 	if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2993 		if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2994 		    boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2995 			return "; PBRSB-eIBRS: SW sequence";
2996 		else
2997 			return "; PBRSB-eIBRS: Vulnerable";
2998 	} else {
2999 		return "; PBRSB-eIBRS: Not affected";
3000 	}
3001 }
3002 
spectre_bhi_state(void)3003 static const char *spectre_bhi_state(void)
3004 {
3005 	if (!boot_cpu_has_bug(X86_BUG_BHI))
3006 		return "; BHI: Not affected";
3007 	else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_HW))
3008 		return "; BHI: BHI_DIS_S";
3009 	else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP))
3010 		return "; BHI: SW loop, KVM: SW loop";
3011 	else if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
3012 		 !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE) &&
3013 		 rrsba_disabled)
3014 		return "; BHI: Retpoline";
3015 	else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))
3016 		return "; BHI: Vulnerable, KVM: SW loop";
3017 
3018 	return "; BHI: Vulnerable";
3019 }
3020 
spectre_v2_show_state(char * buf)3021 static ssize_t spectre_v2_show_state(char *buf)
3022 {
3023 	if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
3024 		return sysfs_emit(buf, "Vulnerable: LFENCE\n");
3025 
3026 	if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
3027 		return sysfs_emit(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
3028 
3029 	if (sched_smt_active() && unprivileged_ebpf_enabled() &&
3030 	    spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
3031 		return sysfs_emit(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
3032 
3033 	return sysfs_emit(buf, "%s%s%s%s%s%s%s%s\n",
3034 			  spectre_v2_strings[spectre_v2_enabled],
3035 			  ibpb_state(),
3036 			  boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? "; IBRS_FW" : "",
3037 			  stibp_state(),
3038 			  boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? "; RSB filling" : "",
3039 			  pbrsb_eibrs_state(),
3040 			  spectre_bhi_state(),
3041 			  /* this should always be at the end */
3042 			  spectre_v2_module_string());
3043 }
3044 
srbds_show_state(char * buf)3045 static ssize_t srbds_show_state(char *buf)
3046 {
3047 	return sysfs_emit(buf, "%s\n", srbds_strings[srbds_mitigation]);
3048 }
3049 
retbleed_show_state(char * buf)3050 static ssize_t retbleed_show_state(char *buf)
3051 {
3052 	if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
3053 	    retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
3054 		if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
3055 		    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
3056 			return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
3057 
3058 		return sysfs_emit(buf, "%s; SMT %s\n", retbleed_strings[retbleed_mitigation],
3059 				  !sched_smt_active() ? "disabled" :
3060 				  spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
3061 				  spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
3062 				  "enabled with STIBP protection" : "vulnerable");
3063 	}
3064 
3065 	return sysfs_emit(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
3066 }
3067 
srso_show_state(char * buf)3068 static ssize_t srso_show_state(char *buf)
3069 {
3070 	if (boot_cpu_has(X86_FEATURE_SRSO_NO))
3071 		return sysfs_emit(buf, "Mitigation: SMT disabled\n");
3072 
3073 	return sysfs_emit(buf, "%s\n", srso_strings[srso_mitigation]);
3074 }
3075 
gds_show_state(char * buf)3076 static ssize_t gds_show_state(char *buf)
3077 {
3078 	return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]);
3079 }
3080 
cpu_show_common(struct device * dev,struct device_attribute * attr,char * buf,unsigned int bug)3081 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
3082 			       char *buf, unsigned int bug)
3083 {
3084 	if (!boot_cpu_has_bug(bug))
3085 		return sysfs_emit(buf, "Not affected\n");
3086 
3087 	switch (bug) {
3088 	case X86_BUG_CPU_MELTDOWN:
3089 		if (boot_cpu_has(X86_FEATURE_PTI))
3090 			return sysfs_emit(buf, "Mitigation: PTI\n");
3091 
3092 		if (hypervisor_is_type(X86_HYPER_XEN_PV))
3093 			return sysfs_emit(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
3094 
3095 		break;
3096 
3097 	case X86_BUG_SPECTRE_V1:
3098 		return sysfs_emit(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
3099 
3100 	case X86_BUG_SPECTRE_V2:
3101 		return spectre_v2_show_state(buf);
3102 
3103 	case X86_BUG_SPEC_STORE_BYPASS:
3104 		return sysfs_emit(buf, "%s\n", ssb_strings[ssb_mode]);
3105 
3106 	case X86_BUG_L1TF:
3107 		if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
3108 			return l1tf_show_state(buf);
3109 		break;
3110 
3111 	case X86_BUG_MDS:
3112 		return mds_show_state(buf);
3113 
3114 	case X86_BUG_TAA:
3115 		return tsx_async_abort_show_state(buf);
3116 
3117 	case X86_BUG_ITLB_MULTIHIT:
3118 		return itlb_multihit_show_state(buf);
3119 
3120 	case X86_BUG_SRBDS:
3121 		return srbds_show_state(buf);
3122 
3123 	case X86_BUG_MMIO_STALE_DATA:
3124 	case X86_BUG_MMIO_UNKNOWN:
3125 		return mmio_stale_data_show_state(buf);
3126 
3127 	case X86_BUG_RETBLEED:
3128 		return retbleed_show_state(buf);
3129 
3130 	case X86_BUG_SRSO:
3131 		return srso_show_state(buf);
3132 
3133 	case X86_BUG_GDS:
3134 		return gds_show_state(buf);
3135 
3136 	case X86_BUG_RFDS:
3137 		return rfds_show_state(buf);
3138 
3139 	case X86_BUG_ITS:
3140 		return its_show_state(buf);
3141 
3142 	default:
3143 		break;
3144 	}
3145 
3146 	return sysfs_emit(buf, "Vulnerable\n");
3147 }
3148 
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)3149 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
3150 {
3151 	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
3152 }
3153 
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)3154 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
3155 {
3156 	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
3157 }
3158 
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)3159 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
3160 {
3161 	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
3162 }
3163 
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)3164 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
3165 {
3166 	return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
3167 }
3168 
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)3169 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
3170 {
3171 	return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
3172 }
3173 
cpu_show_mds(struct device * dev,struct device_attribute * attr,char * buf)3174 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
3175 {
3176 	return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
3177 }
3178 
cpu_show_tsx_async_abort(struct device * dev,struct device_attribute * attr,char * buf)3179 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
3180 {
3181 	return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
3182 }
3183 
cpu_show_itlb_multihit(struct device * dev,struct device_attribute * attr,char * buf)3184 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
3185 {
3186 	return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
3187 }
3188 
cpu_show_srbds(struct device * dev,struct device_attribute * attr,char * buf)3189 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
3190 {
3191 	return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
3192 }
3193 
cpu_show_mmio_stale_data(struct device * dev,struct device_attribute * attr,char * buf)3194 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
3195 {
3196 	if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
3197 		return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
3198 	else
3199 		return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
3200 }
3201 
cpu_show_retbleed(struct device * dev,struct device_attribute * attr,char * buf)3202 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
3203 {
3204 	return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
3205 }
3206 
cpu_show_spec_rstack_overflow(struct device * dev,struct device_attribute * attr,char * buf)3207 ssize_t cpu_show_spec_rstack_overflow(struct device *dev, struct device_attribute *attr, char *buf)
3208 {
3209 	return cpu_show_common(dev, attr, buf, X86_BUG_SRSO);
3210 }
3211 
cpu_show_gds(struct device * dev,struct device_attribute * attr,char * buf)3212 ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf)
3213 {
3214 	return cpu_show_common(dev, attr, buf, X86_BUG_GDS);
3215 }
3216 
cpu_show_reg_file_data_sampling(struct device * dev,struct device_attribute * attr,char * buf)3217 ssize_t cpu_show_reg_file_data_sampling(struct device *dev, struct device_attribute *attr, char *buf)
3218 {
3219 	return cpu_show_common(dev, attr, buf, X86_BUG_RFDS);
3220 }
3221 
cpu_show_indirect_target_selection(struct device * dev,struct device_attribute * attr,char * buf)3222 ssize_t cpu_show_indirect_target_selection(struct device *dev, struct device_attribute *attr, char *buf)
3223 {
3224 	return cpu_show_common(dev, attr, buf, X86_BUG_ITS);
3225 }
3226 #endif
3227 
__warn_thunk(void)3228 void __warn_thunk(void)
3229 {
3230 	WARN_ONCE(1, "Unpatched return thunk in use. This should not happen!\n");
3231 }
3232