1 /*
2 * Netburst Performance Events (P4, old Xeon)
3 *
4 * Copyright (C) 2010 Parallels, Inc., Cyrill Gorcunov <gorcunov@openvz.org>
5 * Copyright (C) 2010 Intel Corporation, Lin Ming <ming.m.lin@intel.com>
6 *
7 * For licencing details see kernel-base/COPYING
8 */
9
10 #include <linux/perf_event.h>
11
12 #include <asm/perf_event_p4.h>
13 #include <asm/cpu_device_id.h>
14 #include <asm/hardirq.h>
15 #include <asm/apic.h>
16
17 #include "../perf_event.h"
18
19 #define P4_CNTR_LIMIT 3
20 /*
21 * array indices: 0,1 - HT threads, used with HT enabled cpu
22 */
23 struct p4_event_bind {
24 unsigned int opcode; /* Event code and ESCR selector */
25 unsigned int escr_msr[2]; /* ESCR MSR for this event */
26 unsigned int escr_emask; /* valid ESCR EventMask bits */
27 unsigned int shared; /* event is shared across threads */
28 signed char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on absence */
29 };
30
31 struct p4_pebs_bind {
32 unsigned int metric_pebs;
33 unsigned int metric_vert;
34 };
35
36 /* it sets P4_PEBS_ENABLE_UOP_TAG as well */
37 #define P4_GEN_PEBS_BIND(name, pebs, vert) \
38 [P4_PEBS_METRIC__##name] = { \
39 .metric_pebs = pebs | P4_PEBS_ENABLE_UOP_TAG, \
40 .metric_vert = vert, \
41 }
42
43 /*
44 * note we have P4_PEBS_ENABLE_UOP_TAG always set here
45 *
46 * it's needed for mapping P4_PEBS_CONFIG_METRIC_MASK bits of
47 * event configuration to find out which values are to be
48 * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
49 * registers
50 */
51 static struct p4_pebs_bind p4_pebs_bind_map[] = {
52 P4_GEN_PEBS_BIND(1stl_cache_load_miss_retired, 0x0000001, 0x0000001),
53 P4_GEN_PEBS_BIND(2ndl_cache_load_miss_retired, 0x0000002, 0x0000001),
54 P4_GEN_PEBS_BIND(dtlb_load_miss_retired, 0x0000004, 0x0000001),
55 P4_GEN_PEBS_BIND(dtlb_store_miss_retired, 0x0000004, 0x0000002),
56 P4_GEN_PEBS_BIND(dtlb_all_miss_retired, 0x0000004, 0x0000003),
57 P4_GEN_PEBS_BIND(tagged_mispred_branch, 0x0018000, 0x0000010),
58 P4_GEN_PEBS_BIND(mob_load_replay_retired, 0x0000200, 0x0000001),
59 P4_GEN_PEBS_BIND(split_load_retired, 0x0000400, 0x0000001),
60 P4_GEN_PEBS_BIND(split_store_retired, 0x0000400, 0x0000002),
61 };
62
63 /*
64 * Note that we don't use CCCR1 here, there is an
65 * exception for P4_BSQ_ALLOCATION but we just have
66 * no workaround
67 *
68 * consider this binding as resources which particular
69 * event may borrow, it doesn't contain EventMask,
70 * Tags and friends -- they are left to a caller
71 */
72 static struct p4_event_bind p4_event_bind_map[] = {
73 [P4_EVENT_TC_DELIVER_MODE] = {
74 .opcode = P4_OPCODE(P4_EVENT_TC_DELIVER_MODE),
75 .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
76 .escr_emask =
77 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) |
78 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DB) |
79 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DI) |
80 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BD) |
81 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BB) |
82 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BI) |
83 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, ID),
84 .shared = 1,
85 .cntr = { {4, 5, -1}, {6, 7, -1} },
86 },
87 [P4_EVENT_BPU_FETCH_REQUEST] = {
88 .opcode = P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST),
89 .escr_msr = { MSR_P4_BPU_ESCR0, MSR_P4_BPU_ESCR1 },
90 .escr_emask =
91 P4_ESCR_EMASK_BIT(P4_EVENT_BPU_FETCH_REQUEST, TCMISS),
92 .cntr = { {0, -1, -1}, {2, -1, -1} },
93 },
94 [P4_EVENT_ITLB_REFERENCE] = {
95 .opcode = P4_OPCODE(P4_EVENT_ITLB_REFERENCE),
96 .escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
97 .escr_emask =
98 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT) |
99 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, MISS) |
100 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT_UK),
101 .cntr = { {0, -1, -1}, {2, -1, -1} },
102 },
103 [P4_EVENT_MEMORY_CANCEL] = {
104 .opcode = P4_OPCODE(P4_EVENT_MEMORY_CANCEL),
105 .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
106 .escr_emask =
107 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL) |
108 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_CANCEL, 64K_CONF),
109 .cntr = { {8, 9, -1}, {10, 11, -1} },
110 },
111 [P4_EVENT_MEMORY_COMPLETE] = {
112 .opcode = P4_OPCODE(P4_EVENT_MEMORY_COMPLETE),
113 .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
114 .escr_emask =
115 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_COMPLETE, LSC) |
116 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_COMPLETE, SSC),
117 .cntr = { {8, 9, -1}, {10, 11, -1} },
118 },
119 [P4_EVENT_LOAD_PORT_REPLAY] = {
120 .opcode = P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY),
121 .escr_msr = { MSR_P4_SAAT_ESCR0, MSR_P4_SAAT_ESCR1 },
122 .escr_emask =
123 P4_ESCR_EMASK_BIT(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD),
124 .cntr = { {8, 9, -1}, {10, 11, -1} },
125 },
126 [P4_EVENT_STORE_PORT_REPLAY] = {
127 .opcode = P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY),
128 .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
129 .escr_emask =
130 P4_ESCR_EMASK_BIT(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST),
131 .cntr = { {8, 9, -1}, {10, 11, -1} },
132 },
133 [P4_EVENT_MOB_LOAD_REPLAY] = {
134 .opcode = P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY),
135 .escr_msr = { MSR_P4_MOB_ESCR0, MSR_P4_MOB_ESCR1 },
136 .escr_emask =
137 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, NO_STA) |
138 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, NO_STD) |
139 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA) |
140 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR),
141 .cntr = { {0, -1, -1}, {2, -1, -1} },
142 },
143 [P4_EVENT_PAGE_WALK_TYPE] = {
144 .opcode = P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE),
145 .escr_msr = { MSR_P4_PMH_ESCR0, MSR_P4_PMH_ESCR1 },
146 .escr_emask =
147 P4_ESCR_EMASK_BIT(P4_EVENT_PAGE_WALK_TYPE, DTMISS) |
148 P4_ESCR_EMASK_BIT(P4_EVENT_PAGE_WALK_TYPE, ITMISS),
149 .shared = 1,
150 .cntr = { {0, -1, -1}, {2, -1, -1} },
151 },
152 [P4_EVENT_BSQ_CACHE_REFERENCE] = {
153 .opcode = P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),
154 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
155 .escr_emask =
156 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
157 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
158 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
159 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
160 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
161 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM) |
162 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
163 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
164 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),
165 .cntr = { {0, -1, -1}, {2, -1, -1} },
166 },
167 [P4_EVENT_IOQ_ALLOCATION] = {
168 .opcode = P4_OPCODE(P4_EVENT_IOQ_ALLOCATION),
169 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
170 .escr_emask =
171 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, DEFAULT) |
172 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, ALL_READ) |
173 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE) |
174 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_UC) |
175 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WC) |
176 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WT) |
177 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WP) |
178 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WB) |
179 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, OWN) |
180 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, OTHER) |
181 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, PREFETCH),
182 .cntr = { {0, -1, -1}, {2, -1, -1} },
183 },
184 [P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */
185 .opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES),
186 .escr_msr = { MSR_P4_FSB_ESCR1, MSR_P4_FSB_ESCR1 },
187 .escr_emask =
188 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT) |
189 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ) |
190 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE) |
191 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC) |
192 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC) |
193 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT) |
194 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP) |
195 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB) |
196 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN) |
197 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER) |
198 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH),
199 .cntr = { {2, -1, -1}, {3, -1, -1} },
200 },
201 [P4_EVENT_FSB_DATA_ACTIVITY] = {
202 .opcode = P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY),
203 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
204 .escr_emask =
205 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
206 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN) |
207 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER) |
208 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV) |
209 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN) |
210 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER),
211 .shared = 1,
212 .cntr = { {0, -1, -1}, {2, -1, -1} },
213 },
214 [P4_EVENT_BSQ_ALLOCATION] = { /* shared ESCR, broken CCCR1 */
215 .opcode = P4_OPCODE(P4_EVENT_BSQ_ALLOCATION),
216 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR0 },
217 .escr_emask =
218 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0) |
219 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1) |
220 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0) |
221 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1) |
222 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE) |
223 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE) |
224 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE) |
225 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE) |
226 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE) |
227 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE) |
228 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0) |
229 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1) |
230 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2),
231 .cntr = { {0, -1, -1}, {1, -1, -1} },
232 },
233 [P4_EVENT_BSQ_ACTIVE_ENTRIES] = { /* shared ESCR */
234 .opcode = P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES),
235 .escr_msr = { MSR_P4_BSU_ESCR1 , MSR_P4_BSU_ESCR1 },
236 .escr_emask =
237 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0) |
238 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1) |
239 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0) |
240 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1) |
241 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE) |
242 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE) |
243 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE) |
244 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE) |
245 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE) |
246 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE) |
247 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0) |
248 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1) |
249 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2),
250 .cntr = { {2, -1, -1}, {3, -1, -1} },
251 },
252 [P4_EVENT_SSE_INPUT_ASSIST] = {
253 .opcode = P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST),
254 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
255 .escr_emask =
256 P4_ESCR_EMASK_BIT(P4_EVENT_SSE_INPUT_ASSIST, ALL),
257 .shared = 1,
258 .cntr = { {8, 9, -1}, {10, 11, -1} },
259 },
260 [P4_EVENT_PACKED_SP_UOP] = {
261 .opcode = P4_OPCODE(P4_EVENT_PACKED_SP_UOP),
262 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
263 .escr_emask =
264 P4_ESCR_EMASK_BIT(P4_EVENT_PACKED_SP_UOP, ALL),
265 .shared = 1,
266 .cntr = { {8, 9, -1}, {10, 11, -1} },
267 },
268 [P4_EVENT_PACKED_DP_UOP] = {
269 .opcode = P4_OPCODE(P4_EVENT_PACKED_DP_UOP),
270 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
271 .escr_emask =
272 P4_ESCR_EMASK_BIT(P4_EVENT_PACKED_DP_UOP, ALL),
273 .shared = 1,
274 .cntr = { {8, 9, -1}, {10, 11, -1} },
275 },
276 [P4_EVENT_SCALAR_SP_UOP] = {
277 .opcode = P4_OPCODE(P4_EVENT_SCALAR_SP_UOP),
278 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
279 .escr_emask =
280 P4_ESCR_EMASK_BIT(P4_EVENT_SCALAR_SP_UOP, ALL),
281 .shared = 1,
282 .cntr = { {8, 9, -1}, {10, 11, -1} },
283 },
284 [P4_EVENT_SCALAR_DP_UOP] = {
285 .opcode = P4_OPCODE(P4_EVENT_SCALAR_DP_UOP),
286 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
287 .escr_emask =
288 P4_ESCR_EMASK_BIT(P4_EVENT_SCALAR_DP_UOP, ALL),
289 .shared = 1,
290 .cntr = { {8, 9, -1}, {10, 11, -1} },
291 },
292 [P4_EVENT_64BIT_MMX_UOP] = {
293 .opcode = P4_OPCODE(P4_EVENT_64BIT_MMX_UOP),
294 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
295 .escr_emask =
296 P4_ESCR_EMASK_BIT(P4_EVENT_64BIT_MMX_UOP, ALL),
297 .shared = 1,
298 .cntr = { {8, 9, -1}, {10, 11, -1} },
299 },
300 [P4_EVENT_128BIT_MMX_UOP] = {
301 .opcode = P4_OPCODE(P4_EVENT_128BIT_MMX_UOP),
302 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
303 .escr_emask =
304 P4_ESCR_EMASK_BIT(P4_EVENT_128BIT_MMX_UOP, ALL),
305 .shared = 1,
306 .cntr = { {8, 9, -1}, {10, 11, -1} },
307 },
308 [P4_EVENT_X87_FP_UOP] = {
309 .opcode = P4_OPCODE(P4_EVENT_X87_FP_UOP),
310 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
311 .escr_emask =
312 P4_ESCR_EMASK_BIT(P4_EVENT_X87_FP_UOP, ALL),
313 .shared = 1,
314 .cntr = { {8, 9, -1}, {10, 11, -1} },
315 },
316 [P4_EVENT_TC_MISC] = {
317 .opcode = P4_OPCODE(P4_EVENT_TC_MISC),
318 .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
319 .escr_emask =
320 P4_ESCR_EMASK_BIT(P4_EVENT_TC_MISC, FLUSH),
321 .cntr = { {4, 5, -1}, {6, 7, -1} },
322 },
323 [P4_EVENT_GLOBAL_POWER_EVENTS] = {
324 .opcode = P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS),
325 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
326 .escr_emask =
327 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING),
328 .cntr = { {0, -1, -1}, {2, -1, -1} },
329 },
330 [P4_EVENT_TC_MS_XFER] = {
331 .opcode = P4_OPCODE(P4_EVENT_TC_MS_XFER),
332 .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
333 .escr_emask =
334 P4_ESCR_EMASK_BIT(P4_EVENT_TC_MS_XFER, CISC),
335 .cntr = { {4, 5, -1}, {6, 7, -1} },
336 },
337 [P4_EVENT_UOP_QUEUE_WRITES] = {
338 .opcode = P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES),
339 .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
340 .escr_emask =
341 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD) |
342 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER) |
343 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM),
344 .cntr = { {4, 5, -1}, {6, 7, -1} },
345 },
346 [P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE] = {
347 .opcode = P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE),
348 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
349 .escr_emask =
350 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL) |
351 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL) |
352 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN) |
353 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT),
354 .cntr = { {4, 5, -1}, {6, 7, -1} },
355 },
356 [P4_EVENT_RETIRED_BRANCH_TYPE] = {
357 .opcode = P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE),
358 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
359 .escr_emask =
360 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
361 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
362 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
363 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT),
364 .cntr = { {4, 5, -1}, {6, 7, -1} },
365 },
366 [P4_EVENT_RESOURCE_STALL] = {
367 .opcode = P4_OPCODE(P4_EVENT_RESOURCE_STALL),
368 .escr_msr = { MSR_P4_ALF_ESCR0, MSR_P4_ALF_ESCR1 },
369 .escr_emask =
370 P4_ESCR_EMASK_BIT(P4_EVENT_RESOURCE_STALL, SBFULL),
371 .cntr = { {12, 13, 16}, {14, 15, 17} },
372 },
373 [P4_EVENT_WC_BUFFER] = {
374 .opcode = P4_OPCODE(P4_EVENT_WC_BUFFER),
375 .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
376 .escr_emask =
377 P4_ESCR_EMASK_BIT(P4_EVENT_WC_BUFFER, WCB_EVICTS) |
378 P4_ESCR_EMASK_BIT(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS),
379 .shared = 1,
380 .cntr = { {8, 9, -1}, {10, 11, -1} },
381 },
382 [P4_EVENT_B2B_CYCLES] = {
383 .opcode = P4_OPCODE(P4_EVENT_B2B_CYCLES),
384 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
385 .escr_emask = 0,
386 .cntr = { {0, -1, -1}, {2, -1, -1} },
387 },
388 [P4_EVENT_BNR] = {
389 .opcode = P4_OPCODE(P4_EVENT_BNR),
390 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
391 .escr_emask = 0,
392 .cntr = { {0, -1, -1}, {2, -1, -1} },
393 },
394 [P4_EVENT_SNOOP] = {
395 .opcode = P4_OPCODE(P4_EVENT_SNOOP),
396 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
397 .escr_emask = 0,
398 .cntr = { {0, -1, -1}, {2, -1, -1} },
399 },
400 [P4_EVENT_RESPONSE] = {
401 .opcode = P4_OPCODE(P4_EVENT_RESPONSE),
402 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
403 .escr_emask = 0,
404 .cntr = { {0, -1, -1}, {2, -1, -1} },
405 },
406 [P4_EVENT_FRONT_END_EVENT] = {
407 .opcode = P4_OPCODE(P4_EVENT_FRONT_END_EVENT),
408 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
409 .escr_emask =
410 P4_ESCR_EMASK_BIT(P4_EVENT_FRONT_END_EVENT, NBOGUS) |
411 P4_ESCR_EMASK_BIT(P4_EVENT_FRONT_END_EVENT, BOGUS),
412 .cntr = { {12, 13, 16}, {14, 15, 17} },
413 },
414 [P4_EVENT_EXECUTION_EVENT] = {
415 .opcode = P4_OPCODE(P4_EVENT_EXECUTION_EVENT),
416 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
417 .escr_emask =
418 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0) |
419 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1) |
420 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2) |
421 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3) |
422 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
423 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
424 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
425 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3),
426 .cntr = { {12, 13, 16}, {14, 15, 17} },
427 },
428 [P4_EVENT_REPLAY_EVENT] = {
429 .opcode = P4_OPCODE(P4_EVENT_REPLAY_EVENT),
430 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
431 .escr_emask =
432 P4_ESCR_EMASK_BIT(P4_EVENT_REPLAY_EVENT, NBOGUS) |
433 P4_ESCR_EMASK_BIT(P4_EVENT_REPLAY_EVENT, BOGUS),
434 .cntr = { {12, 13, 16}, {14, 15, 17} },
435 },
436 [P4_EVENT_INSTR_RETIRED] = {
437 .opcode = P4_OPCODE(P4_EVENT_INSTR_RETIRED),
438 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
439 .escr_emask =
440 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
441 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSTAG) |
442 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG) |
443 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSTAG),
444 .cntr = { {12, 13, 16}, {14, 15, 17} },
445 },
446 [P4_EVENT_UOPS_RETIRED] = {
447 .opcode = P4_OPCODE(P4_EVENT_UOPS_RETIRED),
448 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
449 .escr_emask =
450 P4_ESCR_EMASK_BIT(P4_EVENT_UOPS_RETIRED, NBOGUS) |
451 P4_ESCR_EMASK_BIT(P4_EVENT_UOPS_RETIRED, BOGUS),
452 .cntr = { {12, 13, 16}, {14, 15, 17} },
453 },
454 [P4_EVENT_UOP_TYPE] = {
455 .opcode = P4_OPCODE(P4_EVENT_UOP_TYPE),
456 .escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
457 .escr_emask =
458 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_TYPE, TAGLOADS) |
459 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_TYPE, TAGSTORES),
460 .cntr = { {12, 13, 16}, {14, 15, 17} },
461 },
462 [P4_EVENT_BRANCH_RETIRED] = {
463 .opcode = P4_OPCODE(P4_EVENT_BRANCH_RETIRED),
464 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
465 .escr_emask =
466 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMNP) |
467 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMNM) |
468 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMTP) |
469 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMTM),
470 .cntr = { {12, 13, 16}, {14, 15, 17} },
471 },
472 [P4_EVENT_MISPRED_BRANCH_RETIRED] = {
473 .opcode = P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
474 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
475 .escr_emask =
476 P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
477 .cntr = { {12, 13, 16}, {14, 15, 17} },
478 },
479 [P4_EVENT_X87_ASSIST] = {
480 .opcode = P4_OPCODE(P4_EVENT_X87_ASSIST),
481 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
482 .escr_emask =
483 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, FPSU) |
484 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, FPSO) |
485 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, POAO) |
486 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, POAU) |
487 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, PREA),
488 .cntr = { {12, 13, 16}, {14, 15, 17} },
489 },
490 [P4_EVENT_MACHINE_CLEAR] = {
491 .opcode = P4_OPCODE(P4_EVENT_MACHINE_CLEAR),
492 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
493 .escr_emask =
494 P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, CLEAR) |
495 P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, MOCLEAR) |
496 P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, SMCLEAR),
497 .cntr = { {12, 13, 16}, {14, 15, 17} },
498 },
499 [P4_EVENT_INSTR_COMPLETED] = {
500 .opcode = P4_OPCODE(P4_EVENT_INSTR_COMPLETED),
501 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
502 .escr_emask =
503 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_COMPLETED, NBOGUS) |
504 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_COMPLETED, BOGUS),
505 .cntr = { {12, 13, 16}, {14, 15, 17} },
506 },
507 };
508
509 #define P4_GEN_CACHE_EVENT(event, bit, metric) \
510 p4_config_pack_escr(P4_ESCR_EVENT(event) | \
511 P4_ESCR_EMASK_BIT(event, bit)) | \
512 p4_config_pack_cccr(metric | \
513 P4_CCCR_ESEL(P4_OPCODE_ESEL(P4_OPCODE(event))))
514
515 static __initconst const u64 p4_hw_cache_event_ids
516 [PERF_COUNT_HW_CACHE_MAX]
517 [PERF_COUNT_HW_CACHE_OP_MAX]
518 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
519 {
520 [ C(L1D ) ] = {
521 [ C(OP_READ) ] = {
522 [ C(RESULT_ACCESS) ] = 0x0,
523 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
524 P4_PEBS_METRIC__1stl_cache_load_miss_retired),
525 },
526 },
527 [ C(LL ) ] = {
528 [ C(OP_READ) ] = {
529 [ C(RESULT_ACCESS) ] = 0x0,
530 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
531 P4_PEBS_METRIC__2ndl_cache_load_miss_retired),
532 },
533 },
534 [ C(DTLB) ] = {
535 [ C(OP_READ) ] = {
536 [ C(RESULT_ACCESS) ] = 0x0,
537 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
538 P4_PEBS_METRIC__dtlb_load_miss_retired),
539 },
540 [ C(OP_WRITE) ] = {
541 [ C(RESULT_ACCESS) ] = 0x0,
542 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
543 P4_PEBS_METRIC__dtlb_store_miss_retired),
544 },
545 },
546 [ C(ITLB) ] = {
547 [ C(OP_READ) ] = {
548 [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
549 P4_PEBS_METRIC__none),
550 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
551 P4_PEBS_METRIC__none),
552 },
553 [ C(OP_WRITE) ] = {
554 [ C(RESULT_ACCESS) ] = -1,
555 [ C(RESULT_MISS) ] = -1,
556 },
557 [ C(OP_PREFETCH) ] = {
558 [ C(RESULT_ACCESS) ] = -1,
559 [ C(RESULT_MISS) ] = -1,
560 },
561 },
562 [ C(NODE) ] = {
563 [ C(OP_READ) ] = {
564 [ C(RESULT_ACCESS) ] = -1,
565 [ C(RESULT_MISS) ] = -1,
566 },
567 [ C(OP_WRITE) ] = {
568 [ C(RESULT_ACCESS) ] = -1,
569 [ C(RESULT_MISS) ] = -1,
570 },
571 [ C(OP_PREFETCH) ] = {
572 [ C(RESULT_ACCESS) ] = -1,
573 [ C(RESULT_MISS) ] = -1,
574 },
575 },
576 };
577
578 /*
579 * Because of Netburst being quite restricted in how many
580 * identical events may run simultaneously, we introduce event aliases,
581 * ie the different events which have the same functionality but
582 * utilize non-intersected resources (ESCR/CCCR/counter registers).
583 *
584 * This allow us to relax restrictions a bit and run two or more
585 * identical events together.
586 *
587 * Never set any custom internal bits such as P4_CONFIG_HT,
588 * P4_CONFIG_ALIASABLE or bits for P4_PEBS_METRIC, they are
589 * either up to date automatically or not applicable at all.
590 */
591 static struct p4_event_alias {
592 u64 original;
593 u64 alternative;
594 } p4_event_aliases[] = {
595 {
596 /*
597 * Non-halted cycles can be substituted with non-sleeping cycles (see
598 * Intel SDM Vol3b for details). We need this alias to be able
599 * to run nmi-watchdog and 'perf top' (or any other user space tool
600 * which is interested in running PERF_COUNT_HW_CPU_CYCLES)
601 * simultaneously.
602 */
603 .original =
604 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
605 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
606 .alternative =
607 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_EXECUTION_EVENT) |
608 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0)|
609 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1)|
610 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2)|
611 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3)|
612 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
613 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
614 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
615 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3))|
616 p4_config_pack_cccr(P4_CCCR_THRESHOLD(15) | P4_CCCR_COMPLEMENT |
617 P4_CCCR_COMPARE),
618 },
619 };
620
p4_get_alias_event(u64 config)621 static u64 p4_get_alias_event(u64 config)
622 {
623 u64 config_match;
624 int i;
625
626 /*
627 * Only event with special mark is allowed,
628 * we're to be sure it didn't come as malformed
629 * RAW event.
630 */
631 if (!(config & P4_CONFIG_ALIASABLE))
632 return 0;
633
634 config_match = config & P4_CONFIG_EVENT_ALIAS_MASK;
635
636 for (i = 0; i < ARRAY_SIZE(p4_event_aliases); i++) {
637 if (config_match == p4_event_aliases[i].original) {
638 config_match = p4_event_aliases[i].alternative;
639 break;
640 } else if (config_match == p4_event_aliases[i].alternative) {
641 config_match = p4_event_aliases[i].original;
642 break;
643 }
644 }
645
646 if (i >= ARRAY_SIZE(p4_event_aliases))
647 return 0;
648
649 return config_match | (config & P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS);
650 }
651
652 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
653 /* non-halted CPU clocks */
654 [PERF_COUNT_HW_CPU_CYCLES] =
655 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
656 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)) |
657 P4_CONFIG_ALIASABLE,
658
659 /*
660 * retired instructions
661 * in a sake of simplicity we don't use the FSB tagging
662 */
663 [PERF_COUNT_HW_INSTRUCTIONS] =
664 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_INSTR_RETIRED) |
665 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
666 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG)),
667
668 /* cache hits */
669 [PERF_COUNT_HW_CACHE_REFERENCES] =
670 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
671 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
672 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
673 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
674 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
675 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
676 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),
677
678 /* cache misses */
679 [PERF_COUNT_HW_CACHE_MISSES] =
680 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
681 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
682 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
683 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),
684
685 /* branch instructions retired */
686 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =
687 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_RETIRED_BRANCH_TYPE) |
688 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
689 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
690 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
691 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT)),
692
693 /* mispredicted branches retired */
694 [PERF_COUNT_HW_BRANCH_MISSES] =
695 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_MISPRED_BRANCH_RETIRED) |
696 P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS)),
697
698 /* bus ready clocks (cpu is driving #DRDY_DRV\#DRDY_OWN): */
699 [PERF_COUNT_HW_BUS_CYCLES] =
700 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_FSB_DATA_ACTIVITY) |
701 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
702 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN)) |
703 p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
704 };
705
p4_config_get_bind(u64 config)706 static struct p4_event_bind *p4_config_get_bind(u64 config)
707 {
708 unsigned int evnt = p4_config_unpack_event(config);
709 struct p4_event_bind *bind = NULL;
710
711 if (evnt < ARRAY_SIZE(p4_event_bind_map))
712 bind = &p4_event_bind_map[evnt];
713
714 return bind;
715 }
716
p4_pmu_event_map(int hw_event)717 static u64 p4_pmu_event_map(int hw_event)
718 {
719 struct p4_event_bind *bind;
720 unsigned int esel;
721 u64 config;
722
723 config = p4_general_events[hw_event];
724 bind = p4_config_get_bind(config);
725 esel = P4_OPCODE_ESEL(bind->opcode);
726 config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
727
728 return config;
729 }
730
731 /* check cpu model specifics */
p4_event_match_cpu_model(unsigned int event_idx)732 static bool p4_event_match_cpu_model(unsigned int event_idx)
733 {
734 /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
735 if (event_idx == P4_EVENT_INSTR_COMPLETED) {
736 if (boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT &&
737 boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT_2M &&
738 boot_cpu_data.x86_vfm != INTEL_P4_CEDARMILL)
739 return false;
740 }
741
742 /*
743 * For info
744 * - IQ_ESCR0, IQ_ESCR1 only for models 1 and 2
745 */
746
747 return true;
748 }
749
p4_validate_raw_event(struct perf_event * event)750 static int p4_validate_raw_event(struct perf_event *event)
751 {
752 unsigned int v, emask;
753
754 /* User data may have out-of-bound event index */
755 v = p4_config_unpack_event(event->attr.config);
756 if (v >= ARRAY_SIZE(p4_event_bind_map))
757 return -EINVAL;
758
759 /* It may be unsupported: */
760 if (!p4_event_match_cpu_model(v))
761 return -EINVAL;
762
763 /*
764 * NOTE: P4_CCCR_THREAD_ANY has not the same meaning as
765 * in Architectural Performance Monitoring, it means not
766 * on _which_ logical cpu to count but rather _when_, ie it
767 * depends on logical cpu state -- count event if one cpu active,
768 * none, both or any, so we just allow user to pass any value
769 * desired.
770 *
771 * In turn we always set Tx_OS/Tx_USR bits bound to logical
772 * cpu without their propagation to another cpu
773 */
774
775 /*
776 * if an event is shared across the logical threads
777 * the user needs special permissions to be able to use it
778 */
779 if (p4_ht_active() && p4_event_bind_map[v].shared) {
780 v = perf_allow_cpu();
781 if (v)
782 return v;
783 }
784
785 /* ESCR EventMask bits may be invalid */
786 emask = p4_config_unpack_escr(event->attr.config) & P4_ESCR_EVENTMASK_MASK;
787 if (emask & ~p4_event_bind_map[v].escr_emask)
788 return -EINVAL;
789
790 /*
791 * it may have some invalid PEBS bits
792 */
793 if (p4_config_pebs_has(event->attr.config, P4_PEBS_CONFIG_ENABLE))
794 return -EINVAL;
795
796 v = p4_config_unpack_metric(event->attr.config);
797 if (v >= ARRAY_SIZE(p4_pebs_bind_map))
798 return -EINVAL;
799
800 return 0;
801 }
802
p4_hw_config(struct perf_event * event)803 static int p4_hw_config(struct perf_event *event)
804 {
805 int cpu = get_cpu();
806 int rc = 0;
807 u32 escr, cccr;
808
809 /*
810 * the reason we use cpu that early is that: if we get scheduled
811 * first time on the same cpu -- we will not need swap thread
812 * specific flags in config (and will save some cpu cycles)
813 */
814
815 cccr = p4_default_cccr_conf(cpu);
816 escr = p4_default_escr_conf(cpu, event->attr.exclude_kernel,
817 event->attr.exclude_user);
818 event->hw.config = p4_config_pack_escr(escr) |
819 p4_config_pack_cccr(cccr);
820
821 if (p4_ht_active() && p4_ht_thread(cpu))
822 event->hw.config = p4_set_ht_bit(event->hw.config);
823
824 if (event->attr.type == PERF_TYPE_RAW) {
825 struct p4_event_bind *bind;
826 unsigned int esel;
827 /*
828 * Clear bits we reserve to be managed by kernel itself
829 * and never allowed from a user space
830 */
831 event->attr.config &= P4_CONFIG_MASK;
832
833 rc = p4_validate_raw_event(event);
834 if (rc)
835 goto out;
836
837 /*
838 * Note that for RAW events we allow user to use P4_CCCR_RESERVED
839 * bits since we keep additional info here (for cache events and etc)
840 */
841 event->hw.config |= event->attr.config;
842 bind = p4_config_get_bind(event->attr.config);
843 if (!bind) {
844 rc = -EINVAL;
845 goto out;
846 }
847 esel = P4_OPCODE_ESEL(bind->opcode);
848 event->hw.config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
849 }
850
851 rc = x86_setup_perfctr(event);
852 out:
853 put_cpu();
854 return rc;
855 }
856
p4_pmu_clear_cccr_ovf(struct hw_perf_event * hwc)857 static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
858 {
859 u64 v;
860
861 /* an official way for overflow indication */
862 rdmsrl(hwc->config_base, v);
863 if (v & P4_CCCR_OVF) {
864 wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF);
865 return 1;
866 }
867
868 /*
869 * In some circumstances the overflow might issue an NMI but did
870 * not set P4_CCCR_OVF bit. Because a counter holds a negative value
871 * we simply check for high bit being set, if it's cleared it means
872 * the counter has reached zero value and continued counting before
873 * real NMI signal was received:
874 */
875 rdmsrl(hwc->event_base, v);
876 if (!(v & ARCH_P4_UNFLAGGED_BIT))
877 return 1;
878
879 return 0;
880 }
881
p4_pmu_disable_pebs(void)882 static void p4_pmu_disable_pebs(void)
883 {
884 /*
885 * FIXME
886 *
887 * It's still allowed that two threads setup same cache
888 * events so we can't simply clear metrics until we knew
889 * no one is depending on us, so we need kind of counter
890 * for "ReplayEvent" users.
891 *
892 * What is more complex -- RAW events, if user (for some
893 * reason) will pass some cache event metric with improper
894 * event opcode -- it's fine from hardware point of view
895 * but completely nonsense from "meaning" of such action.
896 *
897 * So at moment let leave metrics turned on forever -- it's
898 * ok for now but need to be revisited!
899 *
900 * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0);
901 * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0);
902 */
903 }
904
p4_pmu_disable_event(struct perf_event * event)905 static inline void p4_pmu_disable_event(struct perf_event *event)
906 {
907 struct hw_perf_event *hwc = &event->hw;
908
909 /*
910 * If event gets disabled while counter is in overflowed
911 * state we need to clear P4_CCCR_OVF, otherwise interrupt get
912 * asserted again and again
913 */
914 (void)wrmsrl_safe(hwc->config_base,
915 p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
916 }
917
p4_pmu_disable_all(void)918 static void p4_pmu_disable_all(void)
919 {
920 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
921 int idx;
922
923 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
924 struct perf_event *event = cpuc->events[idx];
925 if (!test_bit(idx, cpuc->active_mask))
926 continue;
927 p4_pmu_disable_event(event);
928 }
929
930 p4_pmu_disable_pebs();
931 }
932
933 /* configuration must be valid */
p4_pmu_enable_pebs(u64 config)934 static void p4_pmu_enable_pebs(u64 config)
935 {
936 struct p4_pebs_bind *bind;
937 unsigned int idx;
938
939 BUILD_BUG_ON(P4_PEBS_METRIC__max > P4_PEBS_CONFIG_METRIC_MASK);
940
941 idx = p4_config_unpack_metric(config);
942 if (idx == P4_PEBS_METRIC__none)
943 return;
944
945 bind = &p4_pebs_bind_map[idx];
946
947 (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs);
948 (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert);
949 }
950
__p4_pmu_enable_event(struct perf_event * event)951 static void __p4_pmu_enable_event(struct perf_event *event)
952 {
953 struct hw_perf_event *hwc = &event->hw;
954 int thread = p4_ht_config_thread(hwc->config);
955 u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
956 unsigned int idx = p4_config_unpack_event(hwc->config);
957 struct p4_event_bind *bind;
958 u64 escr_addr, cccr;
959
960 bind = &p4_event_bind_map[idx];
961 escr_addr = bind->escr_msr[thread];
962
963 /*
964 * - we dont support cascaded counters yet
965 * - and counter 1 is broken (erratum)
966 */
967 WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
968 WARN_ON_ONCE(hwc->idx == 1);
969
970 /* we need a real Event value */
971 escr_conf &= ~P4_ESCR_EVENT_MASK;
972 escr_conf |= P4_ESCR_EVENT(P4_OPCODE_EVNT(bind->opcode));
973
974 cccr = p4_config_unpack_cccr(hwc->config);
975
976 /*
977 * it could be Cache event so we need to write metrics
978 * into additional MSRs
979 */
980 p4_pmu_enable_pebs(hwc->config);
981
982 (void)wrmsrl_safe(escr_addr, escr_conf);
983 (void)wrmsrl_safe(hwc->config_base,
984 (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
985 }
986
987 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(X86_PMC_IDX_MAX)], p4_running);
988
p4_pmu_enable_event(struct perf_event * event)989 static void p4_pmu_enable_event(struct perf_event *event)
990 {
991 int idx = event->hw.idx;
992
993 __set_bit(idx, per_cpu(p4_running, smp_processor_id()));
994 __p4_pmu_enable_event(event);
995 }
996
p4_pmu_enable_all(int added)997 static void p4_pmu_enable_all(int added)
998 {
999 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1000 int idx;
1001
1002 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
1003 struct perf_event *event = cpuc->events[idx];
1004 if (!test_bit(idx, cpuc->active_mask))
1005 continue;
1006 __p4_pmu_enable_event(event);
1007 }
1008 }
1009
p4_pmu_set_period(struct perf_event * event)1010 static int p4_pmu_set_period(struct perf_event *event)
1011 {
1012 struct hw_perf_event *hwc = &event->hw;
1013 s64 left = this_cpu_read(pmc_prev_left[hwc->idx]);
1014 int ret;
1015
1016 ret = x86_perf_event_set_period(event);
1017
1018 if (hwc->event_base) {
1019 /*
1020 * This handles erratum N15 in intel doc 249199-029,
1021 * the counter may not be updated correctly on write
1022 * so we need a second write operation to do the trick
1023 * (the official workaround didn't work)
1024 *
1025 * the former idea is taken from OProfile code
1026 */
1027 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1028 }
1029
1030 return ret;
1031 }
1032
p4_pmu_handle_irq(struct pt_regs * regs)1033 static int p4_pmu_handle_irq(struct pt_regs *regs)
1034 {
1035 struct perf_sample_data data;
1036 struct cpu_hw_events *cpuc;
1037 struct perf_event *event;
1038 struct hw_perf_event *hwc;
1039 int idx, handled = 0;
1040 u64 val;
1041
1042 cpuc = this_cpu_ptr(&cpu_hw_events);
1043
1044 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
1045 int overflow;
1046
1047 if (!test_bit(idx, cpuc->active_mask)) {
1048 /* catch in-flight IRQs */
1049 if (__test_and_clear_bit(idx, per_cpu(p4_running, smp_processor_id())))
1050 handled++;
1051 continue;
1052 }
1053
1054 event = cpuc->events[idx];
1055 hwc = &event->hw;
1056
1057 WARN_ON_ONCE(hwc->idx != idx);
1058
1059 /* it might be unflagged overflow */
1060 overflow = p4_pmu_clear_cccr_ovf(hwc);
1061
1062 val = x86_perf_event_update(event);
1063 if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1))))
1064 continue;
1065
1066 handled += overflow;
1067
1068 /* event overflow for sure */
1069 perf_sample_data_init(&data, 0, hwc->last_period);
1070
1071 if (!static_call(x86_pmu_set_period)(event))
1072 continue;
1073
1074
1075 if (perf_event_overflow(event, &data, regs))
1076 x86_pmu_stop(event, 0);
1077 }
1078
1079 if (handled)
1080 inc_irq_stat(apic_perf_irqs);
1081
1082 /*
1083 * When dealing with the unmasking of the LVTPC on P4 perf hw, it has
1084 * been observed that the OVF bit flag has to be cleared first _before_
1085 * the LVTPC can be unmasked.
1086 *
1087 * The reason is the NMI line will continue to be asserted while the OVF
1088 * bit is set. This causes a second NMI to generate if the LVTPC is
1089 * unmasked before the OVF bit is cleared, leading to unknown NMI
1090 * messages.
1091 */
1092 apic_write(APIC_LVTPC, APIC_DM_NMI);
1093
1094 return handled;
1095 }
1096
1097 /*
1098 * swap thread specific fields according to a thread
1099 * we are going to run on
1100 */
p4_pmu_swap_config_ts(struct hw_perf_event * hwc,int cpu)1101 static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
1102 {
1103 u32 escr, cccr;
1104
1105 /*
1106 * we either lucky and continue on same cpu or no HT support
1107 */
1108 if (!p4_should_swap_ts(hwc->config, cpu))
1109 return;
1110
1111 /*
1112 * the event is migrated from an another logical
1113 * cpu, so we need to swap thread specific flags
1114 */
1115
1116 escr = p4_config_unpack_escr(hwc->config);
1117 cccr = p4_config_unpack_cccr(hwc->config);
1118
1119 if (p4_ht_thread(cpu)) {
1120 cccr &= ~P4_CCCR_OVF_PMI_T0;
1121 cccr |= P4_CCCR_OVF_PMI_T1;
1122 if (escr & P4_ESCR_T0_OS) {
1123 escr &= ~P4_ESCR_T0_OS;
1124 escr |= P4_ESCR_T1_OS;
1125 }
1126 if (escr & P4_ESCR_T0_USR) {
1127 escr &= ~P4_ESCR_T0_USR;
1128 escr |= P4_ESCR_T1_USR;
1129 }
1130 hwc->config = p4_config_pack_escr(escr);
1131 hwc->config |= p4_config_pack_cccr(cccr);
1132 hwc->config |= P4_CONFIG_HT;
1133 } else {
1134 cccr &= ~P4_CCCR_OVF_PMI_T1;
1135 cccr |= P4_CCCR_OVF_PMI_T0;
1136 if (escr & P4_ESCR_T1_OS) {
1137 escr &= ~P4_ESCR_T1_OS;
1138 escr |= P4_ESCR_T0_OS;
1139 }
1140 if (escr & P4_ESCR_T1_USR) {
1141 escr &= ~P4_ESCR_T1_USR;
1142 escr |= P4_ESCR_T0_USR;
1143 }
1144 hwc->config = p4_config_pack_escr(escr);
1145 hwc->config |= p4_config_pack_cccr(cccr);
1146 hwc->config &= ~P4_CONFIG_HT;
1147 }
1148 }
1149
1150 /*
1151 * ESCR address hashing is tricky, ESCRs are not sequential
1152 * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and
1153 * the metric between any ESCRs is laid in range [0xa0,0xe1]
1154 *
1155 * so we make ~70% filled hashtable
1156 */
1157
1158 #define P4_ESCR_MSR_BASE 0x000003a0
1159 #define P4_ESCR_MSR_MAX 0x000003e1
1160 #define P4_ESCR_MSR_TABLE_SIZE (P4_ESCR_MSR_MAX - P4_ESCR_MSR_BASE + 1)
1161 #define P4_ESCR_MSR_IDX(msr) (msr - P4_ESCR_MSR_BASE)
1162 #define P4_ESCR_MSR_TABLE_ENTRY(msr) [P4_ESCR_MSR_IDX(msr)] = msr
1163
1164 static const unsigned int p4_escr_table[P4_ESCR_MSR_TABLE_SIZE] = {
1165 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR0),
1166 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR1),
1167 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR0),
1168 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR1),
1169 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR0),
1170 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR1),
1171 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR0),
1172 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR1),
1173 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR2),
1174 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR3),
1175 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR4),
1176 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR5),
1177 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR0),
1178 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR1),
1179 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR0),
1180 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR1),
1181 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR0),
1182 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR1),
1183 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR0),
1184 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR1),
1185 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR0),
1186 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR1),
1187 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR0),
1188 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR1),
1189 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR0),
1190 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR1),
1191 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR0),
1192 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR1),
1193 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR0),
1194 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR1),
1195 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR0),
1196 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR1),
1197 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR0),
1198 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR1),
1199 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR0),
1200 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR1),
1201 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR0),
1202 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR1),
1203 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR0),
1204 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR1),
1205 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR0),
1206 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR1),
1207 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR0),
1208 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR1),
1209 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR0),
1210 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR1),
1211 };
1212
p4_get_escr_idx(unsigned int addr)1213 static int p4_get_escr_idx(unsigned int addr)
1214 {
1215 unsigned int idx = P4_ESCR_MSR_IDX(addr);
1216
1217 if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE ||
1218 !p4_escr_table[idx] ||
1219 p4_escr_table[idx] != addr)) {
1220 WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);
1221 return -1;
1222 }
1223
1224 return idx;
1225 }
1226
p4_next_cntr(int thread,unsigned long * used_mask,struct p4_event_bind * bind)1227 static int p4_next_cntr(int thread, unsigned long *used_mask,
1228 struct p4_event_bind *bind)
1229 {
1230 int i, j;
1231
1232 for (i = 0; i < P4_CNTR_LIMIT; i++) {
1233 j = bind->cntr[thread][i];
1234 if (j != -1 && !test_bit(j, used_mask))
1235 return j;
1236 }
1237
1238 return -1;
1239 }
1240
p4_pmu_schedule_events(struct cpu_hw_events * cpuc,int n,int * assign)1241 static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1242 {
1243 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1244 unsigned long escr_mask[BITS_TO_LONGS(P4_ESCR_MSR_TABLE_SIZE)];
1245 int cpu = smp_processor_id();
1246 struct hw_perf_event *hwc;
1247 struct p4_event_bind *bind;
1248 unsigned int i, thread, num;
1249 int cntr_idx, escr_idx;
1250 u64 config_alias;
1251 int pass;
1252
1253 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1254 bitmap_zero(escr_mask, P4_ESCR_MSR_TABLE_SIZE);
1255
1256 for (i = 0, num = n; i < n; i++, num--) {
1257
1258 hwc = &cpuc->event_list[i]->hw;
1259 thread = p4_ht_thread(cpu);
1260 pass = 0;
1261
1262 again:
1263 /*
1264 * It's possible to hit a circular lock
1265 * between original and alternative events
1266 * if both are scheduled already.
1267 */
1268 if (pass > 2)
1269 goto done;
1270
1271 bind = p4_config_get_bind(hwc->config);
1272 escr_idx = p4_get_escr_idx(bind->escr_msr[thread]);
1273 if (unlikely(escr_idx == -1))
1274 goto done;
1275
1276 if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) {
1277 cntr_idx = hwc->idx;
1278 if (assign)
1279 assign[i] = hwc->idx;
1280 goto reserve;
1281 }
1282
1283 cntr_idx = p4_next_cntr(thread, used_mask, bind);
1284 if (cntr_idx == -1 || test_bit(escr_idx, escr_mask)) {
1285 /*
1286 * Check whether an event alias is still available.
1287 */
1288 config_alias = p4_get_alias_event(hwc->config);
1289 if (!config_alias)
1290 goto done;
1291 hwc->config = config_alias;
1292 pass++;
1293 goto again;
1294 }
1295 /*
1296 * Perf does test runs to see if a whole group can be assigned
1297 * together successfully. There can be multiple rounds of this.
1298 * Unfortunately, p4_pmu_swap_config_ts touches the hwc->config
1299 * bits, such that the next round of group assignments will
1300 * cause the above p4_should_swap_ts to pass instead of fail.
1301 * This leads to counters exclusive to thread0 being used by
1302 * thread1.
1303 *
1304 * Solve this with a cheap hack, reset the idx back to -1 to
1305 * force a new lookup (p4_next_cntr) to get the right counter
1306 * for the right thread.
1307 *
1308 * This probably doesn't comply with the general spirit of how
1309 * perf wants to work, but P4 is special. :-(
1310 */
1311 if (p4_should_swap_ts(hwc->config, cpu))
1312 hwc->idx = -1;
1313 p4_pmu_swap_config_ts(hwc, cpu);
1314 if (assign)
1315 assign[i] = cntr_idx;
1316 reserve:
1317 set_bit(cntr_idx, used_mask);
1318 set_bit(escr_idx, escr_mask);
1319 }
1320
1321 done:
1322 return num ? -EINVAL : 0;
1323 }
1324
1325 PMU_FORMAT_ATTR(cccr, "config:0-31" );
1326 PMU_FORMAT_ATTR(escr, "config:32-62");
1327 PMU_FORMAT_ATTR(ht, "config:63" );
1328
1329 static struct attribute *intel_p4_formats_attr[] = {
1330 &format_attr_cccr.attr,
1331 &format_attr_escr.attr,
1332 &format_attr_ht.attr,
1333 NULL,
1334 };
1335
1336 static __initconst const struct x86_pmu p4_pmu = {
1337 .name = "Netburst P4/Xeon",
1338 .handle_irq = p4_pmu_handle_irq,
1339 .disable_all = p4_pmu_disable_all,
1340 .enable_all = p4_pmu_enable_all,
1341 .enable = p4_pmu_enable_event,
1342 .disable = p4_pmu_disable_event,
1343
1344 .set_period = p4_pmu_set_period,
1345
1346 .eventsel = MSR_P4_BPU_CCCR0,
1347 .perfctr = MSR_P4_BPU_PERFCTR0,
1348 .event_map = p4_pmu_event_map,
1349 .max_events = ARRAY_SIZE(p4_general_events),
1350 .get_event_constraints = x86_get_event_constraints,
1351 /*
1352 * IF HT disabled we may need to use all
1353 * ARCH_P4_MAX_CCCR counters simultaneously
1354 * though leave it restricted at moment assuming
1355 * HT is on
1356 */
1357 .cntr_mask64 = GENMASK_ULL(ARCH_P4_MAX_CCCR - 1, 0),
1358 .apic = 1,
1359 .cntval_bits = ARCH_P4_CNTRVAL_BITS,
1360 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
1361 .max_period = (1ULL << (ARCH_P4_CNTRVAL_BITS - 1)) - 1,
1362 .hw_config = p4_hw_config,
1363 .schedule_events = p4_pmu_schedule_events,
1364
1365 .format_attrs = intel_p4_formats_attr,
1366 };
1367
p4_pmu_init(void)1368 __init int p4_pmu_init(void)
1369 {
1370 unsigned int low, high;
1371 int i, reg;
1372
1373 /* If we get stripped -- indexing fails */
1374 BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC);
1375
1376 rdmsr(MSR_IA32_MISC_ENABLE, low, high);
1377 if (!(low & (1 << 7))) {
1378 pr_cont("unsupported Netburst CPU model %d ",
1379 boot_cpu_data.x86_model);
1380 return -ENODEV;
1381 }
1382
1383 memcpy(hw_cache_event_ids, p4_hw_cache_event_ids,
1384 sizeof(hw_cache_event_ids));
1385
1386 pr_cont("Netburst events, ");
1387
1388 x86_pmu = p4_pmu;
1389
1390 /*
1391 * Even though the counters are configured to interrupt a particular
1392 * logical processor when an overflow happens, testing has shown that
1393 * on kdump kernels (which uses a single cpu), thread1's counter
1394 * continues to run and will report an NMI on thread0. Due to the
1395 * overflow bug, this leads to a stream of unknown NMIs.
1396 *
1397 * Solve this by zero'ing out the registers to mimic a reset.
1398 */
1399 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
1400 reg = x86_pmu_config_addr(i);
1401 wrmsrl_safe(reg, 0ULL);
1402 }
1403
1404 return 0;
1405 }
1406