1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14
15 #include <linux/bits.h>
16
17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
18 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */
19 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */
20 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
21
22 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
23 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
24 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
25 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
26
27 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
28
29 #ifndef __ASSEMBLY__
30
31 #include <linux/cpumask.h>
32 #include <linux/linkage.h>
33 #include <linux/irqflags.h>
34 #include <linux/bitops.h>
35 #include <asm/fpu-types.h>
36 #include <asm/cpu.h>
37 #include <asm/page.h>
38 #include <asm/ptrace.h>
39 #include <asm/setup.h>
40 #include <asm/runtime_instr.h>
41 #include <asm/irqflags.h>
42 #include <asm/alternative.h>
43 #include <asm/fault.h>
44
45 struct pcpu {
46 unsigned long ec_mask; /* bit mask for ec_xxx functions */
47 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
48 unsigned long flags; /* per CPU flags */
49 unsigned long capacity; /* cpu capacity for scheduler */
50 signed char state; /* physical cpu state */
51 signed char polarization; /* physical polarization */
52 u16 address; /* physical cpu address */
53 };
54
55 DECLARE_PER_CPU(struct pcpu, pcpu_devices);
56
57 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
58
this_pcpu(void)59 static __always_inline struct pcpu *this_pcpu(void)
60 {
61 return (struct pcpu *)(get_lowcore()->pcpu);
62 }
63
set_cpu_flag(int flag)64 static __always_inline void set_cpu_flag(int flag)
65 {
66 set_bit(flag, &this_pcpu()->flags);
67 }
68
clear_cpu_flag(int flag)69 static __always_inline void clear_cpu_flag(int flag)
70 {
71 clear_bit(flag, &this_pcpu()->flags);
72 }
73
test_cpu_flag(int flag)74 static __always_inline bool test_cpu_flag(int flag)
75 {
76 return test_bit(flag, &this_pcpu()->flags);
77 }
78
test_and_set_cpu_flag(int flag)79 static __always_inline bool test_and_set_cpu_flag(int flag)
80 {
81 return test_and_set_bit(flag, &this_pcpu()->flags);
82 }
83
test_and_clear_cpu_flag(int flag)84 static __always_inline bool test_and_clear_cpu_flag(int flag)
85 {
86 return test_and_clear_bit(flag, &this_pcpu()->flags);
87 }
88
89 /*
90 * Test CIF flag of another CPU. The caller needs to ensure that
91 * CPU hotplug can not happen, e.g. by disabling preemption.
92 */
test_cpu_flag_of(int flag,int cpu)93 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
94 {
95 return test_bit(flag, &per_cpu(pcpu_devices, cpu).flags);
96 }
97
98 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
99
get_cpu_id(struct cpuid * ptr)100 static inline void get_cpu_id(struct cpuid *ptr)
101 {
102 asm volatile("stidp %0" : "=Q" (*ptr));
103 }
104
get_cpu_timer(void)105 static __always_inline unsigned long get_cpu_timer(void)
106 {
107 unsigned long timer;
108
109 asm volatile("stpt %[timer]" : [timer] "=Q" (timer));
110 return timer;
111 }
112
113 void s390_adjust_jiffies(void);
114 void s390_update_cpu_mhz(void);
115 void cpu_detect_mhz_feature(void);
116
117 extern const struct seq_operations cpuinfo_op;
118 extern void execve_tail(void);
119 unsigned long vdso_text_size(void);
120 unsigned long vdso_size(void);
121
122 /*
123 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
124 */
125
126 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \
127 _REGION3_SIZE : TASK_SIZE_MAX)
128 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
129 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
130 #define TASK_SIZE_MAX (-PAGE_SIZE)
131
132 #define VDSO_BASE (STACK_TOP + PAGE_SIZE)
133 #define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
134 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
135 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
136
137 #define HAVE_ARCH_PICK_MMAP_LAYOUT
138
139 #define __stackleak_poison __stackleak_poison
__stackleak_poison(unsigned long erase_low,unsigned long erase_high,unsigned long poison)140 static __always_inline void __stackleak_poison(unsigned long erase_low,
141 unsigned long erase_high,
142 unsigned long poison)
143 {
144 unsigned long tmp, count;
145
146 count = erase_high - erase_low;
147 if (!count)
148 return;
149 asm volatile(
150 " cghi %[count],8\n"
151 " je 2f\n"
152 " aghi %[count],-(8+1)\n"
153 " srlg %[tmp],%[count],8\n"
154 " ltgr %[tmp],%[tmp]\n"
155 " jz 1f\n"
156 "0: stg %[poison],0(%[addr])\n"
157 " mvc 8(256-8,%[addr]),0(%[addr])\n"
158 " la %[addr],256(%[addr])\n"
159 " brctg %[tmp],0b\n"
160 "1: stg %[poison],0(%[addr])\n"
161 " exrl %[count],3f\n"
162 " j 4f\n"
163 "2: stg %[poison],0(%[addr])\n"
164 " j 4f\n"
165 "3: mvc 8(1,%[addr]),0(%[addr])\n"
166 "4:\n"
167 : [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp)
168 : [poison] "d" (poison)
169 : "memory", "cc"
170 );
171 }
172
173 /*
174 * Thread structure
175 */
176 struct thread_struct {
177 unsigned int acrs[NUM_ACRS];
178 unsigned long ksp; /* kernel stack pointer */
179 unsigned long user_timer; /* task cputime in user space */
180 unsigned long guest_timer; /* task cputime in kvm guest */
181 unsigned long system_timer; /* task cputime in kernel space */
182 unsigned long hardirq_timer; /* task cputime in hardirq context */
183 unsigned long softirq_timer; /* task cputime in softirq context */
184 const sys_call_ptr_t *sys_call_table; /* system call table address */
185 union teid gmap_teid; /* address and flags of last gmap fault */
186 unsigned int gmap_int_code; /* int code of last gmap fault */
187 int ufpu_flags; /* user fpu flags */
188 int kfpu_flags; /* kernel fpu flags */
189
190 /* Per-thread information related to debugging */
191 struct per_regs per_user; /* User specified PER registers */
192 struct per_event per_event; /* Cause of the last PER trap */
193 unsigned long per_flags; /* Flags to control debug behavior */
194 unsigned int system_call; /* system call number in signal */
195 unsigned long last_break; /* last breaking-event-address. */
196 /* pfault_wait is used to block the process on a pfault event */
197 unsigned long pfault_wait;
198 struct list_head list;
199 /* cpu runtime instrumentation */
200 struct runtime_instr_cb *ri_cb;
201 struct gs_cb *gs_cb; /* Current guarded storage cb */
202 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
203 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
204 struct fpu ufpu; /* User FP and VX register save area */
205 struct fpu kfpu; /* Kernel FP and VX register save area */
206 };
207
208 /* Flag to disable transactions. */
209 #define PER_FLAG_NO_TE 1UL
210 /* Flag to enable random transaction aborts. */
211 #define PER_FLAG_TE_ABORT_RAND 2UL
212 /* Flag to specify random transaction abort mode:
213 * - abort each transaction at a random instruction before TEND if set.
214 * - abort random transactions at a random instruction if cleared.
215 */
216 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
217
218 typedef struct thread_struct thread_struct;
219
220 #define ARCH_MIN_TASKALIGN 8
221
222 #define INIT_THREAD { \
223 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
224 .last_break = 1, \
225 }
226
227 /*
228 * Do necessary setup to start up a new thread.
229 */
230 #define start_thread(regs, new_psw, new_stackp) do { \
231 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
232 regs->psw.addr = new_psw; \
233 regs->gprs[15] = new_stackp; \
234 execve_tail(); \
235 } while (0)
236
237 #define start_thread31(regs, new_psw, new_stackp) do { \
238 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
239 regs->psw.addr = new_psw; \
240 regs->gprs[15] = new_stackp; \
241 execve_tail(); \
242 } while (0)
243
244 struct task_struct;
245 struct mm_struct;
246 struct seq_file;
247 struct pt_regs;
248
249 void show_registers(struct pt_regs *regs);
250 void show_cacheinfo(struct seq_file *m);
251
252 /* Free guarded storage control block */
253 void guarded_storage_release(struct task_struct *tsk);
254 void gs_load_bc_cb(struct pt_regs *regs);
255
256 unsigned long __get_wchan(struct task_struct *p);
257 #define task_pt_regs(tsk) ((struct pt_regs *) \
258 (task_stack_page(tsk) + THREAD_SIZE) - 1)
259 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
260 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
261
262 /* Has task runtime instrumentation enabled ? */
263 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
264
265 /* avoid using global register due to gcc bug in versions < 8.4 */
266 #define current_stack_pointer (__current_stack_pointer())
267
__current_stack_pointer(void)268 static __always_inline unsigned long __current_stack_pointer(void)
269 {
270 unsigned long sp;
271
272 asm volatile("lgr %0,15" : "=d" (sp));
273 return sp;
274 }
275
on_thread_stack(void)276 static __always_inline bool on_thread_stack(void)
277 {
278 unsigned long ksp = get_lowcore()->kernel_stack;
279
280 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
281 }
282
stap(void)283 static __always_inline unsigned short stap(void)
284 {
285 unsigned short cpu_address;
286
287 asm volatile("stap %0" : "=Q" (cpu_address));
288 return cpu_address;
289 }
290
291 #define cpu_relax() barrier()
292
293 #define ECAG_CACHE_ATTRIBUTE 0
294 #define ECAG_CPU_ATTRIBUTE 1
295
__ecag(unsigned int asi,unsigned char parm)296 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
297 {
298 unsigned long val;
299
300 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
301 return val;
302 }
303
psw_set_key(unsigned int key)304 static inline void psw_set_key(unsigned int key)
305 {
306 asm volatile("spka 0(%0)" : : "d" (key));
307 }
308
309 /*
310 * Set PSW to specified value.
311 */
__load_psw(psw_t psw)312 static inline void __load_psw(psw_t psw)
313 {
314 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
315 }
316
317 /*
318 * Set PSW mask to specified value, while leaving the
319 * PSW addr pointing to the next instruction.
320 */
__load_psw_mask(unsigned long mask)321 static __always_inline void __load_psw_mask(unsigned long mask)
322 {
323 psw_t psw __uninitialized;
324 unsigned long addr;
325
326 psw.mask = mask;
327
328 asm volatile(
329 " larl %0,1f\n"
330 " stg %0,%1\n"
331 " lpswe %2\n"
332 "1:"
333 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
334 }
335
336 /*
337 * Extract current PSW mask
338 */
__extract_psw(void)339 static inline unsigned long __extract_psw(void)
340 {
341 unsigned int reg1, reg2;
342
343 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
344 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
345 }
346
__local_mcck_save(void)347 static inline unsigned long __local_mcck_save(void)
348 {
349 unsigned long mask = __extract_psw();
350
351 __load_psw_mask(mask & ~PSW_MASK_MCHECK);
352 return mask & PSW_MASK_MCHECK;
353 }
354
355 #define local_mcck_save(mflags) \
356 do { \
357 typecheck(unsigned long, mflags); \
358 mflags = __local_mcck_save(); \
359 } while (0)
360
local_mcck_restore(unsigned long mflags)361 static inline void local_mcck_restore(unsigned long mflags)
362 {
363 unsigned long mask = __extract_psw();
364
365 mask &= ~PSW_MASK_MCHECK;
366 __load_psw_mask(mask | mflags);
367 }
368
local_mcck_disable(void)369 static inline void local_mcck_disable(void)
370 {
371 __local_mcck_save();
372 }
373
local_mcck_enable(void)374 static inline void local_mcck_enable(void)
375 {
376 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
377 }
378
379 /*
380 * Rewind PSW instruction address by specified number of bytes.
381 */
__rewind_psw(psw_t psw,unsigned long ilc)382 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
383 {
384 unsigned long mask;
385
386 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
387 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
388 (1UL << 24) - 1;
389 return (psw.addr - ilc) & mask;
390 }
391
392 /*
393 * Function to drop a processor into disabled wait state
394 */
disabled_wait(void)395 static __always_inline void __noreturn disabled_wait(void)
396 {
397 psw_t psw;
398
399 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
400 psw.addr = _THIS_IP_;
401 __load_psw(psw);
402 while (1);
403 }
404
405 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
406
regs_irqs_disabled(struct pt_regs * regs)407 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
408 {
409 return arch_irqs_disabled_flags(regs->psw.mask);
410 }
411
bpon(void)412 static __always_inline void bpon(void)
413 {
414 asm_inline volatile(
415 ALTERNATIVE(" nop\n",
416 " .insn rrf,0xb2e80000,0,0,13,0\n",
417 ALT_SPEC(82))
418 );
419 }
420
421 #endif /* __ASSEMBLY__ */
422
423 #endif /* __ASM_S390_PROCESSOR_H */
424