1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
4 #ifdef __KERNEL__
5
6 /*
7 */
8
9 /* Check of existence of legacy devices */
10 extern int check_legacy_ioport(unsigned long base_port);
11 #define I8042_DATA_REG 0x60
12 #define FDC_BASE 0x3f0
13
14 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
15 extern struct pci_dev *isa_bridge_pcidev;
16 /*
17 * has legacy ISA devices ?
18 */
19 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
20 #endif
21
22 #include <linux/device.h>
23 #include <linux/compiler.h>
24 #include <linux/mm.h>
25 #include <asm/page.h>
26 #include <asm/byteorder.h>
27 #include <asm/synch.h>
28 #include <asm/delay.h>
29 #include <asm/mmiowb.h>
30 #include <asm/mmu.h>
31
32 #define SIO_CONFIG_RA 0x398
33 #define SIO_CONFIG_RD 0x399
34
35 /* 32 bits uses slightly different variables for the various IO
36 * bases. Most of this file only uses _IO_BASE though which we
37 * define properly based on the platform
38 */
39 #ifndef CONFIG_PCI
40 #define _IO_BASE POISON_POINTER_DELTA
41 #define _ISA_MEM_BASE 0
42 #define PCI_DRAM_OFFSET 0
43 #elif defined(CONFIG_PPC32)
44 #define _IO_BASE isa_io_base
45 #define _ISA_MEM_BASE isa_mem_base
46 #define PCI_DRAM_OFFSET pci_dram_offset
47 #else
48 #define _IO_BASE pci_io_base
49 #define _ISA_MEM_BASE isa_mem_base
50 #define PCI_DRAM_OFFSET 0
51 #endif
52
53 extern unsigned long isa_io_base;
54 extern unsigned long pci_io_base;
55 extern unsigned long pci_dram_offset;
56
57 extern resource_size_t isa_mem_base;
58
59 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
60 * is not set or addresses cannot be translated to MMIO. This is typically
61 * set when the platform supports "special" PIO accesses via a non memory
62 * mapped mechanism, and allows things like the early udbg UART code to
63 * function.
64 */
65 extern bool isa_io_special;
66
67 #ifdef CONFIG_PPC32
68 #ifdef CONFIG_PPC_INDIRECT_PIO
69 #error CONFIG_PPC_INDIRECT_PIO is not yet supported on 32 bits
70 #endif
71 #endif
72
73 /*
74 *
75 * Low level MMIO accessors
76 *
77 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
78 * specific and thus shouldn't be used in generic code. The accessors
79 * provided here are:
80 *
81 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
82 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
83 * _insb, _insw, _insl, _outsb, _outsw, _outsl
84 *
85 * Those operate directly on a kernel virtual address. Note that the prototype
86 * for the out_* accessors has the arguments in opposite order from the usual
87 * linux PCI accessors. Unlike those, they take the address first and the value
88 * next.
89 */
90
91 /* -mprefixed can generate offsets beyond range, fall back hack */
92 #ifdef CONFIG_PPC_KERNEL_PREFIXED
93 #define DEF_MMIO_IN_X(name, size, insn) \
94 static inline u##size name(const volatile u##size __iomem *addr) \
95 { \
96 u##size ret; \
97 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
98 : "=r" (ret) : "r" (addr) : "memory"); \
99 return ret; \
100 }
101
102 #define DEF_MMIO_OUT_X(name, size, insn) \
103 static inline void name(volatile u##size __iomem *addr, u##size val) \
104 { \
105 __asm__ __volatile__("sync;"#insn" %1,0,%0" \
106 : : "r" (addr), "r" (val) : "memory"); \
107 mmiowb_set_pending(); \
108 }
109
110 #define DEF_MMIO_IN_D(name, size, insn) \
111 static inline u##size name(const volatile u##size __iomem *addr) \
112 { \
113 u##size ret; \
114 __asm__ __volatile__("sync;"#insn" %0,0(%1);twi 0,%0,0;isync"\
115 : "=r" (ret) : "b" (addr) : "memory"); \
116 return ret; \
117 }
118
119 #define DEF_MMIO_OUT_D(name, size, insn) \
120 static inline void name(volatile u##size __iomem *addr, u##size val) \
121 { \
122 __asm__ __volatile__("sync;"#insn" %1,0(%0)" \
123 : : "b" (addr), "r" (val) : "memory"); \
124 mmiowb_set_pending(); \
125 }
126 #else
127 #define DEF_MMIO_IN_X(name, size, insn) \
128 static inline u##size name(const volatile u##size __iomem *addr) \
129 { \
130 u##size ret; \
131 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
132 : "=r" (ret) : "Z" (*addr) : "memory"); \
133 return ret; \
134 }
135
136 #define DEF_MMIO_OUT_X(name, size, insn) \
137 static inline void name(volatile u##size __iomem *addr, u##size val) \
138 { \
139 __asm__ __volatile__("sync;"#insn" %1,%y0" \
140 : "=Z" (*addr) : "r" (val) : "memory"); \
141 mmiowb_set_pending(); \
142 }
143
144 #define DEF_MMIO_IN_D(name, size, insn) \
145 static inline u##size name(const volatile u##size __iomem *addr) \
146 { \
147 u##size ret; \
148 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
149 : "=r" (ret) : "m<>" (*addr) : "memory"); \
150 return ret; \
151 }
152
153 #define DEF_MMIO_OUT_D(name, size, insn) \
154 static inline void name(volatile u##size __iomem *addr, u##size val) \
155 { \
156 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
157 : "=m<>" (*addr) : "r" (val) : "memory"); \
158 mmiowb_set_pending(); \
159 }
160 #endif
161
162 DEF_MMIO_IN_D(in_8, 8, lbz);
163 DEF_MMIO_OUT_D(out_8, 8, stb);
164
165 #ifdef __BIG_ENDIAN__
166 DEF_MMIO_IN_D(in_be16, 16, lhz);
167 DEF_MMIO_IN_D(in_be32, 32, lwz);
168 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
169 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
170
171 DEF_MMIO_OUT_D(out_be16, 16, sth);
172 DEF_MMIO_OUT_D(out_be32, 32, stw);
173 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
174 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
175 #else
176 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
177 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
178 DEF_MMIO_IN_D(in_le16, 16, lhz);
179 DEF_MMIO_IN_D(in_le32, 32, lwz);
180
181 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
182 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
183 DEF_MMIO_OUT_D(out_le16, 16, sth);
184 DEF_MMIO_OUT_D(out_le32, 32, stw);
185
186 #endif /* __BIG_ENDIAN */
187
188 #ifdef __powerpc64__
189
190 #ifdef __BIG_ENDIAN__
191 DEF_MMIO_OUT_D(out_be64, 64, std);
192 DEF_MMIO_IN_D(in_be64, 64, ld);
193
194 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)195 static inline u64 in_le64(const volatile u64 __iomem *addr)
196 {
197 return swab64(in_be64(addr));
198 }
199
out_le64(volatile u64 __iomem * addr,u64 val)200 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
201 {
202 out_be64(addr, swab64(val));
203 }
204 #else
205 DEF_MMIO_OUT_D(out_le64, 64, std);
206 DEF_MMIO_IN_D(in_le64, 64, ld);
207
208 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)209 static inline u64 in_be64(const volatile u64 __iomem *addr)
210 {
211 return swab64(in_le64(addr));
212 }
213
out_be64(volatile u64 __iomem * addr,u64 val)214 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
215 {
216 out_le64(addr, swab64(val));
217 }
218
219 #endif
220 #endif /* __powerpc64__ */
221
222 /*
223 * Low level IO stream instructions are defined out of line for now
224 */
225 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
226 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
227 extern void _insw(const volatile u16 __iomem *addr, void *buf, long count);
228 extern void _outsw(volatile u16 __iomem *addr, const void *buf, long count);
229 extern void _insl(const volatile u32 __iomem *addr, void *buf, long count);
230 extern void _outsl(volatile u32 __iomem *addr, const void *buf, long count);
231
232 /*
233 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
234 */
235
236 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
237 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
238 unsigned long n);
239 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
240 unsigned long n);
241
242 /*
243 *
244 * PCI and standard ISA accessors
245 *
246 * Those are globally defined linux accessors for devices on PCI or ISA
247 * busses. They follow the Linux defined semantics. The current implementation
248 * for PowerPC is as close as possible to the x86 version of these, and thus
249 * provides fairly heavy weight barriers for the non-raw versions
250 *
251 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_PIO
252 * is set allowing the platform to provide its own implementation of some
253 * of the accessors.
254 */
255
256 /*
257 * Include the EEH definitions when EEH is enabled only so they don't get
258 * in the way when building for 32 bits
259 */
260 #ifdef CONFIG_EEH
261 #include <asm/eeh.h>
262 #endif
263
264 #define _IO_PORT(port) ((volatile void __iomem *)(_IO_BASE + (port)))
265
266 #ifdef __powerpc64__
267 /*
268 * Real mode versions of raw accessors. Those instructions are only supposed
269 * to be used in hypervisor real mode as per the architecture spec.
270 */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)271 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
272 {
273 __asm__ __volatile__(".machine push; \
274 .machine power6; \
275 stbcix %0,0,%1; \
276 .machine pop;"
277 : : "r" (val), "r" (paddr) : "memory");
278 }
279
__raw_rm_writew(u16 val,volatile void __iomem * paddr)280 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
281 {
282 __asm__ __volatile__(".machine push; \
283 .machine power6; \
284 sthcix %0,0,%1; \
285 .machine pop;"
286 : : "r" (val), "r" (paddr) : "memory");
287 }
288
__raw_rm_writel(u32 val,volatile void __iomem * paddr)289 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
290 {
291 __asm__ __volatile__(".machine push; \
292 .machine power6; \
293 stwcix %0,0,%1; \
294 .machine pop;"
295 : : "r" (val), "r" (paddr) : "memory");
296 }
297
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)298 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
299 {
300 __asm__ __volatile__(".machine push; \
301 .machine power6; \
302 stdcix %0,0,%1; \
303 .machine pop;"
304 : : "r" (val), "r" (paddr) : "memory");
305 }
306
__raw_rm_writeq_be(u64 val,volatile void __iomem * paddr)307 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
308 {
309 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
310 }
311
__raw_rm_readb(volatile void __iomem * paddr)312 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
313 {
314 u8 ret;
315 __asm__ __volatile__(".machine push; \
316 .machine power6; \
317 lbzcix %0,0, %1; \
318 .machine pop;"
319 : "=r" (ret) : "r" (paddr) : "memory");
320 return ret;
321 }
322
__raw_rm_readw(volatile void __iomem * paddr)323 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
324 {
325 u16 ret;
326 __asm__ __volatile__(".machine push; \
327 .machine power6; \
328 lhzcix %0,0, %1; \
329 .machine pop;"
330 : "=r" (ret) : "r" (paddr) : "memory");
331 return ret;
332 }
333
__raw_rm_readl(volatile void __iomem * paddr)334 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
335 {
336 u32 ret;
337 __asm__ __volatile__(".machine push; \
338 .machine power6; \
339 lwzcix %0,0, %1; \
340 .machine pop;"
341 : "=r" (ret) : "r" (paddr) : "memory");
342 return ret;
343 }
344
__raw_rm_readq(volatile void __iomem * paddr)345 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
346 {
347 u64 ret;
348 __asm__ __volatile__(".machine push; \
349 .machine power6; \
350 ldcix %0,0, %1; \
351 .machine pop;"
352 : "=r" (ret) : "r" (paddr) : "memory");
353 return ret;
354 }
355 #endif /* __powerpc64__ */
356
357 /*
358 *
359 * PCI PIO and MMIO accessors.
360 *
361 *
362 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
363 * machine checks (which they occasionally do when probing non existing
364 * IO ports on some platforms, like PowerMac and 8xx).
365 * I always found it to be of dubious reliability and I am tempted to get
366 * rid of it one of these days. So if you think it's important to keep it,
367 * please voice up asap. We never had it for 64 bits and I do not intend
368 * to port it over
369 */
370
371 #ifdef CONFIG_PPC32
372
373 #define __do_in_asm(name, op) \
374 static inline unsigned int name(unsigned int port) \
375 { \
376 unsigned int x; \
377 __asm__ __volatile__( \
378 "sync\n" \
379 "0:" op " %0,0,%1\n" \
380 "1: twi 0,%0,0\n" \
381 "2: isync\n" \
382 "3: nop\n" \
383 "4:\n" \
384 ".section .fixup,\"ax\"\n" \
385 "5: li %0,-1\n" \
386 " b 4b\n" \
387 ".previous\n" \
388 EX_TABLE(0b, 5b) \
389 EX_TABLE(1b, 5b) \
390 EX_TABLE(2b, 5b) \
391 EX_TABLE(3b, 5b) \
392 : "=&r" (x) \
393 : "r" (port + _IO_BASE) \
394 : "memory"); \
395 return x; \
396 }
397
398 #define __do_out_asm(name, op) \
399 static inline void name(unsigned int val, unsigned int port) \
400 { \
401 __asm__ __volatile__( \
402 "sync\n" \
403 "0:" op " %0,0,%1\n" \
404 "1: sync\n" \
405 "2:\n" \
406 EX_TABLE(0b, 2b) \
407 EX_TABLE(1b, 2b) \
408 : : "r" (val), "r" (port + _IO_BASE) \
409 : "memory"); \
410 }
411
412 __do_in_asm(_rec_inb, "lbzx")
413 __do_in_asm(_rec_inw, "lhbrx")
414 __do_in_asm(_rec_inl, "lwbrx")
415 __do_out_asm(_rec_outb, "stbx")
416 __do_out_asm(_rec_outw, "sthbrx")
417 __do_out_asm(_rec_outl, "stwbrx")
418
419 #endif /* CONFIG_PPC32 */
420
421 /* The "__do_*" operations below provide the actual "base" implementation
422 * for each of the defined accessors. Some of them use the out_* functions
423 * directly, some of them still use EEH, though we might change that in the
424 * future. Those macros below provide the necessary argument swapping and
425 * handling of the IO base for PIO.
426 *
427 * They are themselves used by the macros that define the actual accessors
428 * and can be used by the hooks if any.
429 *
430 * Note that PIO operations are always defined in terms of their corresonding
431 * MMIO operations. That allows platforms like iSeries who want to modify the
432 * behaviour of both to only hook on the MMIO version and get both. It's also
433 * possible to hook directly at the toplevel PIO operation if they have to
434 * be handled differently
435 */
436
437 #ifdef CONFIG_EEH
438 #define __do_readb(addr) eeh_readb(addr)
439 #define __do_readw(addr) eeh_readw(addr)
440 #define __do_readl(addr) eeh_readl(addr)
441 #define __do_readq(addr) eeh_readq(addr)
442 #define __do_readw_be(addr) eeh_readw_be(addr)
443 #define __do_readl_be(addr) eeh_readl_be(addr)
444 #define __do_readq_be(addr) eeh_readq_be(addr)
445 #else /* CONFIG_EEH */
446 #define __do_readb(addr) in_8(addr)
447 #define __do_readw(addr) in_le16(addr)
448 #define __do_readl(addr) in_le32(addr)
449 #define __do_readq(addr) in_le64(addr)
450 #define __do_readw_be(addr) in_be16(addr)
451 #define __do_readl_be(addr) in_be32(addr)
452 #define __do_readq_be(addr) in_be64(addr)
453 #endif /* !defined(CONFIG_EEH) */
454
455 #ifdef CONFIG_PPC32
456 #define __do_outb(val, port) _rec_outb(val, port)
457 #define __do_outw(val, port) _rec_outw(val, port)
458 #define __do_outl(val, port) _rec_outl(val, port)
459 #define __do_inb(port) _rec_inb(port)
460 #define __do_inw(port) _rec_inw(port)
461 #define __do_inl(port) _rec_inl(port)
462 #else /* CONFIG_PPC32 */
463 #define __do_outb(val, port) writeb(val,_IO_PORT(port));
464 #define __do_outw(val, port) writew(val,_IO_PORT(port));
465 #define __do_outl(val, port) writel(val,_IO_PORT(port));
466 #define __do_inb(port) readb(_IO_PORT(port));
467 #define __do_inw(port) readw(_IO_PORT(port));
468 #define __do_inl(port) readl(_IO_PORT(port));
469 #endif /* !CONFIG_PPC32 */
470
471 #ifdef CONFIG_EEH
472 #define __do_readsb(a, b, n) eeh_readsb(a, (b), (n))
473 #define __do_readsw(a, b, n) eeh_readsw(a, (b), (n))
474 #define __do_readsl(a, b, n) eeh_readsl(a, (b), (n))
475 #else /* CONFIG_EEH */
476 #define __do_readsb(a, b, n) _insb(a, (b), (n))
477 #define __do_readsw(a, b, n) _insw(a, (b), (n))
478 #define __do_readsl(a, b, n) _insl(a, (b), (n))
479 #endif /* !CONFIG_EEH */
480 #define __do_writesb(a, b, n) _outsb(a, (b), (n))
481 #define __do_writesw(a, b, n) _outsw(a, (b), (n))
482 #define __do_writesl(a, b, n) _outsl(a, (b), (n))
483
484 #define __do_insb(p, b, n) readsb(_IO_PORT(p), (b), (n))
485 #define __do_insw(p, b, n) readsw(_IO_PORT(p), (b), (n))
486 #define __do_insl(p, b, n) readsl(_IO_PORT(p), (b), (n))
487 #define __do_outsb(p, b, n) writesb(_IO_PORT(p),(b),(n))
488 #define __do_outsw(p, b, n) writesw(_IO_PORT(p),(b),(n))
489 #define __do_outsl(p, b, n) writesl(_IO_PORT(p),(b),(n))
490
491 #ifdef CONFIG_EEH
492 #define __do_memcpy_fromio(dst, src, n) \
493 eeh_memcpy_fromio(dst, src, n)
494 #else /* CONFIG_EEH */
495 #define __do_memcpy_fromio(dst, src, n) \
496 _memcpy_fromio(dst, src, n)
497 #endif /* !CONFIG_EEH */
498
readb(const volatile void __iomem * addr)499 static inline u8 readb(const volatile void __iomem *addr)
500 {
501 return __do_readb(addr);
502 }
503 #define readb readb
504
readw(const volatile void __iomem * addr)505 static inline u16 readw(const volatile void __iomem *addr)
506 {
507 return __do_readw(addr);
508 }
509 #define readw readw
510
readl(const volatile void __iomem * addr)511 static inline u32 readl(const volatile void __iomem *addr)
512 {
513 return __do_readl(addr);
514 }
515 #define readl readl
516
readw_be(const volatile void __iomem * addr)517 static inline u16 readw_be(const volatile void __iomem *addr)
518 {
519 return __do_readw_be(addr);
520 }
521
readl_be(const volatile void __iomem * addr)522 static inline u32 readl_be(const volatile void __iomem *addr)
523 {
524 return __do_readl_be(addr);
525 }
526
writeb(u8 val,volatile void __iomem * addr)527 static inline void writeb(u8 val, volatile void __iomem *addr)
528 {
529 out_8(addr, val);
530 }
531 #define writeb writeb
532
writew(u16 val,volatile void __iomem * addr)533 static inline void writew(u16 val, volatile void __iomem *addr)
534 {
535 out_le16(addr, val);
536 }
537 #define writew writew
538
writel(u32 val,volatile void __iomem * addr)539 static inline void writel(u32 val, volatile void __iomem *addr)
540 {
541 out_le32(addr, val);
542 }
543 #define writel writel
544
writew_be(u16 val,volatile void __iomem * addr)545 static inline void writew_be(u16 val, volatile void __iomem *addr)
546 {
547 out_be16(addr, val);
548 }
549
writel_be(u32 val,volatile void __iomem * addr)550 static inline void writel_be(u32 val, volatile void __iomem *addr)
551 {
552 out_be32(addr, val);
553 }
554
readsb(const volatile void __iomem * a,void * b,unsigned long c)555 static inline void readsb(const volatile void __iomem *a, void *b, unsigned long c)
556 {
557 __do_readsb(a, b, c);
558 }
559 #define readsb readsb
560
readsw(const volatile void __iomem * a,void * b,unsigned long c)561 static inline void readsw(const volatile void __iomem *a, void *b, unsigned long c)
562 {
563 __do_readsw(a, b, c);
564 }
565 #define readsw readsw
566
readsl(const volatile void __iomem * a,void * b,unsigned long c)567 static inline void readsl(const volatile void __iomem *a, void *b, unsigned long c)
568 {
569 __do_readsl(a, b, c);
570 }
571 #define readsl readsl
572
writesb(volatile void __iomem * a,const void * b,unsigned long c)573 static inline void writesb(volatile void __iomem *a, const void *b, unsigned long c)
574 {
575 __do_writesb(a, b, c);
576 }
577 #define writesb writesb
578
writesw(volatile void __iomem * a,const void * b,unsigned long c)579 static inline void writesw(volatile void __iomem *a, const void *b, unsigned long c)
580 {
581 __do_writesw(a, b, c);
582 }
583 #define writesw writesw
584
writesl(volatile void __iomem * a,const void * b,unsigned long c)585 static inline void writesl(volatile void __iomem *a, const void *b, unsigned long c)
586 {
587 __do_writesl(a, b, c);
588 }
589 #define writesl writesl
590
memset_io(volatile void __iomem * a,int c,unsigned long n)591 static inline void memset_io(volatile void __iomem *a, int c, unsigned long n)
592 {
593 _memset_io(a, c, n);
594 }
595 #define memset_io memset_io
596
memcpy_fromio(void * d,const volatile void __iomem * s,unsigned long n)597 static inline void memcpy_fromio(void *d, const volatile void __iomem *s, unsigned long n)
598 {
599 __do_memcpy_fromio(d, s, n);
600 }
601 #define memcpy_fromio memcpy_fromio
602
memcpy_toio(volatile void __iomem * d,const void * s,unsigned long n)603 static inline void memcpy_toio(volatile void __iomem *d, const void *s, unsigned long n)
604 {
605 _memcpy_toio(d, s, n);
606 }
607 #define memcpy_toio memcpy_toio
608
609 #ifdef __powerpc64__
readq(const volatile void __iomem * addr)610 static inline u64 readq(const volatile void __iomem *addr)
611 {
612 return __do_readq(addr);
613 }
614
readq_be(const volatile void __iomem * addr)615 static inline u64 readq_be(const volatile void __iomem *addr)
616 {
617 return __do_readq_be(addr);
618 }
619
writeq(u64 val,volatile void __iomem * addr)620 static inline void writeq(u64 val, volatile void __iomem *addr)
621 {
622 out_le64(addr, val);
623 }
624
writeq_be(u64 val,volatile void __iomem * addr)625 static inline void writeq_be(u64 val, volatile void __iomem *addr)
626 {
627 out_be64(addr, val);
628 }
629 #endif /* __powerpc64__ */
630
631 #ifdef CONFIG_PPC_INDIRECT_PIO
632 #define DEF_PCI_HOOK(x) x
633 #else
634 #define DEF_PCI_HOOK(x) NULL
635 #endif
636
637 /* Structure containing all the hooks */
638 extern struct ppc_pci_io {
639
640 #define DEF_PCI_AC_RET(name, ret, at, al) ret (*name) at;
641 #define DEF_PCI_AC_NORET(name, at, al) void (*name) at;
642
643 #include <asm/io-defs.h>
644
645 #undef DEF_PCI_AC_RET
646 #undef DEF_PCI_AC_NORET
647
648 } ppc_pci_io;
649
650 /* The inline wrappers */
651 #define DEF_PCI_AC_RET(name, ret, at, al) \
652 static inline ret name at \
653 { \
654 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
655 return ppc_pci_io.name al; \
656 return __do_##name al; \
657 }
658
659 #define DEF_PCI_AC_NORET(name, at, al) \
660 static inline void name at \
661 { \
662 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
663 ppc_pci_io.name al; \
664 else \
665 __do_##name al; \
666 }
667
668 #include <asm/io-defs.h>
669
670 #undef DEF_PCI_AC_RET
671 #undef DEF_PCI_AC_NORET
672
673 // Signal to asm-generic/io.h that we have implemented these.
674 #define inb inb
675 #define inw inw
676 #define inl inl
677 #define outb outb
678 #define outw outw
679 #define outl outl
680 #define insb insb
681 #define insw insw
682 #define insl insl
683 #define outsb outsb
684 #define outsw outsw
685 #define outsl outsl
686 #ifdef __powerpc64__
687 #define readq readq
688 #define writeq writeq
689 #endif
690
691 /*
692 * We don't do relaxed operations yet, at least not with this semantic
693 */
694 #define readb_relaxed(addr) readb(addr)
695 #define readw_relaxed(addr) readw(addr)
696 #define readl_relaxed(addr) readl(addr)
697 #define readq_relaxed(addr) readq(addr)
698 #define writeb_relaxed(v, addr) writeb(v, addr)
699 #define writew_relaxed(v, addr) writew(v, addr)
700 #define writel_relaxed(v, addr) writel(v, addr)
701 #define writeq_relaxed(v, addr) writeq(v, addr)
702
703 #ifndef CONFIG_GENERIC_IOMAP
704 /*
705 * Here comes the implementation of the IOMAP interfaces.
706 */
ioread16be(const void __iomem * addr)707 static inline unsigned int ioread16be(const void __iomem *addr)
708 {
709 return readw_be(addr);
710 }
711 #define ioread16be ioread16be
712
ioread32be(const void __iomem * addr)713 static inline unsigned int ioread32be(const void __iomem *addr)
714 {
715 return readl_be(addr);
716 }
717 #define ioread32be ioread32be
718
719 #ifdef __powerpc64__
ioread64be(const void __iomem * addr)720 static inline u64 ioread64be(const void __iomem *addr)
721 {
722 return readq_be(addr);
723 }
724 #define ioread64be ioread64be
725 #endif /* __powerpc64__ */
726
iowrite16be(u16 val,void __iomem * addr)727 static inline void iowrite16be(u16 val, void __iomem *addr)
728 {
729 writew_be(val, addr);
730 }
731 #define iowrite16be iowrite16be
732
iowrite32be(u32 val,void __iomem * addr)733 static inline void iowrite32be(u32 val, void __iomem *addr)
734 {
735 writel_be(val, addr);
736 }
737 #define iowrite32be iowrite32be
738
739 #ifdef __powerpc64__
iowrite64be(u64 val,void __iomem * addr)740 static inline void iowrite64be(u64 val, void __iomem *addr)
741 {
742 writeq_be(val, addr);
743 }
744 #define iowrite64be iowrite64be
745 #endif /* __powerpc64__ */
746
747 struct pci_dev;
748 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
749 #define pci_iounmap pci_iounmap
750 void __iomem *ioport_map(unsigned long port, unsigned int len);
751 #define ioport_map ioport_map
752 #endif
753
iosync(void)754 static inline void iosync(void)
755 {
756 __asm__ __volatile__ ("sync" : : : "memory");
757 }
758
759 /* Enforce in-order execution of data I/O.
760 * No distinction between read/write on PPC; use eieio for all three.
761 * Those are fairly week though. They don't provide a barrier between
762 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
763 * they only provide barriers between 2 __raw MMIO operations and
764 * possibly break write combining.
765 */
766 #define iobarrier_rw() eieio()
767 #define iobarrier_r() eieio()
768 #define iobarrier_w() eieio()
769
770
771 /*
772 * output pause versions need a delay at least for the
773 * w83c105 ide controller in a p610.
774 */
775 #define inb_p(port) inb(port)
776 #define outb_p(val, port) (udelay(1), outb((val), (port)))
777 #define inw_p(port) inw(port)
778 #define outw_p(val, port) (udelay(1), outw((val), (port)))
779 #define inl_p(port) inl(port)
780 #define outl_p(val, port) (udelay(1), outl((val), (port)))
781
782
783 #define IO_SPACE_LIMIT ~(0UL)
784
785 /**
786 * ioremap - map bus memory into CPU space
787 * @address: bus address of the memory
788 * @size: size of the resource to map
789 *
790 * ioremap performs a platform specific sequence of operations to
791 * make bus memory CPU accessible via the readb/readw/readl/writeb/
792 * writew/writel functions and the other mmio helpers. The returned
793 * address is not guaranteed to be usable directly as a virtual
794 * address.
795 *
796 * We provide a few variations of it:
797 *
798 * * ioremap is the standard one and provides non-cacheable guarded mappings
799 * and can be hooked by the platform via ppc_md
800 *
801 * * ioremap_prot allows to specify the page flags as an argument and can
802 * also be hooked by the platform via ppc_md.
803 *
804 * * ioremap_wc enables write combining
805 *
806 * * ioremap_wt enables write through
807 *
808 * * ioremap_coherent maps coherent cached memory
809 *
810 * * iounmap undoes such a mapping and can be hooked
811 *
812 * * __ioremap_caller is the same as above but takes an explicit caller
813 * reference rather than using __builtin_return_address(0)
814 *
815 */
816 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
817 #define ioremap ioremap
818 #define ioremap_prot ioremap_prot
819 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
820 #define ioremap_wc ioremap_wc
821
822 #ifdef CONFIG_PPC32
823 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
824 #define ioremap_wt ioremap_wt
825 #endif
826
827 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
828 #define ioremap_cache(addr, size) \
829 ioremap_prot((addr), (size), PAGE_KERNEL)
830
831 #define iounmap iounmap
832
833 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
834
835 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
836 unsigned long size, pgprot_t prot);
837
838 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
839 pgprot_t prot, void *caller);
840
841 /*
842 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
843 * which needs some additional definitions here. They basically allow PIO
844 * space overall to be 1GB. This will work as long as we never try to use
845 * iomap to map MMIO below 1GB which should be fine on ppc64
846 */
847 #define HAVE_ARCH_PIO_SIZE 1
848 #define PIO_OFFSET 0x00000000UL
849 #define PIO_MASK (FULL_IO_SIZE - 1)
850 #define PIO_RESERVED (FULL_IO_SIZE)
851
852 #define mmio_read16be(addr) readw_be(addr)
853 #define mmio_read32be(addr) readl_be(addr)
854 #define mmio_read64be(addr) readq_be(addr)
855 #define mmio_write16be(val, addr) writew_be(val, addr)
856 #define mmio_write32be(val, addr) writel_be(val, addr)
857 #define mmio_write64be(val, addr) writeq_be(val, addr)
858 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
859 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
860 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
861 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
862 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
863 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
864
865 /**
866 * virt_to_phys - map virtual addresses to physical
867 * @address: address to remap
868 *
869 * The returned physical address is the physical (CPU) mapping for
870 * the memory address given. It is only valid to use this function on
871 * addresses directly mapped or allocated via kmalloc.
872 *
873 * This function does not give bus mappings for DMA transfers. In
874 * almost all conceivable cases a device driver should not be using
875 * this function
876 */
virt_to_phys(const volatile void * address)877 static inline unsigned long virt_to_phys(const volatile void * address)
878 {
879 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
880
881 return __pa((unsigned long)address);
882 }
883 #define virt_to_phys virt_to_phys
884
885 /**
886 * phys_to_virt - map physical address to virtual
887 * @address: address to remap
888 *
889 * The returned virtual address is a current CPU mapping for
890 * the memory address given. It is only valid to use this function on
891 * addresses that have a kernel mapping
892 *
893 * This function does not handle bus mappings for DMA transfers. In
894 * almost all conceivable cases a device driver should not be using
895 * this function
896 */
phys_to_virt(unsigned long address)897 static inline void * phys_to_virt(unsigned long address)
898 {
899 return (void *)__va(address);
900 }
901 #define phys_to_virt phys_to_virt
902
903 /*
904 * 32 bits still uses virt_to_bus() for its implementation of DMA
905 * mappings se we have to keep it defined here. We also have some old
906 * drivers (shame shame shame) that use bus_to_virt() and haven't been
907 * fixed yet so I need to define it here.
908 */
909 #ifdef CONFIG_PPC32
910
virt_to_bus(volatile void * address)911 static inline unsigned long virt_to_bus(volatile void * address)
912 {
913 if (address == NULL)
914 return 0;
915 return __pa(address) + PCI_DRAM_OFFSET;
916 }
917 #define virt_to_bus virt_to_bus
918
bus_to_virt(unsigned long address)919 static inline void * bus_to_virt(unsigned long address)
920 {
921 if (address == 0)
922 return NULL;
923 return __va(address - PCI_DRAM_OFFSET);
924 }
925 #define bus_to_virt bus_to_virt
926
927 #endif /* CONFIG_PPC32 */
928
929 /* access ports */
930 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
931 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
932
933 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
934 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
935
936 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
937 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
938
939 /* Clear and set bits in one shot. These macros can be used to clear and
940 * set multiple bits in a register using a single read-modify-write. These
941 * macros can also be used to set a multiple-bit bit pattern using a mask,
942 * by specifying the mask in the 'clear' parameter and the new bit pattern
943 * in the 'set' parameter.
944 */
945
946 #define clrsetbits(type, addr, clear, set) \
947 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
948
949 #ifdef __powerpc64__
950 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
951 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
952 #endif
953
954 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
955 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
956
957 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
958 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
959
960 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
961
962 #include <asm-generic/io.h>
963
964 #ifdef __powerpc64__
__raw_writeq_be(unsigned long v,volatile void __iomem * addr)965 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
966 {
967 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
968 }
969 #define __raw_writeq_be __raw_writeq_be
970 #endif // __powerpc64__
971
972 #endif /* __KERNEL__ */
973
974 #endif /* _ASM_POWERPC_IO_H */
975