1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2013 Imagination Technologies
4  * Author: Paul Burton <paul.burton@mips.com>
5  */
6 
7 #include <linux/cpu.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/memblock.h>
11 #include <linux/sched/task_stack.h>
12 #include <linux/sched/hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/smp.h>
15 #include <linux/types.h>
16 #include <linux/irq.h>
17 
18 #include <asm/bcache.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mips_mt.h>
21 #include <asm/mipsregs.h>
22 #include <asm/pm-cps.h>
23 #include <asm/r4kcache.h>
24 #include <asm/regdef.h>
25 #include <asm/smp.h>
26 #include <asm/smp-cps.h>
27 #include <asm/time.h>
28 #include <asm/uasm.h>
29 
30 #define BEV_VEC_SIZE	0x500
31 #define BEV_VEC_ALIGN	0x1000
32 
33 enum label_id {
34 	label_not_nmi = 1,
35 };
36 
37 UASM_L_LA(_not_nmi)
38 
39 static u64 core_entry_reg;
40 static phys_addr_t cps_vec_pa;
41 
42 struct cluster_boot_config *mips_cps_cluster_bootcfg;
43 
power_up_other_cluster(unsigned int cluster)44 static void power_up_other_cluster(unsigned int cluster)
45 {
46 	u32 stat, seq_state;
47 	unsigned int timeout;
48 
49 	mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0,
50 			   CM_GCR_Cx_OTHER_BLOCK_LOCAL);
51 	stat = read_cpc_co_stat_conf();
52 	mips_cm_unlock_other();
53 
54 	seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
55 	seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
56 	if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5)
57 		return;
58 
59 	/* Set endianness & power up the CM */
60 	mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
61 	write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN));
62 	write_cpc_redir_pwrup_ctl(1);
63 	mips_cm_unlock_other();
64 
65 	/* Wait for the CM to start up */
66 	timeout = 1000;
67 	mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0,
68 			   CM_GCR_Cx_OTHER_BLOCK_LOCAL);
69 	while (1) {
70 		stat = read_cpc_co_stat_conf();
71 		seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
72 		seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
73 		if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5)
74 			break;
75 
76 		if (timeout) {
77 			mdelay(1);
78 			timeout--;
79 		} else {
80 			pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n",
81 				cluster, stat);
82 			mdelay(1000);
83 		}
84 	}
85 
86 	mips_cm_unlock_other();
87 }
88 
core_vpe_count(unsigned int cluster,unsigned core)89 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
90 {
91 	return min(smp_max_threads, mips_cps_numvps(cluster, core));
92 }
93 
mips_cps_build_core_entry(void * addr)94 static void __init *mips_cps_build_core_entry(void *addr)
95 {
96 	extern void (*nmi_handler)(void);
97 	u32 *p = addr;
98 	u32 val;
99 	struct uasm_label labels[2];
100 	struct uasm_reloc relocs[2];
101 	struct uasm_label *l = labels;
102 	struct uasm_reloc *r = relocs;
103 
104 	memset(labels, 0, sizeof(labels));
105 	memset(relocs, 0, sizeof(relocs));
106 
107 	uasm_i_mfc0(&p, GPR_K0, C0_STATUS);
108 	UASM_i_LA(&p, GPR_T9, ST0_NMI);
109 	uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9);
110 
111 	uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi);
112 	uasm_i_nop(&p);
113 	UASM_i_LA(&p, GPR_K0, (long)&nmi_handler);
114 
115 	uasm_l_not_nmi(&l, p);
116 
117 	val = CAUSEF_IV;
118 	uasm_i_lui(&p, GPR_K0, val >> 16);
119 	uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);
120 	uasm_i_mtc0(&p, GPR_K0, C0_CAUSE);
121 	val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64;
122 	uasm_i_lui(&p, GPR_K0, val >> 16);
123 	uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);
124 	uasm_i_mtc0(&p, GPR_K0, C0_STATUS);
125 	uasm_i_ehb(&p);
126 	uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK);
127 	UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base);
128 #if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT)
129 	UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot)));
130 #else
131 	UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot)));
132 #endif
133 	uasm_i_jr(&p, GPR_T9);
134 	uasm_i_nop(&p);
135 
136 	uasm_resolve_relocs(relocs, labels);
137 
138 	return p;
139 }
140 
check_64bit_reset(void)141 static bool __init check_64bit_reset(void)
142 {
143 	bool cx_64bit_reset = false;
144 
145 	mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
146 	write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE);
147 	if ((read_gcr_co_reset64_base() & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) ==
148 	    CM_GCR_Cx_RESET64_BASE_BEVEXCBASE)
149 		cx_64bit_reset = true;
150 	mips_cm_unlock_other();
151 
152 	return cx_64bit_reset;
153 }
154 
allocate_cps_vecs(void)155 static int __init allocate_cps_vecs(void)
156 {
157 	/* Try to allocate in KSEG1 first */
158 	cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
159 						0x0, CSEGX_SIZE - 1);
160 
161 	if (cps_vec_pa)
162 		core_entry_reg = CKSEG1ADDR(cps_vec_pa) &
163 					CM_GCR_Cx_RESET_BASE_BEVEXCBASE;
164 
165 	if (!cps_vec_pa && mips_cm_is64) {
166 		phys_addr_t end;
167 
168 		if (check_64bit_reset()) {
169 			pr_info("VP Local Reset Exception Base support 47 bits address\n");
170 			end = MEMBLOCK_ALLOC_ANYWHERE;
171 		} else {
172 			end = SZ_4G - 1;
173 		}
174 		cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 0, end);
175 		if (cps_vec_pa) {
176 			if (check_64bit_reset())
177 				core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) |
178 					CM_GCR_Cx_RESET_BASE_MODE;
179 			else
180 				core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) |
181 					CM_GCR_Cx_RESET_BASE_MODE;
182 		}
183 	}
184 
185 	if (!cps_vec_pa)
186 		return -ENOMEM;
187 
188 	return 0;
189 }
190 
setup_cps_vecs(void)191 static void __init setup_cps_vecs(void)
192 {
193 	void *cps_vec;
194 
195 	cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa);
196 	mips_cps_build_core_entry(cps_vec);
197 
198 	memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
199 	memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
200 	memcpy(cps_vec + 0x300, &excep_cache, 0x80);
201 	memcpy(cps_vec + 0x380, &excep_genex, 0x80);
202 	memcpy(cps_vec + 0x400, &excep_intex, 0x80);
203 	memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
204 
205 	/* Make sure no prefetched data in cache */
206 	blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE);
207 	bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE);
208 	__sync();
209 }
210 
cps_smp_setup(void)211 static void __init cps_smp_setup(void)
212 {
213 	unsigned int nclusters, ncores, nvpes, core_vpes;
214 	int cl, c, v;
215 
216 	/* Detect & record VPE topology */
217 	nvpes = 0;
218 	nclusters = mips_cps_numclusters();
219 	pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
220 	for (cl = 0; cl < nclusters; cl++) {
221 		if (cl > 0)
222 			pr_cont(",");
223 		pr_cont("{");
224 
225 		if (mips_cm_revision() >= CM_REV_CM3_5)
226 			power_up_other_cluster(cl);
227 
228 		ncores = mips_cps_numcores(cl);
229 		for (c = 0; c < ncores; c++) {
230 			core_vpes = core_vpe_count(cl, c);
231 
232 			if (c > 0)
233 				pr_cont(",");
234 			pr_cont("%u", core_vpes);
235 
236 			/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
237 			if (!cl && !c)
238 				smp_num_siblings = core_vpes;
239 
240 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
241 				cpu_set_cluster(&cpu_data[nvpes + v], cl);
242 				cpu_set_core(&cpu_data[nvpes + v], c);
243 				cpu_set_vpe_id(&cpu_data[nvpes + v], v);
244 			}
245 
246 			nvpes += core_vpes;
247 		}
248 
249 		pr_cont("}");
250 	}
251 	pr_cont(" total %u\n", nvpes);
252 
253 	/* Indicate present CPUs (CPU being synonymous with VPE) */
254 	for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
255 		set_cpu_possible(v, true);
256 		set_cpu_present(v, true);
257 		__cpu_number_map[v] = v;
258 		__cpu_logical_map[v] = v;
259 	}
260 
261 	/* Set a coherent default CCA (CWB) */
262 	change_c0_config(CONF_CM_CMASK, 0x5);
263 
264 	/* Initialise core 0 */
265 	mips_cps_core_init();
266 
267 	/* Make core 0 coherent with everything */
268 	write_gcr_cl_coherence(0xff);
269 
270 	if (allocate_cps_vecs())
271 		pr_err("Failed to allocate CPS vectors\n");
272 
273 	if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
274 		write_gcr_bev_base(core_entry_reg);
275 
276 #ifdef CONFIG_MIPS_MT_FPAFF
277 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
278 	if (cpu_has_fpu)
279 		cpumask_set_cpu(0, &mt_fpu_cpumask);
280 #endif /* CONFIG_MIPS_MT_FPAFF */
281 }
282 
cps_prepare_cpus(unsigned int max_cpus)283 static void __init cps_prepare_cpus(unsigned int max_cpus)
284 {
285 	unsigned int nclusters, ncores, core_vpes, c, cl, cca;
286 	bool cca_unsuitable, cores_limited;
287 	struct cluster_boot_config *cluster_bootcfg;
288 	struct core_boot_config *core_bootcfg;
289 
290 	mips_mt_set_cpuoptions();
291 
292 	if (!core_entry_reg) {
293 		pr_err("core_entry address unsuitable, disabling smp-cps\n");
294 		goto err_out;
295 	}
296 
297 	/* Detect whether the CCA is unsuited to multi-core SMP */
298 	cca = read_c0_config() & CONF_CM_CMASK;
299 	switch (cca) {
300 	case 0x4: /* CWBE */
301 	case 0x5: /* CWB */
302 		/* The CCA is coherent, multi-core is fine */
303 		cca_unsuitable = false;
304 		break;
305 
306 	default:
307 		/* CCA is not coherent, multi-core is not usable */
308 		cca_unsuitable = true;
309 	}
310 
311 	/* Warn the user if the CCA prevents multi-core */
312 	cores_limited = false;
313 	if (cca_unsuitable || cpu_has_dc_aliases) {
314 		for_each_present_cpu(c) {
315 			if (cpus_are_siblings(smp_processor_id(), c))
316 				continue;
317 
318 			set_cpu_present(c, false);
319 			cores_limited = true;
320 		}
321 	}
322 	if (cores_limited)
323 		pr_warn("Using only one core due to %s%s%s\n",
324 			cca_unsuitable ? "unsuitable CCA" : "",
325 			(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
326 			cpu_has_dc_aliases ? "dcache aliasing" : "");
327 
328 	setup_cps_vecs();
329 
330 	/* Allocate cluster boot configuration structs */
331 	nclusters = mips_cps_numclusters();
332 	mips_cps_cluster_bootcfg = kcalloc(nclusters,
333 					   sizeof(*mips_cps_cluster_bootcfg),
334 					   GFP_KERNEL);
335 	if (!mips_cps_cluster_bootcfg)
336 		goto err_out;
337 
338 	if (nclusters > 1)
339 		mips_cm_update_property();
340 
341 	for (cl = 0; cl < nclusters; cl++) {
342 		/* Allocate core boot configuration structs */
343 		ncores = mips_cps_numcores(cl);
344 		core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg),
345 					GFP_KERNEL);
346 		if (!core_bootcfg)
347 			goto err_out;
348 		mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg;
349 
350 		mips_cps_cluster_bootcfg[cl].core_power =
351 			kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long),
352 				GFP_KERNEL);
353 		if (!mips_cps_cluster_bootcfg[cl].core_power)
354 			goto err_out;
355 
356 		/* Allocate VPE boot configuration structs */
357 		for (c = 0; c < ncores; c++) {
358 			core_vpes = core_vpe_count(cl, c);
359 			core_bootcfg[c].vpe_config = kcalloc(core_vpes,
360 					sizeof(*core_bootcfg[c].vpe_config),
361 					GFP_KERNEL);
362 			if (!core_bootcfg[c].vpe_config)
363 				goto err_out;
364 		}
365 	}
366 
367 	/* Mark this CPU as powered up & booted */
368 	cl = cpu_cluster(&current_cpu_data);
369 	c = cpu_core(&current_cpu_data);
370 	cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
371 	core_bootcfg = &cluster_bootcfg->core_config[c];
372 	bitmap_set(cluster_bootcfg->core_power, cpu_core(&current_cpu_data), 1);
373 	atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(&current_cpu_data));
374 
375 	return;
376 err_out:
377 	/* Clean up allocations */
378 	if (mips_cps_cluster_bootcfg) {
379 		for (cl = 0; cl < nclusters; cl++) {
380 			cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
381 			ncores = mips_cps_numcores(cl);
382 			for (c = 0; c < ncores; c++) {
383 				core_bootcfg = &cluster_bootcfg->core_config[c];
384 				kfree(core_bootcfg->vpe_config);
385 			}
386 			kfree(mips_cps_cluster_bootcfg[c].core_config);
387 		}
388 		kfree(mips_cps_cluster_bootcfg);
389 		mips_cps_cluster_bootcfg = NULL;
390 	}
391 
392 	/* Effectively disable SMP by declaring CPUs not present */
393 	for_each_possible_cpu(c) {
394 		if (c == 0)
395 			continue;
396 		set_cpu_present(c, false);
397 	}
398 }
399 
init_cluster_l2(void)400 static void init_cluster_l2(void)
401 {
402 	u32 l2_cfg, l2sm_cop, result;
403 
404 	while (!mips_cm_is_l2_hci_broken) {
405 		l2_cfg = read_gcr_redir_l2_ram_config();
406 
407 		/* If HCI is not supported, use the state machine below */
408 		if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT))
409 			break;
410 		if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED))
411 			break;
412 
413 		/* If the HCI_DONE bit is set, we're finished */
414 		if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE)
415 			return;
416 	}
417 
418 	l2sm_cop = read_gcr_redir_l2sm_cop();
419 	if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT),
420 		 "L2 init not supported on this system yet"))
421 		return;
422 
423 	/* Clear L2 tag registers */
424 	write_gcr_redir_l2_tag_state(0);
425 	write_gcr_redir_l2_ecc(0);
426 
427 	/* Ensure the L2 tag writes complete before the state machine starts */
428 	mb();
429 
430 	/* Wait for the L2 state machine to be idle */
431 	do {
432 		l2sm_cop = read_gcr_redir_l2sm_cop();
433 	} while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING);
434 
435 	/* Start a store tag operation */
436 	l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG;
437 	l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE);
438 	l2sm_cop |= CM_GCR_L2SM_COP_CMD_START;
439 	write_gcr_redir_l2sm_cop(l2sm_cop);
440 
441 	/* Ensure the state machine starts before we poll for completion */
442 	mb();
443 
444 	/* Wait for the operation to be complete */
445 	do {
446 		l2sm_cop = read_gcr_redir_l2sm_cop();
447 		result = l2sm_cop & CM_GCR_L2SM_COP_RESULT;
448 		result >>= __ffs(CM_GCR_L2SM_COP_RESULT);
449 	} while (!result);
450 
451 	WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK,
452 	     "L2 state machine failed cache init with error %u\n", result);
453 }
454 
boot_core(unsigned int cluster,unsigned int core,unsigned int vpe_id)455 static void boot_core(unsigned int cluster, unsigned int core,
456 		      unsigned int vpe_id)
457 {
458 	struct cluster_boot_config *cluster_cfg;
459 	u32 access, stat, seq_state;
460 	unsigned int timeout, ncores;
461 
462 	cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
463 	ncores = mips_cps_numcores(cluster);
464 
465 	if ((cluster != cpu_cluster(&current_cpu_data)) &&
466 	    bitmap_empty(cluster_cfg->core_power, ncores)) {
467 		power_up_other_cluster(cluster);
468 
469 		mips_cm_lock_other(cluster, core, 0,
470 				   CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
471 
472 		/* Ensure cluster GCRs are where we expect */
473 		write_gcr_redir_base(read_gcr_base());
474 		write_gcr_redir_cpc_base(read_gcr_cpc_base());
475 		write_gcr_redir_gic_base(read_gcr_gic_base());
476 
477 		init_cluster_l2();
478 
479 		/* Mirror L2 configuration */
480 		write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base());
481 		write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control());
482 		write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b());
483 
484 		/* Mirror ECC/parity setup */
485 		write_gcr_redir_err_control(read_gcr_err_control());
486 
487 		/* Set BEV base */
488 		write_gcr_redir_bev_base(core_entry_reg);
489 
490 		mips_cm_unlock_other();
491 	}
492 
493 	if (cluster != cpu_cluster(&current_cpu_data)) {
494 		mips_cm_lock_other(cluster, core, 0,
495 				   CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
496 
497 		/* Ensure the core can access the GCRs */
498 		access = read_gcr_redir_access();
499 		access |= BIT(core);
500 		write_gcr_redir_access(access);
501 
502 		mips_cm_unlock_other();
503 	} else {
504 		/* Ensure the core can access the GCRs */
505 		access = read_gcr_access();
506 		access |= BIT(core);
507 		write_gcr_access(access);
508 	}
509 
510 	/* Select the appropriate core */
511 	mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
512 
513 	/* Set its reset vector */
514 	if (mips_cm_is64)
515 		write_gcr_co_reset64_base(core_entry_reg);
516 	else
517 		write_gcr_co_reset_base(core_entry_reg);
518 
519 	/* Ensure its coherency is disabled */
520 	write_gcr_co_coherence(0);
521 
522 	/* Start it with the legacy memory map and exception base */
523 	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
524 
525 	/* Ensure the core can access the GCRs */
526 	if (mips_cm_revision() < CM_REV_CM3)
527 		set_gcr_access(1 << core);
528 	else
529 		set_gcr_access_cm3(1 << core);
530 
531 	if (mips_cpc_present()) {
532 		/* Reset the core */
533 		mips_cpc_lock_other(core);
534 
535 		if (mips_cm_revision() >= CM_REV_CM3) {
536 			/* Run only the requested VP following the reset */
537 			write_cpc_co_vp_stop(0xf);
538 			write_cpc_co_vp_run(1 << vpe_id);
539 
540 			/*
541 			 * Ensure that the VP_RUN register is written before the
542 			 * core leaves reset.
543 			 */
544 			wmb();
545 		}
546 
547 		write_cpc_co_cmd(CPC_Cx_CMD_RESET);
548 
549 		timeout = 100;
550 		while (true) {
551 			stat = read_cpc_co_stat_conf();
552 			seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
553 			seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
554 
555 			/* U6 == coherent execution, ie. the core is up */
556 			if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
557 				break;
558 
559 			/* Delay a little while before we start warning */
560 			if (timeout) {
561 				timeout--;
562 				mdelay(10);
563 				continue;
564 			}
565 
566 			pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
567 				core, stat);
568 			mdelay(1000);
569 		}
570 
571 		mips_cpc_unlock_other();
572 	} else {
573 		/* Take the core out of reset */
574 		write_gcr_co_reset_release(0);
575 	}
576 
577 	mips_cm_unlock_other();
578 
579 	/* The core is now powered up */
580 	bitmap_set(cluster_cfg->core_power, core, 1);
581 
582 	/*
583 	 * Restore CM_PWRUP=0 so that the CM can power down if all the cores in
584 	 * the cluster do (eg. if they're all removed via hotplug.
585 	 */
586 	if (mips_cm_revision() >= CM_REV_CM3_5) {
587 		mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
588 		write_cpc_redir_pwrup_ctl(0);
589 		mips_cm_unlock_other();
590 	}
591 }
592 
remote_vpe_boot(void * dummy)593 static void remote_vpe_boot(void *dummy)
594 {
595 	unsigned int cluster = cpu_cluster(&current_cpu_data);
596 	unsigned core = cpu_core(&current_cpu_data);
597 	struct cluster_boot_config *cluster_cfg =
598 		&mips_cps_cluster_bootcfg[cluster];
599 	struct core_boot_config *core_cfg = &cluster_cfg->core_config[core];
600 
601 	mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
602 }
603 
cps_boot_secondary(int cpu,struct task_struct * idle)604 static int cps_boot_secondary(int cpu, struct task_struct *idle)
605 {
606 	unsigned int cluster = cpu_cluster(&cpu_data[cpu]);
607 	unsigned core = cpu_core(&cpu_data[cpu]);
608 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
609 	struct cluster_boot_config *cluster_cfg =
610 		&mips_cps_cluster_bootcfg[cluster];
611 	struct core_boot_config *core_cfg = &cluster_cfg->core_config[core];
612 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
613 	unsigned int remote;
614 	int err;
615 
616 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;
617 	vpe_cfg->sp = __KSTK_TOS(idle);
618 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);
619 
620 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
621 
622 	preempt_disable();
623 
624 	if (!test_bit(core, cluster_cfg->core_power)) {
625 		/* Boot a VPE on a powered down core */
626 		boot_core(cluster, core, vpe_id);
627 		goto out;
628 	}
629 
630 	if (cpu_has_vp) {
631 		mips_cm_lock_other(cluster, core, vpe_id,
632 				   CM_GCR_Cx_OTHER_BLOCK_LOCAL);
633 		if (mips_cm_is64)
634 			write_gcr_co_reset64_base(core_entry_reg);
635 		else
636 			write_gcr_co_reset_base(core_entry_reg);
637 		mips_cm_unlock_other();
638 	}
639 
640 	if (!cpus_are_siblings(cpu, smp_processor_id())) {
641 		/* Boot a VPE on another powered up core */
642 		for (remote = 0; remote < NR_CPUS; remote++) {
643 			if (!cpus_are_siblings(cpu, remote))
644 				continue;
645 			if (cpu_online(remote))
646 				break;
647 		}
648 		if (remote >= NR_CPUS) {
649 			pr_crit("No online CPU in core %u to start CPU%d\n",
650 				core, cpu);
651 			goto out;
652 		}
653 
654 		err = smp_call_function_single(remote, remote_vpe_boot,
655 					       NULL, 1);
656 		if (err)
657 			panic("Failed to call remote CPU\n");
658 		goto out;
659 	}
660 
661 	BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
662 
663 	/* Boot a VPE on this core */
664 	mips_cps_boot_vpes(core_cfg, vpe_id);
665 out:
666 	preempt_enable();
667 	return 0;
668 }
669 
cps_init_secondary(void)670 static void cps_init_secondary(void)
671 {
672 	int core = cpu_core(&current_cpu_data);
673 
674 	/* Disable MT - we only want to run 1 TC per VPE */
675 	if (cpu_has_mipsmt)
676 		dmt();
677 
678 	if (mips_cm_revision() >= CM_REV_CM3) {
679 		unsigned int ident = read_gic_vl_ident();
680 
681 		/*
682 		 * Ensure that our calculation of the VP ID matches up with
683 		 * what the GIC reports, otherwise we'll have configured
684 		 * interrupts incorrectly.
685 		 */
686 		BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
687 	}
688 
689 	if (core > 0 && !read_gcr_cl_coherence())
690 		pr_warn("Core %u is not in coherent domain\n", core);
691 
692 	if (cpu_has_veic)
693 		clear_c0_status(ST0_IM);
694 	else
695 		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
696 					 STATUSF_IP4 | STATUSF_IP5 |
697 					 STATUSF_IP6 | STATUSF_IP7);
698 }
699 
cps_smp_finish(void)700 static void cps_smp_finish(void)
701 {
702 	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
703 
704 #ifdef CONFIG_MIPS_MT_FPAFF
705 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
706 	if (cpu_has_fpu)
707 		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
708 #endif /* CONFIG_MIPS_MT_FPAFF */
709 
710 	local_irq_enable();
711 }
712 
713 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
714 
715 enum cpu_death {
716 	CPU_DEATH_HALT,
717 	CPU_DEATH_POWER,
718 };
719 
cps_shutdown_this_cpu(enum cpu_death death)720 static void cps_shutdown_this_cpu(enum cpu_death death)
721 {
722 	unsigned int cpu, core, vpe_id;
723 
724 	cpu = smp_processor_id();
725 	core = cpu_core(&cpu_data[cpu]);
726 
727 	if (death == CPU_DEATH_HALT) {
728 		vpe_id = cpu_vpe_id(&cpu_data[cpu]);
729 
730 		pr_debug("Halting core %d VP%d\n", core, vpe_id);
731 		if (cpu_has_mipsmt) {
732 			/* Halt this TC */
733 			write_c0_tchalt(TCHALT_H);
734 			instruction_hazard();
735 		} else if (cpu_has_vp) {
736 			write_cpc_cl_vp_stop(1 << vpe_id);
737 
738 			/* Ensure that the VP_STOP register is written */
739 			wmb();
740 		}
741 	} else {
742 		if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
743 			pr_debug("Gating power to core %d\n", core);
744 			/* Power down the core */
745 			cps_pm_enter_state(CPS_PM_POWER_GATED);
746 		}
747 	}
748 }
749 
750 #ifdef CONFIG_KEXEC_CORE
751 
cps_kexec_nonboot_cpu(void)752 static void cps_kexec_nonboot_cpu(void)
753 {
754 	if (cpu_has_mipsmt || cpu_has_vp)
755 		cps_shutdown_this_cpu(CPU_DEATH_HALT);
756 	else
757 		cps_shutdown_this_cpu(CPU_DEATH_POWER);
758 }
759 
760 #endif /* CONFIG_KEXEC_CORE */
761 
762 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */
763 
764 #ifdef CONFIG_HOTPLUG_CPU
765 
cps_cpu_disable(void)766 static int cps_cpu_disable(void)
767 {
768 	unsigned cpu = smp_processor_id();
769 	struct cluster_boot_config *cluster_cfg;
770 	struct core_boot_config *core_cfg;
771 
772 	if (!cps_pm_support_state(CPS_PM_POWER_GATED))
773 		return -EINVAL;
774 
775 	cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(&current_cpu_data)];
776 	core_cfg = &cluster_cfg->core_config[cpu_core(&current_cpu_data)];
777 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
778 	smp_mb__after_atomic();
779 	set_cpu_online(cpu, false);
780 	calculate_cpu_foreign_map();
781 	irq_migrate_all_off_this_cpu();
782 
783 	return 0;
784 }
785 
786 static unsigned cpu_death_sibling;
787 static enum cpu_death cpu_death;
788 
play_dead(void)789 void play_dead(void)
790 {
791 	unsigned int cpu;
792 
793 	local_irq_disable();
794 	idle_task_exit();
795 	cpu = smp_processor_id();
796 	cpu_death = CPU_DEATH_POWER;
797 
798 	pr_debug("CPU%d going offline\n", cpu);
799 
800 	if (cpu_has_mipsmt || cpu_has_vp) {
801 		/* Look for another online VPE within the core */
802 		for_each_online_cpu(cpu_death_sibling) {
803 			if (!cpus_are_siblings(cpu, cpu_death_sibling))
804 				continue;
805 
806 			/*
807 			 * There is an online VPE within the core. Just halt
808 			 * this TC and leave the core alone.
809 			 */
810 			cpu_death = CPU_DEATH_HALT;
811 			break;
812 		}
813 	}
814 
815 	cpuhp_ap_report_dead();
816 
817 	cps_shutdown_this_cpu(cpu_death);
818 
819 	/* This should never be reached */
820 	panic("Failed to offline CPU %u", cpu);
821 }
822 
wait_for_sibling_halt(void * ptr_cpu)823 static void wait_for_sibling_halt(void *ptr_cpu)
824 {
825 	unsigned cpu = (unsigned long)ptr_cpu;
826 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
827 	unsigned halted;
828 	unsigned long flags;
829 
830 	do {
831 		local_irq_save(flags);
832 		settc(vpe_id);
833 		halted = read_tc_c0_tchalt();
834 		local_irq_restore(flags);
835 	} while (!(halted & TCHALT_H));
836 }
837 
cps_cpu_die(unsigned int cpu)838 static void cps_cpu_die(unsigned int cpu) { }
839 
cps_cleanup_dead_cpu(unsigned cpu)840 static void cps_cleanup_dead_cpu(unsigned cpu)
841 {
842 	unsigned int cluster = cpu_cluster(&cpu_data[cpu]);
843 	unsigned core = cpu_core(&cpu_data[cpu]);
844 	unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
845 	ktime_t fail_time;
846 	unsigned stat;
847 	int err;
848 	struct cluster_boot_config *cluster_cfg;
849 
850 	cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
851 
852 	/*
853 	 * Now wait for the CPU to actually offline. Without doing this that
854 	 * offlining may race with one or more of:
855 	 *
856 	 *   - Onlining the CPU again.
857 	 *   - Powering down the core if another VPE within it is offlined.
858 	 *   - A sibling VPE entering a non-coherent state.
859 	 *
860 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
861 	 * with which we could race, so do nothing.
862 	 */
863 	if (cpu_death == CPU_DEATH_POWER) {
864 		/*
865 		 * Wait for the core to enter a powered down or clock gated
866 		 * state, the latter happening when a JTAG probe is connected
867 		 * in which case the CPC will refuse to power down the core.
868 		 */
869 		fail_time = ktime_add_ms(ktime_get(), 2000);
870 		do {
871 			mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
872 			mips_cpc_lock_other(core);
873 			stat = read_cpc_co_stat_conf();
874 			stat &= CPC_Cx_STAT_CONF_SEQSTATE;
875 			stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
876 			mips_cpc_unlock_other();
877 			mips_cm_unlock_other();
878 
879 			if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
880 			    stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
881 			    stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
882 				break;
883 
884 			/*
885 			 * The core ought to have powered down, but didn't &
886 			 * now we don't really know what state it's in. It's
887 			 * likely that its _pwr_up pin has been wired to logic
888 			 * 1 & it powered back up as soon as we powered it
889 			 * down...
890 			 *
891 			 * The best we can do is warn the user & continue in
892 			 * the hope that the core is doing nothing harmful &
893 			 * might behave properly if we online it later.
894 			 */
895 			if (WARN(ktime_after(ktime_get(), fail_time),
896 				 "CPU%u hasn't powered down, seq. state %u\n",
897 				 cpu, stat))
898 				break;
899 		} while (1);
900 
901 		/* Indicate the core is powered off */
902 		bitmap_clear(cluster_cfg->core_power, core, 1);
903 	} else if (cpu_has_mipsmt) {
904 		/*
905 		 * Have a CPU with access to the offlined CPUs registers wait
906 		 * for its TC to halt.
907 		 */
908 		err = smp_call_function_single(cpu_death_sibling,
909 					       wait_for_sibling_halt,
910 					       (void *)(unsigned long)cpu, 1);
911 		if (err)
912 			panic("Failed to call remote sibling CPU\n");
913 	} else if (cpu_has_vp) {
914 		do {
915 			mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
916 			stat = read_cpc_co_vp_running();
917 			mips_cm_unlock_other();
918 		} while (stat & (1 << vpe_id));
919 	}
920 }
921 
922 #endif /* CONFIG_HOTPLUG_CPU */
923 
924 static const struct plat_smp_ops cps_smp_ops = {
925 	.smp_setup		= cps_smp_setup,
926 	.prepare_cpus		= cps_prepare_cpus,
927 	.boot_secondary		= cps_boot_secondary,
928 	.init_secondary		= cps_init_secondary,
929 	.smp_finish		= cps_smp_finish,
930 	.send_ipi_single	= mips_smp_send_ipi_single,
931 	.send_ipi_mask		= mips_smp_send_ipi_mask,
932 #ifdef CONFIG_HOTPLUG_CPU
933 	.cpu_disable		= cps_cpu_disable,
934 	.cpu_die		= cps_cpu_die,
935 	.cleanup_dead_cpu	= cps_cleanup_dead_cpu,
936 #endif
937 #ifdef CONFIG_KEXEC_CORE
938 	.kexec_nonboot_cpu	= cps_kexec_nonboot_cpu,
939 #endif
940 };
941 
mips_cps_smp_in_use(void)942 bool mips_cps_smp_in_use(void)
943 {
944 	extern const struct plat_smp_ops *mp_ops;
945 	return mp_ops == &cps_smp_ops;
946 }
947 
register_cps_smp_ops(void)948 int register_cps_smp_ops(void)
949 {
950 	if (!mips_cm_present()) {
951 		pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
952 		return -ENODEV;
953 	}
954 
955 	/* check we have a GIC - we need one for IPIs */
956 	if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
957 		pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
958 		return -ENODEV;
959 	}
960 
961 	register_smp_ops(&cps_smp_ops);
962 	return 0;
963 }
964