1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2013 Imagination Technologies
4  * Author: Paul Burton <paul.burton@mips.com>
5  */
6 
7 #include <linux/errno.h>
8 #include <linux/of.h>
9 #include <linux/percpu.h>
10 #include <linux/spinlock.h>
11 
12 #include <asm/mips-cps.h>
13 #include <asm/mipsregs.h>
14 
15 void __iomem *mips_gcr_base;
16 void __iomem *mips_cm_l2sync_base;
17 int mips_cm_is64;
18 bool mips_cm_is_l2_hci_broken;
19 
20 static char *cm2_tr[8] = {
21 	"mem",	"gcr",	"gic",	"mmio",
22 	"0x04", "cpc", "0x06", "0x07"
23 };
24 
25 /* CM3 Tag ECC transaction type */
26 static char *cm3_tr[16] = {
27 	[0x0] = "ReqNoData",
28 	[0x1] = "0x1",
29 	[0x2] = "ReqWData",
30 	[0x3] = "0x3",
31 	[0x4] = "IReqNoResp",
32 	[0x5] = "IReqWResp",
33 	[0x6] = "IReqNoRespDat",
34 	[0x7] = "IReqWRespDat",
35 	[0x8] = "RespNoData",
36 	[0x9] = "RespDataFol",
37 	[0xa] = "RespWData",
38 	[0xb] = "RespDataOnly",
39 	[0xc] = "IRespNoData",
40 	[0xd] = "IRespDataFol",
41 	[0xe] = "IRespWData",
42 	[0xf] = "IRespDataOnly"
43 };
44 
45 static char *cm2_cmd[32] = {
46 	[0x00] = "0x00",
47 	[0x01] = "Legacy Write",
48 	[0x02] = "Legacy Read",
49 	[0x03] = "0x03",
50 	[0x04] = "0x04",
51 	[0x05] = "0x05",
52 	[0x06] = "0x06",
53 	[0x07] = "0x07",
54 	[0x08] = "Coherent Read Own",
55 	[0x09] = "Coherent Read Share",
56 	[0x0a] = "Coherent Read Discard",
57 	[0x0b] = "Coherent Ready Share Always",
58 	[0x0c] = "Coherent Upgrade",
59 	[0x0d] = "Coherent Writeback",
60 	[0x0e] = "0x0e",
61 	[0x0f] = "0x0f",
62 	[0x10] = "Coherent Copyback",
63 	[0x11] = "Coherent Copyback Invalidate",
64 	[0x12] = "Coherent Invalidate",
65 	[0x13] = "Coherent Write Invalidate",
66 	[0x14] = "Coherent Completion Sync",
67 	[0x15] = "0x15",
68 	[0x16] = "0x16",
69 	[0x17] = "0x17",
70 	[0x18] = "0x18",
71 	[0x19] = "0x19",
72 	[0x1a] = "0x1a",
73 	[0x1b] = "0x1b",
74 	[0x1c] = "0x1c",
75 	[0x1d] = "0x1d",
76 	[0x1e] = "0x1e",
77 	[0x1f] = "0x1f"
78 };
79 
80 /* CM3 Tag ECC command type */
81 static char *cm3_cmd[16] = {
82 	[0x0] = "Legacy Read",
83 	[0x1] = "Legacy Write",
84 	[0x2] = "Coherent Read Own",
85 	[0x3] = "Coherent Read Share",
86 	[0x4] = "Coherent Read Discard",
87 	[0x5] = "Coherent Evicted",
88 	[0x6] = "Coherent Upgrade",
89 	[0x7] = "Coherent Upgrade for Store Conditional",
90 	[0x8] = "Coherent Writeback",
91 	[0x9] = "Coherent Write Invalidate",
92 	[0xa] = "0xa",
93 	[0xb] = "0xb",
94 	[0xc] = "0xc",
95 	[0xd] = "0xd",
96 	[0xe] = "0xe",
97 	[0xf] = "0xf"
98 };
99 
100 /* CM3 Tag ECC command group */
101 static char *cm3_cmd_group[8] = {
102 	[0x0] = "Normal",
103 	[0x1] = "Registers",
104 	[0x2] = "TLB",
105 	[0x3] = "0x3",
106 	[0x4] = "L1I",
107 	[0x5] = "L1D",
108 	[0x6] = "L3",
109 	[0x7] = "L2"
110 };
111 
112 static char *cm2_core[8] = {
113 	"Invalid/OK",	"Invalid/Data",
114 	"Shared/OK",	"Shared/Data",
115 	"Modified/OK",	"Modified/Data",
116 	"Exclusive/OK", "Exclusive/Data"
117 };
118 
119 static char *cm2_l2_type[4] = {
120 	[0x0] = "None",
121 	[0x1] = "Tag RAM single/double ECC error",
122 	[0x2] = "Data RAM single/double ECC error",
123 	[0x3] = "WS RAM uncorrectable dirty parity"
124 };
125 
126 static char *cm2_l2_instr[32] = {
127 	[0x00] = "L2_NOP",
128 	[0x01] = "L2_ERR_CORR",
129 	[0x02] = "L2_TAG_INV",
130 	[0x03] = "L2_WS_CLEAN",
131 	[0x04] = "L2_RD_MDYFY_WR",
132 	[0x05] = "L2_WS_MRU",
133 	[0x06] = "L2_EVICT_LN2",
134 	[0x07] = "0x07",
135 	[0x08] = "L2_EVICT",
136 	[0x09] = "L2_REFL",
137 	[0x0a] = "L2_RD",
138 	[0x0b] = "L2_WR",
139 	[0x0c] = "L2_EVICT_MRU",
140 	[0x0d] = "L2_SYNC",
141 	[0x0e] = "L2_REFL_ERR",
142 	[0x0f] = "0x0f",
143 	[0x10] = "L2_INDX_WB_INV",
144 	[0x11] = "L2_INDX_LD_TAG",
145 	[0x12] = "L2_INDX_ST_TAG",
146 	[0x13] = "L2_INDX_ST_DATA",
147 	[0x14] = "L2_INDX_ST_ECC",
148 	[0x15] = "0x15",
149 	[0x16] = "0x16",
150 	[0x17] = "0x17",
151 	[0x18] = "L2_FTCH_AND_LCK",
152 	[0x19] = "L2_HIT_INV",
153 	[0x1a] = "L2_HIT_WB_INV",
154 	[0x1b] = "L2_HIT_WB",
155 	[0x1c] = "0x1c",
156 	[0x1d] = "0x1d",
157 	[0x1e] = "0x1e",
158 	[0x1f] = "0x1f"
159 };
160 
161 static char *cm2_causes[32] = {
162 	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
163 	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
164 	"0x08", "0x09", "0x0a", "0x0b",
165 	"0x0c", "0x0d", "0x0e", "0x0f",
166 	"0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
167 	"0x14", "0x15", "0x16", "0x17",
168 	"L2_RD_UNCORR", "L2_WR_UNCORR", "L2_CORR", "0x1b",
169 	"0x1c", "0x1d", "0x1e", "0x1f"
170 };
171 
172 static char *cm3_causes[32] = {
173 	"0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
174 	"MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
175 	"CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
176 	"0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
177 	"0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
178 	"0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
179 };
180 
181 static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
182 static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
183 
mips_cm_phys_base(void)184 phys_addr_t __weak mips_cm_phys_base(void)
185 {
186 	unsigned long cmgcr;
187 
188 	/* Check the CMGCRBase register is implemented */
189 	if (!(read_c0_config() & MIPS_CONF_M))
190 		return 0;
191 
192 	if (!(read_c0_config2() & MIPS_CONF_M))
193 		return 0;
194 
195 	if (!(read_c0_config3() & MIPS_CONF3_CMGCR))
196 		return 0;
197 
198 	/* Read the address from CMGCRBase */
199 	cmgcr = read_c0_cmgcrbase();
200 	return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
201 }
202 
mips_cm_l2sync_phys_base(void)203 phys_addr_t __weak mips_cm_l2sync_phys_base(void)
204 {
205 	u32 base_reg;
206 
207 	/*
208 	 * If the L2-only sync region is already enabled then leave it at it's
209 	 * current location.
210 	 */
211 	base_reg = read_gcr_l2_only_sync_base();
212 	if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
213 		return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
214 
215 	/* Default to following the CM */
216 	return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
217 }
218 
mips_cm_probe_l2sync(void)219 static void mips_cm_probe_l2sync(void)
220 {
221 	unsigned major_rev;
222 	phys_addr_t addr;
223 
224 	/* L2-only sync was introduced with CM major revision 6 */
225 	major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev());
226 	if (major_rev < 6)
227 		return;
228 
229 	/* Find a location for the L2 sync region */
230 	addr = mips_cm_l2sync_phys_base();
231 	BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE) != addr);
232 	if (!addr)
233 		return;
234 
235 	/* Set the region base address & enable it */
236 	write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
237 
238 	/* Map the region */
239 	mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE);
240 }
241 
mips_cm_update_property(void)242 void mips_cm_update_property(void)
243 {
244 	struct device_node *cm_node;
245 
246 	cm_node = of_find_compatible_node(of_root, NULL, "mobileye,eyeq6-cm");
247 	if (!cm_node)
248 		return;
249 	pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken");
250 	mips_cm_is_l2_hci_broken = true;
251 	of_node_put(cm_node);
252 }
253 
mips_cm_probe(void)254 int mips_cm_probe(void)
255 {
256 	phys_addr_t addr;
257 	u32 base_reg;
258 	unsigned cpu;
259 
260 	/*
261 	 * No need to probe again if we have already been
262 	 * here before.
263 	 */
264 	if (mips_gcr_base)
265 		return 0;
266 
267 	addr = mips_cm_phys_base();
268 	BUG_ON((addr & CM_GCR_BASE_GCRBASE) != addr);
269 	if (!addr)
270 		return -ENODEV;
271 
272 	mips_gcr_base = ioremap(addr, MIPS_CM_GCR_SIZE);
273 	if (!mips_gcr_base)
274 		return -ENXIO;
275 
276 	/* sanity check that we're looking at a CM */
277 	base_reg = read_gcr_base();
278 	if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
279 		pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
280 		       (unsigned long)addr);
281 		iounmap(mips_gcr_base);
282 		mips_gcr_base = NULL;
283 		return -ENODEV;
284 	}
285 
286 	/* set default target to memory */
287 	change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
288 
289 	/* disable CM regions */
290 	write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);
291 	write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK);
292 	write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR);
293 	write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK);
294 	write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR);
295 	write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK);
296 	write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR);
297 	write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK);
298 
299 	/* probe for an L2-only sync region */
300 	mips_cm_probe_l2sync();
301 
302 	/* determine register width for this CM */
303 	mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
304 
305 	for_each_possible_cpu(cpu)
306 		spin_lock_init(&per_cpu(cm_core_lock, cpu));
307 
308 	return 0;
309 }
310 
mips_cm_lock_other(unsigned int cluster,unsigned int core,unsigned int vp,unsigned int block)311 void mips_cm_lock_other(unsigned int cluster, unsigned int core,
312 			unsigned int vp, unsigned int block)
313 {
314 	unsigned int curr_core, cm_rev;
315 	u32 val;
316 
317 	cm_rev = mips_cm_revision();
318 	preempt_disable();
319 
320 	if (cm_rev >= CM_REV_CM3) {
321 		val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) |
322 		      FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
323 
324 		if (cm_rev >= CM_REV_CM3_5) {
325 			if (cluster != cpu_cluster(&current_cpu_data))
326 				val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
327 			val |= CM_GCR_Cx_OTHER_GIC_EN;
328 			val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
329 			val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
330 		} else {
331 			WARN_ON(cluster != 0);
332 			WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
333 		}
334 
335 		/*
336 		 * We need to disable interrupts in SMP systems in order to
337 		 * ensure that we don't interrupt the caller with code which
338 		 * may modify the redirect register. We do so here in a
339 		 * slightly obscure way by using a spin lock, since this has
340 		 * the neat property of also catching any nested uses of
341 		 * mips_cm_lock_other() leading to a deadlock or a nice warning
342 		 * with lockdep enabled.
343 		 */
344 		spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
345 				  *this_cpu_ptr(&cm_core_lock_flags));
346 	} else {
347 		WARN_ON(cluster != 0);
348 		WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
349 
350 		/*
351 		 * We only have a GCR_CL_OTHER per core in systems with
352 		 * CM 2.5 & older, so have to ensure other VP(E)s don't
353 		 * race with us.
354 		 */
355 		curr_core = cpu_core(&current_cpu_data);
356 		spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
357 				  per_cpu(cm_core_lock_flags, curr_core));
358 
359 		val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
360 	}
361 
362 	write_gcr_cl_other(val);
363 
364 	/*
365 	 * Ensure the core-other region reflects the appropriate core &
366 	 * VP before any accesses to it occur.
367 	 */
368 	mb();
369 }
370 
mips_cm_unlock_other(void)371 void mips_cm_unlock_other(void)
372 {
373 	unsigned int curr_core;
374 
375 	if (mips_cm_revision() < CM_REV_CM3) {
376 		curr_core = cpu_core(&current_cpu_data);
377 		spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
378 				       per_cpu(cm_core_lock_flags, curr_core));
379 	} else {
380 		spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
381 				       *this_cpu_ptr(&cm_core_lock_flags));
382 	}
383 
384 	preempt_enable();
385 }
386 
mips_cm_error_report(void)387 void mips_cm_error_report(void)
388 {
389 	u64 cm_error, cm_addr, cm_other;
390 	unsigned long revision;
391 	int ocause, cause;
392 	char buf[256];
393 
394 	if (!mips_cm_present())
395 		return;
396 
397 	revision = mips_cm_revision();
398 	cm_error = read_gcr_error_cause();
399 	cm_addr = read_gcr_error_addr();
400 	cm_other = read_gcr_error_mult();
401 
402 	if (revision < CM_REV_CM3) { /* CM2 */
403 		cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
404 		ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
405 
406 		if (!cause)
407 			return;
408 
409 		if (cause < 16) {
410 			unsigned long cca_bits = (cm_error >> 15) & 7;
411 			unsigned long tr_bits = (cm_error >> 12) & 7;
412 			unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
413 			unsigned long stag_bits = (cm_error >> 3) & 15;
414 			unsigned long sport_bits = (cm_error >> 0) & 7;
415 
416 			snprintf(buf, sizeof(buf),
417 				 "CCA=%lu TR=%s MCmd=%s STag=%lu "
418 				 "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
419 				 cm2_cmd[cmd_bits], stag_bits, sport_bits);
420 		} else if (cause < 24) {
421 			/* glob state & sresp together */
422 			unsigned long c3_bits = (cm_error >> 18) & 7;
423 			unsigned long c2_bits = (cm_error >> 15) & 7;
424 			unsigned long c1_bits = (cm_error >> 12) & 7;
425 			unsigned long c0_bits = (cm_error >> 9) & 7;
426 			unsigned long sc_bit = (cm_error >> 8) & 1;
427 			unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
428 			unsigned long sport_bits = (cm_error >> 0) & 7;
429 
430 			snprintf(buf, sizeof(buf),
431 				 "C3=%s C2=%s C1=%s C0=%s SC=%s "
432 				 "MCmd=%s SPort=%lu\n",
433 				 cm2_core[c3_bits], cm2_core[c2_bits],
434 				 cm2_core[c1_bits], cm2_core[c0_bits],
435 				 sc_bit ? "True" : "False",
436 				 cm2_cmd[cmd_bits], sport_bits);
437 		} else {
438 			unsigned long muc_bit = (cm_error >> 23) & 1;
439 			unsigned long ins_bits = (cm_error >> 18) & 0x1f;
440 			unsigned long arr_bits = (cm_error >> 16) & 3;
441 			unsigned long dw_bits = (cm_error >> 12) & 15;
442 			unsigned long way_bits = (cm_error >> 9) & 7;
443 			unsigned long mway_bit = (cm_error >> 8) & 1;
444 			unsigned long syn_bits = (cm_error >> 0) & 0xFF;
445 
446 			snprintf(buf, sizeof(buf),
447 				 "Type=%s%s Instr=%s DW=%lu Way=%lu "
448 				 "MWay=%s Syndrome=0x%02lx",
449 				 muc_bit ? "Multi-UC " : "",
450 				 cm2_l2_type[arr_bits],
451 				 cm2_l2_instr[ins_bits], dw_bits, way_bits,
452 				 mway_bit ? "True" : "False", syn_bits);
453 		}
454 		pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
455 		       cm2_causes[cause], buf);
456 		pr_err("CM_ADDR =%08llx\n", cm_addr);
457 		pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
458 	} else { /* CM3 */
459 		ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
460 		ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
461 
462 		cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
463 		ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
464 
465 		if (!cause)
466 			return;
467 
468 		/* Used by cause == {1,2,3} */
469 		core_id_bits = (cm_error >> 22) & 0xf;
470 		vp_id_bits = (cm_error >> 18) & 0xf;
471 		cmd_bits = (cm_error >> 14) & 0xf;
472 		cmd_group_bits = (cm_error >> 11) & 0xf;
473 		cm3_cca_bits = (cm_error >> 8) & 7;
474 		mcp_bits = (cm_error >> 5) & 0xf;
475 		cm3_tr_bits = (cm_error >> 1) & 0xf;
476 		sched_bit = cm_error & 0x1;
477 
478 		if (cause == 1 || cause == 3) { /* Tag ECC */
479 			unsigned long tag_ecc = (cm_error >> 57) & 0x1;
480 			unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
481 			unsigned long dword_bits = (cm_error >> 49) & 0xff;
482 			unsigned long data_way_bits = (cm_error >> 45) & 0xf;
483 			unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
484 			unsigned long bank_bit = (cm_error >> 28) & 0x1;
485 			snprintf(buf, sizeof(buf),
486 				 "%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
487 				 "Bank=%lu CoreID=%lu VPID=%lu Command=%s"
488 				 "Command Group=%s CCA=%lu MCP=%d"
489 				 "Transaction type=%s Scheduler=%lu\n",
490 				 tag_ecc ? "TAG" : "DATA",
491 				 tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
492 				 data_way_bits, bank_bit, dword_bits,
493 				 data_sets_bits,
494 				 core_id_bits, vp_id_bits,
495 				 cm3_cmd[cmd_bits],
496 				 cm3_cmd_group[cmd_group_bits],
497 				 cm3_cca_bits, 1 << mcp_bits,
498 				 cm3_tr[cm3_tr_bits], sched_bit);
499 		} else if (cause == 2) {
500 			unsigned long data_error_type = (cm_error >> 41) & 0xfff;
501 			unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
502 			unsigned long data_decode_group = (cm_error >> 34) & 0x7;
503 			unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
504 
505 			snprintf(buf, sizeof(buf),
506 				 "Decode Request Error: Type=%lu, Command=%lu"
507 				 "Command Group=%lu Destination ID=%lu"
508 				 "CoreID=%lu VPID=%lu Command=%s"
509 				 "Command Group=%s CCA=%lu MCP=%d"
510 				 "Transaction type=%s Scheduler=%lu\n",
511 				 data_error_type, data_decode_cmd,
512 				 data_decode_group, data_decode_destination_id,
513 				 core_id_bits, vp_id_bits,
514 				 cm3_cmd[cmd_bits],
515 				 cm3_cmd_group[cmd_group_bits],
516 				 cm3_cca_bits, 1 << mcp_bits,
517 				 cm3_tr[cm3_tr_bits], sched_bit);
518 		} else {
519 			buf[0] = 0;
520 		}
521 
522 		pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
523 		       cm3_causes[cause], buf);
524 		pr_err("CM_ADDR =%llx\n", cm_addr);
525 		pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
526 	}
527 
528 	/* reprime cause register */
529 	write_gcr_error_cause(cm_error);
530 }
531 
mips_cps_first_online_in_cluster(void)532 unsigned int mips_cps_first_online_in_cluster(void)
533 {
534 	unsigned int local_cl;
535 	int i;
536 
537 	local_cl = cpu_cluster(&current_cpu_data);
538 
539 	/*
540 	 * We rely upon knowledge that CPUs are numbered sequentially by
541 	 * cluster - ie. CPUs 0..X will be in cluster 0, CPUs X+1..Y in cluster
542 	 * 1, CPUs Y+1..Z in cluster 2 etc. This means that CPUs in the same
543 	 * cluster will immediately precede or follow one another.
544 	 *
545 	 * First we scan backwards, until we find an online CPU in the cluster
546 	 * or we move on to another cluster.
547 	 */
548 	for (i = smp_processor_id() - 1; i >= 0; i--) {
549 		if (cpu_cluster(&cpu_data[i]) != local_cl)
550 			break;
551 		if (!cpu_online(i))
552 			continue;
553 		return false;
554 	}
555 
556 	/* Then do the same for higher numbered CPUs */
557 	for (i = smp_processor_id() + 1; i < nr_cpu_ids; i++) {
558 		if (cpu_cluster(&cpu_data[i]) != local_cl)
559 			break;
560 		if (!cpu_online(i))
561 			continue;
562 		return false;
563 	}
564 
565 	/* We found no online CPUs in the local cluster */
566 	return true;
567 }
568