1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "ralink,rt3883-soc";
8
9	cpus {
10		cpu@0 {
11			compatible = "mips,mips74Kc";
12		};
13	};
14
15	cpuintc: cpuintc {
16		#address-cells = <0>;
17		#interrupt-cells = <1>;
18		interrupt-controller;
19		compatible = "mti,cpu-interrupt-controller";
20	};
21
22	palmbus@10000000 {
23		compatible = "palmbus";
24		reg = <0x10000000 0x200000>;
25		ranges = <0x0 0x10000000 0x1FFFFF>;
26
27		#address-cells = <1>;
28		#size-cells = <1>;
29
30		sysc: syscon@0 {
31			compatible = "ralink,rt3883-sysc", "syscon";
32			reg = <0x0 0x100>;
33			#clock-cells = <1>;
34			#reset-cells = <1>;
35		};
36
37		intc: intc@200 {
38			compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
39			reg = <0x200 0x100>;
40
41			interrupt-controller;
42			#interrupt-cells = <1>;
43
44			interrupt-parent = <&cpuintc>;
45			interrupts = <2>;
46		};
47
48		memc@300 {
49			compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
50			reg = <0x300 0x100>;
51		};
52
53		uartlite@c00 {
54			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
55			reg = <0xc00 0x100>;
56
57			clocks = <&sysc RT3883_CLK_UARTLITE>;
58
59			interrupt-parent = <&intc>;
60			interrupts = <12>;
61
62			reg-shift = <2>;
63		};
64	};
65};
66