1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the common parts shared by the White Hawk CPU and 4 * White Hawk Single boards 5 * 6 * Copyright (C) 2022 Renesas Electronics Corp. 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/leds/common.h> 12 13/ { 14 aliases { 15 ethernet0 = &avb0; 16 i2c0 = &i2c0; 17 i2c1 = &i2c1; 18 i2c2 = &i2c2; 19 i2c3 = &i2c3; 20 i2c4 = &i2c4; 21 i2c5 = &i2c5; 22 serial0 = &hscif0; 23 }; 24 25 chosen { 26 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 27 stdout-path = "serial0:921600n8"; 28 }; 29 30 sn65dsi86_refclk: clk-x6 { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 }; 35 36 keys { 37 compatible = "gpio-keys"; 38 39 pinctrl-0 = <&keys_pins>; 40 pinctrl-names = "default"; 41 42 key-1 { 43 gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 44 linux,code = <KEY_1>; 45 label = "SW47"; 46 wakeup-source; 47 debounce-interval = <20>; 48 }; 49 50 key-2 { 51 gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 52 linux,code = <KEY_2>; 53 label = "SW48"; 54 wakeup-source; 55 debounce-interval = <20>; 56 }; 57 58 key-3 { 59 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 60 linux,code = <KEY_3>; 61 label = "SW49"; 62 wakeup-source; 63 debounce-interval = <20>; 64 }; 65 }; 66 67 leds { 68 compatible = "gpio-leds"; 69 70 led-1 { 71 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 72 color = <LED_COLOR_ID_GREEN>; 73 function = LED_FUNCTION_INDICATOR; 74 function-enumerator = <1>; 75 }; 76 77 led-2 { 78 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 79 color = <LED_COLOR_ID_GREEN>; 80 function = LED_FUNCTION_INDICATOR; 81 function-enumerator = <2>; 82 }; 83 84 led-3 { 85 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 86 color = <LED_COLOR_ID_GREEN>; 87 function = LED_FUNCTION_INDICATOR; 88 function-enumerator = <3>; 89 }; 90 }; 91 92 memory@48000000 { 93 device_type = "memory"; 94 /* first 128MB is reserved for secure area. */ 95 reg = <0x0 0x48000000 0x0 0x78000000>; 96 }; 97 98 memory@480000000 { 99 device_type = "memory"; 100 reg = <0x4 0x80000000 0x0 0x80000000>; 101 }; 102 103 memory@600000000 { 104 device_type = "memory"; 105 reg = <0x6 0x00000000 0x1 0x00000000>; 106 }; 107 108 mini-dp-con { 109 compatible = "dp-connector"; 110 label = "CN5"; 111 type = "mini"; 112 113 port { 114 mini_dp_con_in: endpoint { 115 remote-endpoint = <&sn65dsi86_out>; 116 }; 117 }; 118 }; 119 120 pcie_clk: clk-9fgv0841-pci { 121 compatible = "fixed-clock"; 122 clock-frequency = <100000000>; 123 #clock-cells = <0>; 124 }; 125 126 reg_1p2v: regulator-1p2v { 127 compatible = "regulator-fixed"; 128 regulator-name = "fixed-1.2V"; 129 regulator-min-microvolt = <1200000>; 130 regulator-max-microvolt = <1200000>; 131 regulator-boot-on; 132 regulator-always-on; 133 }; 134 135 reg_1p8v: regulator-1p8v { 136 compatible = "regulator-fixed"; 137 regulator-name = "fixed-1.8V"; 138 regulator-min-microvolt = <1800000>; 139 regulator-max-microvolt = <1800000>; 140 regulator-boot-on; 141 regulator-always-on; 142 }; 143 144 reg_3p3v: regulator-3p3v { 145 compatible = "regulator-fixed"; 146 regulator-name = "fixed-3.3V"; 147 regulator-min-microvolt = <3300000>; 148 regulator-max-microvolt = <3300000>; 149 regulator-boot-on; 150 regulator-always-on; 151 }; 152}; 153 154&avb0 { 155 pinctrl-0 = <&avb0_pins>; 156 pinctrl-names = "default"; 157 phy-handle = <&avb0_phy>; 158 tx-internal-delay-ps = <2000>; 159 status = "okay"; 160 161 mdio { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 avb0_phy: ethernet-phy@0 { 166 compatible = "ethernet-phy-id0022.1622", 167 "ethernet-phy-ieee802.3-c22"; 168 rxc-skew-ps = <1500>; 169 reg = <0>; 170 interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; 171 reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 172 }; 173 }; 174}; 175 176&dsi0 { 177 status = "okay"; 178 179 ports { 180 port@1 { 181 dsi0_out: endpoint { 182 remote-endpoint = <&sn65dsi86_in>; 183 data-lanes = <1 2 3 4>; 184 }; 185 }; 186 }; 187}; 188 189&du { 190 status = "okay"; 191}; 192 193&extal_clk { 194 clock-frequency = <16666666>; 195}; 196 197&extalr_clk { 198 clock-frequency = <32768>; 199}; 200 201&hscif0 { 202 pinctrl-0 = <&hscif0_pins>; 203 pinctrl-names = "default"; 204 bootph-all; 205 206 status = "okay"; 207}; 208 209&i2c0 { 210 pinctrl-0 = <&i2c0_pins>; 211 pinctrl-names = "default"; 212 213 status = "okay"; 214 clock-frequency = <400000>; 215 216 io_expander_a: gpio@20 { 217 compatible = "onnn,pca9654"; 218 reg = <0x20>; 219 interrupts-extended = <&gpio0 0 IRQ_TYPE_LEVEL_LOW>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 }; 225 226 eeprom@50 { 227 compatible = "rohm,br24g01", "atmel,24c01"; 228 label = "cpu-board"; 229 reg = <0x50>; 230 pagesize = <8>; 231 }; 232}; 233 234&i2c1 { 235 pinctrl-0 = <&i2c1_pins>; 236 pinctrl-names = "default"; 237 238 status = "okay"; 239 clock-frequency = <400000>; 240 241 bridge@2c { 242 pinctrl-0 = <&irq0_pins>; 243 pinctrl-names = "default"; 244 245 compatible = "ti,sn65dsi86"; 246 reg = <0x2c>; 247 248 clocks = <&sn65dsi86_refclk>; 249 clock-names = "refclk"; 250 251 interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; 252 253 enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 254 255 vccio-supply = <®_1p8v>; 256 vpll-supply = <®_1p8v>; 257 vcca-supply = <®_1p2v>; 258 vcc-supply = <®_1p2v>; 259 260 ports { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 port@0 { 265 reg = <0>; 266 sn65dsi86_in: endpoint { 267 remote-endpoint = <&dsi0_out>; 268 }; 269 }; 270 271 port@1 { 272 reg = <1>; 273 sn65dsi86_out: endpoint { 274 remote-endpoint = <&mini_dp_con_in>; 275 }; 276 }; 277 }; 278 }; 279}; 280 281&mmc0 { 282 pinctrl-0 = <&mmc_pins>; 283 pinctrl-1 = <&mmc_pins>; 284 pinctrl-names = "default", "state_uhs"; 285 286 vmmc-supply = <®_3p3v>; 287 vqmmc-supply = <®_1p8v>; 288 mmc-hs200-1_8v; 289 mmc-hs400-1_8v; 290 bus-width = <8>; 291 no-sd; 292 no-sdio; 293 non-removable; 294 full-pwr-cycle-in-suspend; 295 status = "okay"; 296}; 297 298&pcie0_clkref { 299 compatible = "gpio-gate-clock"; 300 clocks = <&pcie_clk>; 301 enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 302 /delete-property/ clock-frequency; 303}; 304 305&pciec0 { 306 reset-gpios = <&io_expander_a 0 GPIO_ACTIVE_LOW>; 307 status = "okay"; 308}; 309 310&pfc { 311 pinctrl-0 = <&scif_clk_pins>; 312 pinctrl-names = "default"; 313 314 avb0_pins: avb0 { 315 mux { 316 groups = "avb0_link", "avb0_mdio", "avb0_rgmii", 317 "avb0_txcrefclk"; 318 function = "avb0"; 319 }; 320 321 pins_mdio { 322 groups = "avb0_mdio"; 323 drive-strength = <21>; 324 }; 325 326 pins_mii { 327 groups = "avb0_rgmii"; 328 drive-strength = <21>; 329 }; 330 331 }; 332 333 hscif0_pins: hscif0 { 334 groups = "hscif0_data"; 335 function = "hscif0"; 336 }; 337 338 i2c0_pins: i2c0 { 339 groups = "i2c0"; 340 function = "i2c0"; 341 }; 342 343 i2c1_pins: i2c1 { 344 groups = "i2c1"; 345 function = "i2c1"; 346 }; 347 348 irq0_pins: irq0 { 349 groups = "intc_ex_irq0_a"; 350 function = "intc_ex"; 351 }; 352 353 keys_pins: keys { 354 pins = "GP_5_0", "GP_5_1", "GP_5_2"; 355 bias-pull-up; 356 }; 357 358 mmc_pins: mmc { 359 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 360 function = "mmc"; 361 power-source = <1800>; 362 }; 363 364 qspi0_pins: qspi0 { 365 groups = "qspi0_ctrl", "qspi0_data4"; 366 function = "qspi0"; 367 }; 368 369 scif_clk_pins: scif_clk { 370 groups = "scif_clk"; 371 function = "scif_clk"; 372 }; 373}; 374 375&rpc { 376 pinctrl-0 = <&qspi0_pins>; 377 pinctrl-names = "default"; 378 379 status = "okay"; 380 381 flash@0 { 382 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 383 reg = <0>; 384 spi-max-frequency = <40000000>; 385 spi-rx-bus-width = <4>; 386 387 partitions { 388 compatible = "fixed-partitions"; 389 #address-cells = <1>; 390 #size-cells = <1>; 391 392 boot@0 { 393 reg = <0x0 0x1200000>; 394 read-only; 395 }; 396 user@1200000 { 397 reg = <0x1200000 0x2e00000>; 398 }; 399 }; 400 }; 401}; 402 403&rwdt { 404 timeout-sec = <60>; 405 status = "okay"; 406}; 407 408&scif_clk { 409 clock-frequency = <24000000>; 410}; 411