1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree Source for the R-Car S4 Starter Kit board
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include <dt-bindings/gpio/gpio.h>
10#include "r8a779f4.dtsi"
11
12/ {
13	model = "R-Car S4 Starter Kit board";
14	compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0";
15
16	aliases {
17		i2c0 = &i2c0;
18		i2c1 = &i2c1;
19		i2c2 = &i2c2;
20		i2c3 = &i2c3;
21		i2c4 = &i2c4;
22		i2c5 = &i2c5;
23		serial0 = &hscif0;
24		serial1 = &hscif1;
25		ethernet0 = &rswitch_port0;
26		ethernet1 = &rswitch_port1;
27	};
28
29	chosen {
30		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
31		stdout-path = "serial0:921600n8";
32	};
33
34	memory@48000000 {
35		device_type = "memory";
36		/* first 128MB is reserved for secure area. */
37		/* The last 512MB is reserved for CR. */
38		reg = <0x0 0x48000000 0x0 0x58000000>;
39	};
40
41	memory@480000000 {
42		device_type = "memory";
43		reg = <0x4 0x80000000 0x0 0x80000000>;
44	};
45
46	vcc_sdhi: regulator-vcc-sdhi {
47		compatible = "regulator-fixed";
48		regulator-name = "SDHI Vcc";
49		regulator-min-microvolt = <3300000>;
50		regulator-max-microvolt = <3300000>;
51		gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
52		enable-active-high;
53	};
54};
55
56&eth_serdes {
57	status = "okay";
58};
59
60&extal_clk {
61	clock-frequency = <20000000>;
62};
63
64&extalr_clk {
65	clock-frequency = <32768>;
66};
67
68&hscif0 {
69	pinctrl-0 = <&hscif0_pins>;
70	pinctrl-names = "default";
71	bootph-all;
72
73	uart-has-rtscts;
74	status = "okay";
75};
76
77&hscif1 {
78	pinctrl-0 = <&hscif1_pins>;
79	pinctrl-names = "default";
80
81	uart-has-rtscts;
82	status = "okay";
83};
84
85&i2c2 {
86	pinctrl-0 = <&i2c2_pins>;
87	pinctrl-names = "default";
88
89	status = "okay";
90	clock-frequency = <400000>;
91};
92
93&i2c4 {
94	pinctrl-0 = <&i2c4_pins>;
95	pinctrl-names = "default";
96
97	status = "okay";
98	clock-frequency = <400000>;
99};
100
101&i2c5 {
102	pinctrl-0 = <&i2c5_pins>;
103	pinctrl-names = "default";
104
105	status = "okay";
106	clock-frequency = <400000>;
107
108	eeprom@50 {
109		compatible = "st,24c16", "atmel,24c16";
110		reg = <0x50>;
111		pagesize = <16>;
112	};
113};
114
115&mmc0 {
116	pinctrl-0 = <&sd_pins>;
117	pinctrl-names = "default";
118
119	vmmc-supply = <&vcc_sdhi>;
120	cd-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
121	bus-width = <4>;
122	status = "okay";
123};
124
125&pfc {
126	pinctrl-0 = <&scif_clk_pins>;
127	pinctrl-names = "default";
128
129	hscif0_pins: hscif0 {
130		groups = "hscif0_data", "hscif0_ctrl";
131		function = "hscif0";
132	};
133
134	hscif1_pins: hscif1 {
135		groups = "hscif1_data", "hscif1_ctrl";
136		function = "hscif1";
137	};
138
139	i2c2_pins: i2c2 {
140		groups = "i2c2";
141		function = "i2c2";
142	};
143
144	i2c4_pins: i2c4 {
145		groups = "i2c4";
146		function = "i2c4";
147	};
148
149	i2c5_pins: i2c5 {
150		groups = "i2c5";
151		function = "i2c5";
152	};
153
154	scif_clk_pins: scif_clk {
155		groups = "scif_clk";
156		function = "scif_clk";
157	};
158
159	sd_pins: sd {
160		groups = "mmc_data4", "mmc_ctrl";
161		function = "mmc";
162		power-source = <3300>;
163	};
164
165	tsn0_pins: tsn0 {
166		groups = "tsn0_mdio_b", "tsn0_link_b";
167		function = "tsn0";
168		drive-strength = <18>;
169		power-source = <3300>;
170	};
171
172	tsn1_pins: tsn1 {
173		groups = "tsn1_mdio_b", "tsn1_link_b";
174		function = "tsn1";
175		drive-strength = <18>;
176		power-source = <3300>;
177	};
178};
179
180&rswitch {
181	pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>;
182	pinctrl-names = "default";
183	status = "okay";
184};
185
186&rswitch_port0 {
187	reg = <0>;
188	phy-handle = <&ic99>;
189	phy-mode = "sgmii";
190	phys = <&eth_serdes 0>;
191	status = "okay";
192
193	mdio {
194		#address-cells = <1>;
195		#size-cells = <0>;
196
197		ic99: ethernet-phy@1 {
198			reg = <1>;
199			compatible = "ethernet-phy-ieee802.3-c45";
200			interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
201		};
202	};
203};
204
205&rswitch_port1 {
206	reg = <1>;
207	phy-handle = <&ic102>;
208	phy-mode = "sgmii";
209	phys = <&eth_serdes 1>;
210	status = "okay";
211
212	mdio {
213		#address-cells = <1>;
214		#size-cells = <0>;
215
216		ic102: ethernet-phy@2 {
217			reg = <2>;
218			compatible = "ethernet-phy-ieee802.3-c45";
219			interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
220		};
221	};
222};
223
224&rwdt {
225	timeout-sec = <60>;
226	status = "okay";
227};
228
229&scif_clk {
230	clock-frequency = <24000000>;
231};
232
233&ufs {
234	status = "okay";
235};
236
237&ufs30_clk {
238	clock-frequency = <38400000>;
239};
240