1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cluster01_opp: opp-table-0 { 18 compatible = "operating-points-v2"; 19 opp-shared; 20 21 opp-500000000 { 22 opp-hz = /bits/ 64 <500000000>; 23 opp-microvolt = <880000>; 24 clock-latency-ns = <500000>; 25 }; 26 opp-800000000 { 27 opp-hz = /bits/ 64 <800000000>; 28 opp-microvolt = <880000>; 29 clock-latency-ns = <500000>; 30 }; 31 opp-1000000000 { 32 opp-hz = /bits/ 64 <1000000000>; 33 opp-microvolt = <880000>; 34 clock-latency-ns = <500000>; 35 }; 36 opp-1200000000 { 37 opp-hz = /bits/ 64 <1200000000>; 38 opp-microvolt = <880000>; 39 clock-latency-ns = <500000>; 40 opp-suspend; 41 }; 42 }; 43 44 cluster23_opp: opp-table-1 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-500000000 { 49 opp-hz = /bits/ 64 <500000000>; 50 opp-microvolt = <880000>; 51 clock-latency-ns = <500000>; 52 }; 53 opp-800000000 { 54 opp-hz = /bits/ 64 <800000000>; 55 opp-microvolt = <880000>; 56 clock-latency-ns = <500000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <880000>; 61 clock-latency-ns = <500000>; 62 }; 63 opp-1200000000 { 64 opp-hz = /bits/ 64 <1200000000>; 65 opp-microvolt = <880000>; 66 clock-latency-ns = <500000>; 67 opp-suspend; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu-map { 76 cluster0 { 77 core0 { 78 cpu = <&a55_0>; 79 }; 80 core1 { 81 cpu = <&a55_1>; 82 }; 83 }; 84 85 cluster1 { 86 core0 { 87 cpu = <&a55_2>; 88 }; 89 core1 { 90 cpu = <&a55_3>; 91 }; 92 }; 93 94 cluster2 { 95 core0 { 96 cpu = <&a55_4>; 97 }; 98 core1 { 99 cpu = <&a55_5>; 100 }; 101 }; 102 103 cluster3 { 104 core0 { 105 cpu = <&a55_6>; 106 }; 107 core1 { 108 cpu = <&a55_7>; 109 }; 110 }; 111 }; 112 113 a55_0: cpu@0 { 114 compatible = "arm,cortex-a55"; 115 reg = <0>; 116 device_type = "cpu"; 117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 118 next-level-cache = <&L3_CA55_0>; 119 enable-method = "psci"; 120 cpu-idle-states = <&CPU_SLEEP_0>; 121 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 122 operating-points-v2 = <&cluster01_opp>; 123 }; 124 125 a55_1: cpu@100 { 126 compatible = "arm,cortex-a55"; 127 reg = <0x100>; 128 device_type = "cpu"; 129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 130 next-level-cache = <&L3_CA55_0>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 134 operating-points-v2 = <&cluster01_opp>; 135 }; 136 137 a55_2: cpu@10000 { 138 compatible = "arm,cortex-a55"; 139 reg = <0x10000>; 140 device_type = "cpu"; 141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 142 next-level-cache = <&L3_CA55_1>; 143 enable-method = "psci"; 144 cpu-idle-states = <&CPU_SLEEP_0>; 145 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 146 operating-points-v2 = <&cluster01_opp>; 147 }; 148 149 a55_3: cpu@10100 { 150 compatible = "arm,cortex-a55"; 151 reg = <0x10100>; 152 device_type = "cpu"; 153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 154 next-level-cache = <&L3_CA55_1>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 158 operating-points-v2 = <&cluster01_opp>; 159 }; 160 161 a55_4: cpu@20000 { 162 compatible = "arm,cortex-a55"; 163 reg = <0x20000>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 166 next-level-cache = <&L3_CA55_2>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0>; 169 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 170 operating-points-v2 = <&cluster23_opp>; 171 }; 172 173 a55_5: cpu@20100 { 174 compatible = "arm,cortex-a55"; 175 reg = <0x20100>; 176 device_type = "cpu"; 177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 178 next-level-cache = <&L3_CA55_2>; 179 enable-method = "psci"; 180 cpu-idle-states = <&CPU_SLEEP_0>; 181 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 182 operating-points-v2 = <&cluster23_opp>; 183 }; 184 185 a55_6: cpu@30000 { 186 compatible = "arm,cortex-a55"; 187 reg = <0x30000>; 188 device_type = "cpu"; 189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 190 next-level-cache = <&L3_CA55_3>; 191 enable-method = "psci"; 192 cpu-idle-states = <&CPU_SLEEP_0>; 193 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 194 operating-points-v2 = <&cluster23_opp>; 195 }; 196 197 a55_7: cpu@30100 { 198 compatible = "arm,cortex-a55"; 199 reg = <0x30100>; 200 device_type = "cpu"; 201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 202 next-level-cache = <&L3_CA55_3>; 203 enable-method = "psci"; 204 cpu-idle-states = <&CPU_SLEEP_0>; 205 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 206 operating-points-v2 = <&cluster23_opp>; 207 }; 208 209 L3_CA55_0: cache-controller-0 { 210 compatible = "cache"; 211 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 212 cache-unified; 213 cache-level = <3>; 214 }; 215 216 L3_CA55_1: cache-controller-1 { 217 compatible = "cache"; 218 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 219 cache-unified; 220 cache-level = <3>; 221 }; 222 223 L3_CA55_2: cache-controller-2 { 224 compatible = "cache"; 225 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 226 cache-unified; 227 cache-level = <3>; 228 }; 229 230 L3_CA55_3: cache-controller-3 { 231 compatible = "cache"; 232 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 233 cache-unified; 234 cache-level = <3>; 235 }; 236 237 idle-states { 238 entry-method = "psci"; 239 240 CPU_SLEEP_0: cpu-sleep-0 { 241 compatible = "arm,idle-state"; 242 arm,psci-suspend-param = <0x0010000>; 243 local-timer-stop; 244 entry-latency-us = <400>; 245 exit-latency-us = <500>; 246 min-residency-us = <4000>; 247 }; 248 }; 249 }; 250 251 extal_clk: extal { 252 compatible = "fixed-clock"; 253 #clock-cells = <0>; 254 /* This value must be overridden by the board */ 255 clock-frequency = <0>; 256 bootph-all; 257 }; 258 259 extalr_clk: extalr { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 /* This value must be overridden by the board */ 263 clock-frequency = <0>; 264 bootph-all; 265 }; 266 267 pcie0_clkref: pcie0-clkref { 268 compatible = "fixed-clock"; 269 #clock-cells = <0>; 270 /* This value must be overridden by the board */ 271 clock-frequency = <0>; 272 }; 273 274 pcie1_clkref: pcie1-clkref { 275 compatible = "fixed-clock"; 276 #clock-cells = <0>; 277 /* This value must be overridden by the board */ 278 clock-frequency = <0>; 279 }; 280 281 pmu_a55 { 282 compatible = "arm,cortex-a55-pmu"; 283 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 284 }; 285 286 psci { 287 compatible = "arm,psci-1.0", "arm,psci-0.2"; 288 method = "smc"; 289 }; 290 291 /* External SCIF clock - to be overridden by boards that provide it */ 292 scif_clk: scif { 293 compatible = "fixed-clock"; 294 #clock-cells = <0>; 295 clock-frequency = <0>; 296 }; 297 298 soc: soc { 299 compatible = "simple-bus"; 300 interrupt-parent = <&gic>; 301 bootph-all; 302 303 #address-cells = <2>; 304 #size-cells = <2>; 305 ranges; 306 307 rwdt: watchdog@e6020000 { 308 compatible = "renesas,r8a779f0-wdt", 309 "renesas,rcar-gen4-wdt"; 310 reg = <0 0xe6020000 0 0x0c>; 311 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&cpg CPG_MOD 907>; 313 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 314 resets = <&cpg 907>; 315 status = "disabled"; 316 }; 317 318 pfc: pinctrl@e6050000 { 319 compatible = "renesas,pfc-r8a779f0"; 320 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 321 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 322 bootph-all; 323 }; 324 325 gpio0: gpio@e6050180 { 326 compatible = "renesas,gpio-r8a779f0", 327 "renesas,rcar-gen4-gpio"; 328 reg = <0 0xe6050180 0 0x54>; 329 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&cpg CPG_MOD 915>; 331 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 332 resets = <&cpg 915>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 gpio-ranges = <&pfc 0 0 21>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 gpio1: gpio@e6050980 { 341 compatible = "renesas,gpio-r8a779f0", 342 "renesas,rcar-gen4-gpio"; 343 reg = <0 0xe6050980 0 0x54>; 344 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&cpg CPG_MOD 915>; 346 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 347 resets = <&cpg 915>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 gpio-ranges = <&pfc 0 32 25>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 }; 354 355 gpio2: gpio@e6051180 { 356 compatible = "renesas,gpio-r8a779f0", 357 "renesas,rcar-gen4-gpio"; 358 reg = <0 0xe6051180 0 0x54>; 359 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cpg CPG_MOD 915>; 361 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 362 resets = <&cpg 915>; 363 gpio-controller; 364 #gpio-cells = <2>; 365 gpio-ranges = <&pfc 0 64 17>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 }; 369 370 gpio3: gpio@e6051980 { 371 compatible = "renesas,gpio-r8a779f0", 372 "renesas,rcar-gen4-gpio"; 373 reg = <0 0xe6051980 0 0x54>; 374 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 915>; 376 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 377 resets = <&cpg 915>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 gpio-ranges = <&pfc 0 96 19>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 }; 384 385 fuse: fuse@e6078800 { 386 compatible = "renesas,r8a779f0-efuse"; 387 reg = <0 0xe6078800 0 0x200>; 388 clocks = <&cpg CPG_MOD 915>; 389 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 390 resets = <&cpg 915>; 391 }; 392 393 cmt0: timer@e60f0000 { 394 compatible = "renesas,r8a779f0-cmt0", 395 "renesas,rcar-gen4-cmt0"; 396 reg = <0 0xe60f0000 0 0x1004>; 397 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 910>; 400 clock-names = "fck"; 401 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 402 resets = <&cpg 910>; 403 status = "disabled"; 404 }; 405 406 cmt1: timer@e6130000 { 407 compatible = "renesas,r8a779f0-cmt1", 408 "renesas,rcar-gen4-cmt1"; 409 reg = <0 0xe6130000 0 0x1004>; 410 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cpg CPG_MOD 911>; 419 clock-names = "fck"; 420 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 421 resets = <&cpg 911>; 422 status = "disabled"; 423 }; 424 425 cmt2: timer@e6140000 { 426 compatible = "renesas,r8a779f0-cmt1", 427 "renesas,rcar-gen4-cmt1"; 428 reg = <0 0xe6140000 0 0x1004>; 429 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cpg CPG_MOD 912>; 438 clock-names = "fck"; 439 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 440 resets = <&cpg 912>; 441 status = "disabled"; 442 }; 443 444 cmt3: timer@e6148000 { 445 compatible = "renesas,r8a779f0-cmt1", 446 "renesas,rcar-gen4-cmt1"; 447 reg = <0 0xe6148000 0 0x1004>; 448 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 913>; 457 clock-names = "fck"; 458 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 459 resets = <&cpg 913>; 460 status = "disabled"; 461 }; 462 463 cpg: clock-controller@e6150000 { 464 compatible = "renesas,r8a779f0-cpg-mssr"; 465 reg = <0 0xe6150000 0 0x4000>; 466 clocks = <&extal_clk>, <&extalr_clk>; 467 clock-names = "extal", "extalr"; 468 #clock-cells = <2>; 469 #power-domain-cells = <0>; 470 #reset-cells = <1>; 471 bootph-all; 472 }; 473 474 rst: reset-controller@e6160000 { 475 compatible = "renesas,r8a779f0-rst"; 476 reg = <0 0xe6160000 0 0x4000>; 477 bootph-all; 478 }; 479 480 sysc: system-controller@e6180000 { 481 compatible = "renesas,r8a779f0-sysc"; 482 reg = <0 0xe6180000 0 0x4000>; 483 #power-domain-cells = <1>; 484 }; 485 486 tsc: thermal@e6198000 { 487 compatible = "renesas,r8a779f0-thermal"; 488 /* The 4th sensor is in control domain and not for Linux */ 489 reg = <0 0xe6198000 0 0x200>, 490 <0 0xe61a0000 0 0x200>, 491 <0 0xe61a8000 0 0x200>; 492 clocks = <&cpg CPG_MOD 919>; 493 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 494 resets = <&cpg 919>; 495 #thermal-sensor-cells = <1>; 496 }; 497 498 intc_ex: interrupt-controller@e61c0000 { 499 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; 500 #interrupt-cells = <2>; 501 interrupt-controller; 502 reg = <0 0xe61c0000 0 0x200>; 503 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; 510 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 511 }; 512 513 tmu0: timer@e61e0000 { 514 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 515 reg = <0 0xe61e0000 0 0x30>; 516 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "tuni0", "tuni1", "tuni2"; 520 clocks = <&cpg CPG_MOD 713>; 521 clock-names = "fck"; 522 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 523 resets = <&cpg 713>; 524 status = "disabled"; 525 }; 526 527 tmu1: timer@e6fc0000 { 528 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 529 reg = <0 0xe6fc0000 0 0x30>; 530 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 535 clocks = <&cpg CPG_MOD 714>; 536 clock-names = "fck"; 537 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 538 resets = <&cpg 714>; 539 status = "disabled"; 540 }; 541 542 tmu2: timer@e6fd0000 { 543 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 544 reg = <0 0xe6fd0000 0 0x30>; 545 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 550 clocks = <&cpg CPG_MOD 715>; 551 clock-names = "fck"; 552 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 553 resets = <&cpg 715>; 554 status = "disabled"; 555 }; 556 557 tmu3: timer@e6fe0000 { 558 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 559 reg = <0 0xe6fe0000 0 0x30>; 560 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 565 clocks = <&cpg CPG_MOD 716>; 566 clock-names = "fck"; 567 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 568 resets = <&cpg 716>; 569 status = "disabled"; 570 }; 571 572 tmu4: timer@ffc00000 { 573 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 574 reg = <0 0xffc00000 0 0x30>; 575 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>; 579 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 580 clocks = <&cpg CPG_MOD 717>; 581 clock-names = "fck"; 582 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 583 resets = <&cpg 717>; 584 status = "disabled"; 585 }; 586 587 eth_serdes: phy@e6444000 { 588 compatible = "renesas,r8a779f0-ether-serdes"; 589 reg = <0 0xe6444000 0 0x2800>; 590 clocks = <&cpg CPG_MOD 1506>; 591 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 592 resets = <&cpg 1506>; 593 #phy-cells = <1>; 594 status = "disabled"; 595 }; 596 597 i2c0: i2c@e6500000 { 598 compatible = "renesas,i2c-r8a779f0", 599 "renesas,rcar-gen4-i2c"; 600 reg = <0 0xe6500000 0 0x40>; 601 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cpg CPG_MOD 518>; 603 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 604 resets = <&cpg 518>; 605 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 606 <&dmac1 0x91>, <&dmac1 0x90>; 607 dma-names = "tx", "rx", "tx", "rx"; 608 i2c-scl-internal-delay-ns = <110>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "disabled"; 612 }; 613 614 i2c1: i2c@e6508000 { 615 compatible = "renesas,i2c-r8a779f0", 616 "renesas,rcar-gen4-i2c"; 617 reg = <0 0xe6508000 0 0x40>; 618 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cpg CPG_MOD 519>; 620 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 621 resets = <&cpg 519>; 622 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 623 <&dmac1 0x93>, <&dmac1 0x92>; 624 dma-names = "tx", "rx", "tx", "rx"; 625 i2c-scl-internal-delay-ns = <110>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c2: i2c@e6510000 { 632 compatible = "renesas,i2c-r8a779f0", 633 "renesas,rcar-gen4-i2c"; 634 reg = <0 0xe6510000 0 0x40>; 635 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&cpg CPG_MOD 520>; 637 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 638 resets = <&cpg 520>; 639 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 640 <&dmac1 0x95>, <&dmac1 0x94>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 i2c-scl-internal-delay-ns = <110>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 i2c3: i2c@e66d0000 { 649 compatible = "renesas,i2c-r8a779f0", 650 "renesas,rcar-gen4-i2c"; 651 reg = <0 0xe66d0000 0 0x40>; 652 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 521>; 654 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 655 resets = <&cpg 521>; 656 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 657 <&dmac1 0x97>, <&dmac1 0x96>; 658 dma-names = "tx", "rx", "tx", "rx"; 659 i2c-scl-internal-delay-ns = <110>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "disabled"; 663 }; 664 665 i2c4: i2c@e66d8000 { 666 compatible = "renesas,i2c-r8a779f0", 667 "renesas,rcar-gen4-i2c"; 668 reg = <0 0xe66d8000 0 0x40>; 669 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cpg CPG_MOD 522>; 671 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 672 resets = <&cpg 522>; 673 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 674 <&dmac1 0x99>, <&dmac1 0x98>; 675 dma-names = "tx", "rx", "tx", "rx"; 676 i2c-scl-internal-delay-ns = <110>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 status = "disabled"; 680 }; 681 682 i2c5: i2c@e66e0000 { 683 compatible = "renesas,i2c-r8a779f0", 684 "renesas,rcar-gen4-i2c"; 685 reg = <0 0xe66e0000 0 0x40>; 686 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&cpg CPG_MOD 523>; 688 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 689 resets = <&cpg 523>; 690 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 691 <&dmac1 0x9b>, <&dmac1 0x9a>; 692 dma-names = "tx", "rx", "tx", "rx"; 693 i2c-scl-internal-delay-ns = <110>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 status = "disabled"; 697 }; 698 699 hscif0: serial@e6540000 { 700 compatible = "renesas,hscif-r8a779f0", 701 "renesas,rcar-gen4-hscif", "renesas,hscif"; 702 reg = <0 0xe6540000 0 0x60>; 703 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cpg CPG_MOD 514>, 705 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 706 <&scif_clk>; 707 clock-names = "fck", "brg_int", "scif_clk"; 708 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 709 <&dmac1 0x31>, <&dmac1 0x30>; 710 dma-names = "tx", "rx", "tx", "rx"; 711 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 712 resets = <&cpg 514>; 713 status = "disabled"; 714 }; 715 716 hscif1: serial@e6550000 { 717 compatible = "renesas,hscif-r8a779f0", 718 "renesas,rcar-gen4-hscif", "renesas,hscif"; 719 reg = <0 0xe6550000 0 0x60>; 720 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cpg CPG_MOD 515>, 722 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 723 <&scif_clk>; 724 clock-names = "fck", "brg_int", "scif_clk"; 725 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 726 <&dmac1 0x33>, <&dmac1 0x32>; 727 dma-names = "tx", "rx", "tx", "rx"; 728 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 729 resets = <&cpg 515>; 730 status = "disabled"; 731 }; 732 733 hscif2: serial@e6560000 { 734 compatible = "renesas,hscif-r8a779f0", 735 "renesas,rcar-gen4-hscif", "renesas,hscif"; 736 reg = <0 0xe6560000 0 0x60>; 737 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD 516>, 739 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 740 <&scif_clk>; 741 clock-names = "fck", "brg_int", "scif_clk"; 742 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 743 <&dmac1 0x35>, <&dmac1 0x34>; 744 dma-names = "tx", "rx", "tx", "rx"; 745 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 746 resets = <&cpg 516>; 747 status = "disabled"; 748 }; 749 750 hscif3: serial@e66a0000 { 751 compatible = "renesas,hscif-r8a779f0", 752 "renesas,rcar-gen4-hscif", "renesas,hscif"; 753 reg = <0 0xe66a0000 0 0x60>; 754 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&cpg CPG_MOD 517>, 756 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 757 <&scif_clk>; 758 clock-names = "fck", "brg_int", "scif_clk"; 759 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 760 <&dmac1 0x37>, <&dmac1 0x36>; 761 dma-names = "tx", "rx", "tx", "rx"; 762 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 763 resets = <&cpg 517>; 764 status = "disabled"; 765 }; 766 767 pciec0: pcie@e65d0000 { 768 compatible = "renesas,r8a779f0-pcie", 769 "renesas,rcar-gen4-pcie"; 770 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, 771 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 772 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 773 <0 0xfe000000 0 0x400000>; 774 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 775 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 779 interrupt-names = "msi", "dma", "sft_ce", "app"; 780 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 781 clock-names = "core", "ref"; 782 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 783 resets = <&cpg 624>; 784 reset-names = "pwr"; 785 max-link-speed = <4>; 786 num-lanes = <2>; 787 #address-cells = <3>; 788 #size-cells = <2>; 789 bus-range = <0x00 0xff>; 790 device_type = "pci"; 791 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, 792 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; 793 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 794 #interrupt-cells = <1>; 795 interrupt-map-mask = <0 0 0 7>; 796 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 797 <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 798 <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 799 <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; 800 snps,enable-cdm-check; 801 status = "disabled"; 802 }; 803 804 pciec1: pcie@e65d8000 { 805 compatible = "renesas,r8a779f0-pcie", 806 "renesas,rcar-gen4-pcie"; 807 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>, 808 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, 809 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, 810 <0 0xee900000 0 0x400000>; 811 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 812 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "msi", "dma", "sft_ce", "app"; 817 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; 818 clock-names = "core", "ref"; 819 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 820 resets = <&cpg 625>; 821 reset-names = "pwr"; 822 max-link-speed = <4>; 823 num-lanes = <2>; 824 #address-cells = <3>; 825 #size-cells = <2>; 826 bus-range = <0x00 0xff>; 827 device_type = "pci"; 828 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>, 829 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; 830 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 831 #interrupt-cells = <1>; 832 interrupt-map-mask = <0 0 0 7>; 833 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 834 <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 835 <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 836 <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 837 snps,enable-cdm-check; 838 status = "disabled"; 839 }; 840 841 pciec0_ep: pcie-ep@e65d0000 { 842 compatible = "renesas,r8a779f0-pcie-ep", 843 "renesas,rcar-gen4-pcie-ep"; 844 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, 845 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 846 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 847 <0 0xfe000000 0 0x400000>; 848 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 849 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "dma", "sft_ce", "app"; 853 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 854 clock-names = "core", "ref"; 855 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 856 resets = <&cpg 624>; 857 reset-names = "pwr"; 858 max-link-speed = <4>; 859 num-lanes = <2>; 860 max-functions = /bits/ 8 <2>; 861 status = "disabled"; 862 }; 863 864 pciec1_ep: pcie-ep@e65d8000 { 865 compatible = "renesas,r8a779f0-pcie-ep", 866 "renesas,rcar-gen4-pcie-ep"; 867 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>, 868 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, 869 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, 870 <0 0xee900000 0 0x400000>; 871 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 872 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "dma", "sft_ce", "app"; 876 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; 877 clock-names = "core", "ref"; 878 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 879 resets = <&cpg 625>; 880 reset-names = "pwr"; 881 max-link-speed = <4>; 882 num-lanes = <2>; 883 max-functions = /bits/ 8 <2>; 884 status = "disabled"; 885 }; 886 887 ufs: ufs@e6860000 { 888 compatible = "renesas,r8a779f0-ufs"; 889 reg = <0 0xe6860000 0 0x100>; 890 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 892 clock-names = "fck", "ref_clk"; 893 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 894 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 895 resets = <&cpg 1514>; 896 status = "disabled"; 897 }; 898 899 rswitch: ethernet@e6880000 { 900 compatible = "renesas,r8a779f0-ether-switch"; 901 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; 902 reg-names = "base", "secure_base"; 903 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "mfwd_error", "race_error", 951 "coma_error", "gwca0_error", 952 "gwca1_error", "etha0_error", 953 "etha1_error", "etha2_error", 954 "gptp0_status", "gptp1_status", 955 "mfwd_status", "race_status", 956 "coma_status", "gwca0_status", 957 "gwca1_status", "etha0_status", 958 "etha1_status", "etha2_status", 959 "rmac0_status", "rmac1_status", 960 "rmac2_status", 961 "gwca0_rxtx0", "gwca0_rxtx1", 962 "gwca0_rxtx2", "gwca0_rxtx3", 963 "gwca0_rxtx4", "gwca0_rxtx5", 964 "gwca0_rxtx6", "gwca0_rxtx7", 965 "gwca1_rxtx0", "gwca1_rxtx1", 966 "gwca1_rxtx2", "gwca1_rxtx3", 967 "gwca1_rxtx4", "gwca1_rxtx5", 968 "gwca1_rxtx6", "gwca1_rxtx7", 969 "gwca0_rxts0", "gwca0_rxts1", 970 "gwca1_rxts0", "gwca1_rxts1", 971 "rmac0_mdio", "rmac1_mdio", 972 "rmac2_mdio", 973 "rmac0_phy", "rmac1_phy", 974 "rmac2_phy"; 975 clocks = <&cpg CPG_MOD 1505>; 976 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 977 resets = <&cpg 1505>; 978 status = "disabled"; 979 980 ethernet-ports { 981 #address-cells = <1>; 982 #size-cells = <0>; 983 984 rswitch_port0: port@0 { 985 reg = <0>; 986 phys = <ð_serdes 0>; 987 status = "disabled"; 988 }; 989 rswitch_port1: port@1 { 990 reg = <1>; 991 phys = <ð_serdes 1>; 992 status = "disabled"; 993 }; 994 rswitch_port2: port@2 { 995 reg = <2>; 996 phys = <ð_serdes 2>; 997 status = "disabled"; 998 }; 999 }; 1000 }; 1001 1002 scif0: serial@e6e60000 { 1003 compatible = "renesas,scif-r8a779f0", 1004 "renesas,rcar-gen4-scif", "renesas,scif"; 1005 reg = <0 0xe6e60000 0 64>; 1006 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&cpg CPG_MOD 702>, 1008 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1009 <&scif_clk>; 1010 clock-names = "fck", "brg_int", "scif_clk"; 1011 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 1012 <&dmac1 0x51>, <&dmac1 0x50>; 1013 dma-names = "tx", "rx", "tx", "rx"; 1014 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1015 resets = <&cpg 702>; 1016 status = "disabled"; 1017 }; 1018 1019 scif1: serial@e6e68000 { 1020 compatible = "renesas,scif-r8a779f0", 1021 "renesas,rcar-gen4-scif", "renesas,scif"; 1022 reg = <0 0xe6e68000 0 64>; 1023 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&cpg CPG_MOD 703>, 1025 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1026 <&scif_clk>; 1027 clock-names = "fck", "brg_int", "scif_clk"; 1028 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 1029 <&dmac1 0x53>, <&dmac1 0x52>; 1030 dma-names = "tx", "rx", "tx", "rx"; 1031 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1032 resets = <&cpg 703>; 1033 status = "disabled"; 1034 }; 1035 1036 scif3: serial@e6c50000 { 1037 compatible = "renesas,scif-r8a779f0", 1038 "renesas,rcar-gen4-scif", "renesas,scif"; 1039 reg = <0 0xe6c50000 0 64>; 1040 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&cpg CPG_MOD 704>, 1042 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1043 <&scif_clk>; 1044 clock-names = "fck", "brg_int", "scif_clk"; 1045 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 1046 <&dmac1 0x57>, <&dmac1 0x56>; 1047 dma-names = "tx", "rx", "tx", "rx"; 1048 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1049 resets = <&cpg 704>; 1050 status = "disabled"; 1051 }; 1052 1053 scif4: serial@e6c40000 { 1054 compatible = "renesas,scif-r8a779f0", 1055 "renesas,rcar-gen4-scif", "renesas,scif"; 1056 reg = <0 0xe6c40000 0 64>; 1057 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&cpg CPG_MOD 705>, 1059 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1060 <&scif_clk>; 1061 clock-names = "fck", "brg_int", "scif_clk"; 1062 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 1063 <&dmac1 0x59>, <&dmac1 0x58>; 1064 dma-names = "tx", "rx", "tx", "rx"; 1065 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1066 resets = <&cpg 705>; 1067 status = "disabled"; 1068 }; 1069 1070 msiof0: spi@e6e90000 { 1071 compatible = "renesas,msiof-r8a779f0", 1072 "renesas,rcar-gen4-msiof"; 1073 reg = <0 0xe6e90000 0 0x0064>; 1074 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&cpg CPG_MOD 618>; 1076 dmas = <&dmac0 0x41>, <&dmac0 0x40>, 1077 <&dmac1 0x41>, <&dmac1 0x40>; 1078 dma-names = "tx", "rx", "tx", "rx"; 1079 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1080 resets = <&cpg 618>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 status = "disabled"; 1084 }; 1085 1086 msiof1: spi@e6ea0000 { 1087 compatible = "renesas,msiof-r8a779f0", 1088 "renesas,rcar-gen4-msiof"; 1089 reg = <0 0xe6ea0000 0 0x0064>; 1090 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&cpg CPG_MOD 619>; 1092 dmas = <&dmac0 0x43>, <&dmac0 0x42>, 1093 <&dmac1 0x43>, <&dmac1 0x42>; 1094 dma-names = "tx", "rx", "tx", "rx"; 1095 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1096 resets = <&cpg 619>; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 status = "disabled"; 1100 }; 1101 1102 msiof2: spi@e6c00000 { 1103 compatible = "renesas,msiof-r8a779f0", 1104 "renesas,rcar-gen4-msiof"; 1105 reg = <0 0xe6c00000 0 0x0064>; 1106 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&cpg CPG_MOD 620>; 1108 dmas = <&dmac0 0x45>, <&dmac0 0x44>, 1109 <&dmac1 0x45>, <&dmac1 0x44>; 1110 dma-names = "tx", "rx", "tx", "rx"; 1111 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1112 resets = <&cpg 620>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 status = "disabled"; 1116 }; 1117 1118 msiof3: spi@e6c10000 { 1119 compatible = "renesas,msiof-r8a779f0", 1120 "renesas,rcar-gen4-msiof"; 1121 reg = <0 0xe6c10000 0 0x0064>; 1122 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&cpg CPG_MOD 621>; 1124 dmas = <&dmac0 0x47>, <&dmac0 0x46>, 1125 <&dmac1 0x47>, <&dmac1 0x46>; 1126 dma-names = "tx", "rx", "tx", "rx"; 1127 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1128 resets = <&cpg 621>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 status = "disabled"; 1132 }; 1133 1134 dmac0: dma-controller@e7350000 { 1135 compatible = "renesas,dmac-r8a779f0", 1136 "renesas,rcar-gen4-dmac"; 1137 reg = <0 0xe7350000 0 0x1000>, 1138 <0 0xe7300000 0 0x10000>; 1139 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1156 interrupt-names = "error", 1157 "ch0", "ch1", "ch2", "ch3", "ch4", 1158 "ch5", "ch6", "ch7", "ch8", "ch9", 1159 "ch10", "ch11", "ch12", "ch13", 1160 "ch14", "ch15"; 1161 clocks = <&cpg CPG_MOD 709>; 1162 clock-names = "fck"; 1163 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1164 resets = <&cpg 709>; 1165 #dma-cells = <1>; 1166 dma-channels = <16>; 1167 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1168 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1169 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1170 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1171 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1172 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1173 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1174 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1175 }; 1176 1177 dmac1: dma-controller@e7351000 { 1178 compatible = "renesas,dmac-r8a779f0", 1179 "renesas,rcar-gen4-dmac"; 1180 reg = <0 0xe7351000 0 0x1000>, 1181 <0 0xe7310000 0 0x10000>; 1182 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1199 interrupt-names = "error", 1200 "ch0", "ch1", "ch2", "ch3", "ch4", 1201 "ch5", "ch6", "ch7", "ch8", "ch9", 1202 "ch10", "ch11", "ch12", "ch13", 1203 "ch14", "ch15"; 1204 clocks = <&cpg CPG_MOD 710>; 1205 clock-names = "fck"; 1206 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1207 resets = <&cpg 710>; 1208 #dma-cells = <1>; 1209 dma-channels = <16>; 1210 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 1211 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 1212 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 1213 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 1214 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 1215 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 1216 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 1217 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 1218 }; 1219 1220 mmc0: mmc@ee140000 { 1221 compatible = "renesas,sdhi-r8a779f0", 1222 "renesas,rcar-gen4-sdhi"; 1223 reg = <0 0xee140000 0 0x2000>; 1224 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; 1226 clock-names = "core", "clkh"; 1227 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1228 resets = <&cpg 706>; 1229 max-frequency = <200000000>; 1230 iommus = <&ipmmu_ds0 32>; 1231 status = "disabled"; 1232 }; 1233 1234 ipmmu_rt0: iommu@ee480000 { 1235 compatible = "renesas,ipmmu-r8a779f0", 1236 "renesas,rcar-gen4-ipmmu-vmsa"; 1237 reg = <0 0xee480000 0 0x20000>; 1238 renesas,ipmmu-main = <&ipmmu_mm>; 1239 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1240 #iommu-cells = <1>; 1241 }; 1242 1243 ipmmu_rt1: iommu@ee4c0000 { 1244 compatible = "renesas,ipmmu-r8a779f0", 1245 "renesas,rcar-gen4-ipmmu-vmsa"; 1246 reg = <0 0xee4c0000 0 0x20000>; 1247 renesas,ipmmu-main = <&ipmmu_mm>; 1248 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1249 #iommu-cells = <1>; 1250 }; 1251 1252 ipmmu_ds0: iommu@eed00000 { 1253 compatible = "renesas,ipmmu-r8a779f0", 1254 "renesas,rcar-gen4-ipmmu-vmsa"; 1255 reg = <0 0xeed00000 0 0x20000>; 1256 renesas,ipmmu-main = <&ipmmu_mm>; 1257 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1258 #iommu-cells = <1>; 1259 }; 1260 1261 ipmmu_hc: iommu@eed40000 { 1262 compatible = "renesas,ipmmu-r8a779f0", 1263 "renesas,rcar-gen4-ipmmu-vmsa"; 1264 reg = <0 0xeed40000 0 0x20000>; 1265 renesas,ipmmu-main = <&ipmmu_mm>; 1266 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1267 #iommu-cells = <1>; 1268 }; 1269 1270 ipmmu_mm: iommu@eefc0000 { 1271 compatible = "renesas,ipmmu-r8a779f0", 1272 "renesas,rcar-gen4-ipmmu-vmsa"; 1273 reg = <0 0xeefc0000 0 0x20000>; 1274 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1276 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1277 #iommu-cells = <1>; 1278 }; 1279 1280 gic: interrupt-controller@f1000000 { 1281 compatible = "arm,gic-v3"; 1282 #interrupt-cells = <3>; 1283 #address-cells = <0>; 1284 interrupt-controller; 1285 reg = <0x0 0xf1000000 0 0x20000>, 1286 <0x0 0xf1060000 0 0x110000>; 1287 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1288 }; 1289 1290 prr: chipid@fff00044 { 1291 compatible = "renesas,prr"; 1292 reg = <0 0xfff00044 0 4>; 1293 bootph-all; 1294 }; 1295 }; 1296 1297 thermal-zones { 1298 sensor_thermal_rtcore: sensor1-thermal { 1299 polling-delay-passive = <250>; 1300 polling-delay = <1000>; 1301 thermal-sensors = <&tsc 0>; 1302 1303 trips { 1304 sensor1_crit: sensor1-crit { 1305 temperature = <120000>; 1306 hysteresis = <1000>; 1307 type = "critical"; 1308 }; 1309 }; 1310 }; 1311 1312 sensor_thermal_apcore0: sensor2-thermal { 1313 polling-delay-passive = <250>; 1314 polling-delay = <1000>; 1315 thermal-sensors = <&tsc 1>; 1316 1317 trips { 1318 sensor2_crit: sensor2-crit { 1319 temperature = <120000>; 1320 hysteresis = <1000>; 1321 type = "critical"; 1322 }; 1323 }; 1324 }; 1325 1326 sensor_thermal_apcore4: sensor3-thermal { 1327 polling-delay-passive = <250>; 1328 polling-delay = <1000>; 1329 thermal-sensors = <&tsc 2>; 1330 1331 trips { 1332 sensor3_crit: sensor3-crit { 1333 temperature = <120000>; 1334 hysteresis = <1000>; 1335 type = "critical"; 1336 }; 1337 }; 1338 }; 1339 }; 1340 1341 timer { 1342 compatible = "arm,armv8-timer"; 1343 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1344 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1345 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1346 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1347 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1348 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 1349 "hyp-virt"; 1350 }; 1351 1352 ufs30_clk: ufs30-clk { 1353 compatible = "fixed-clock"; 1354 #clock-cells = <0>; 1355 /* This value must be overridden by the board */ 1356 clock-frequency = <0>; 1357 }; 1358}; 1359