1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp-table-1 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 51 opp-800000000 { 52 opp-hz = /bits/ 64 <800000000>; 53 opp-microvolt = <1030000>; 54 clock-latency-ns = <300000>; 55 }; 56 opp-1000000000 { 57 opp-hz = /bits/ 64 <1000000000>; 58 opp-microvolt = <1030000>; 59 clock-latency-ns = <300000>; 60 }; 61 opp-1200000000 { 62 opp-hz = /bits/ 64 <1200000000>; 63 opp-microvolt = <1030000>; 64 clock-latency-ns = <300000>; 65 opp-suspend; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 a53_0: cpu@0 { 74 compatible = "arm,cortex-a53"; 75 reg = <0>; 76 device_type = "cpu"; 77 #cooling-cells = <2>; 78 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 79 next-level-cache = <&L2_CA53>; 80 enable-method = "psci"; 81 dynamic-power-coefficient = <277>; 82 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 83 operating-points-v2 = <&cluster1_opp>; 84 }; 85 86 a53_1: cpu@1 { 87 compatible = "arm,cortex-a53"; 88 reg = <1>; 89 device_type = "cpu"; 90 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 91 next-level-cache = <&L2_CA53>; 92 enable-method = "psci"; 93 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 94 operating-points-v2 = <&cluster1_opp>; 95 }; 96 97 L2_CA53: cache-controller-0 { 98 compatible = "cache"; 99 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 100 cache-unified; 101 cache-level = <2>; 102 }; 103 }; 104 105 extal_clk: extal { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 /* This value must be overridden by the board */ 109 clock-frequency = <0>; 110 bootph-all; 111 }; 112 113 /* External PCIe clock - can be overridden by the board */ 114 pcie_bus_clk: pcie_bus { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <0>; 118 }; 119 120 pmu_a53 { 121 compatible = "arm,cortex-a53-pmu"; 122 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 123 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 124 interrupt-affinity = <&a53_0>, <&a53_1>; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0", "arm,psci-0.2"; 129 method = "smc"; 130 }; 131 132 /* External SCIF clock - to be overridden by boards that provide it */ 133 scif_clk: scif { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <0>; 137 }; 138 139 soc: soc { 140 compatible = "simple-bus"; 141 interrupt-parent = <&gic>; 142 bootph-all; 143 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 rwdt: watchdog@e6020000 { 149 compatible = "renesas,r8a774c0-wdt", 150 "renesas,rcar-gen3-wdt"; 151 reg = <0 0xe6020000 0 0x0c>; 152 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&cpg CPG_MOD 402>; 154 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 155 resets = <&cpg 402>; 156 status = "disabled"; 157 }; 158 159 gpio0: gpio@e6050000 { 160 compatible = "renesas,gpio-r8a774c0", 161 "renesas,rcar-gen3-gpio"; 162 reg = <0 0xe6050000 0 0x50>; 163 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 164 #gpio-cells = <2>; 165 gpio-controller; 166 gpio-ranges = <&pfc 0 0 18>; 167 #interrupt-cells = <2>; 168 interrupt-controller; 169 clocks = <&cpg CPG_MOD 912>; 170 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 171 resets = <&cpg 912>; 172 }; 173 174 gpio1: gpio@e6051000 { 175 compatible = "renesas,gpio-r8a774c0", 176 "renesas,rcar-gen3-gpio"; 177 reg = <0 0xe6051000 0 0x50>; 178 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 179 #gpio-cells = <2>; 180 gpio-controller; 181 gpio-ranges = <&pfc 0 32 23>; 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 clocks = <&cpg CPG_MOD 911>; 185 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 186 resets = <&cpg 911>; 187 }; 188 189 gpio2: gpio@e6052000 { 190 compatible = "renesas,gpio-r8a774c0", 191 "renesas,rcar-gen3-gpio"; 192 reg = <0 0xe6052000 0 0x50>; 193 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 194 #gpio-cells = <2>; 195 gpio-controller; 196 gpio-ranges = <&pfc 0 64 26>; 197 #interrupt-cells = <2>; 198 interrupt-controller; 199 clocks = <&cpg CPG_MOD 910>; 200 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 201 resets = <&cpg 910>; 202 }; 203 204 gpio3: gpio@e6053000 { 205 compatible = "renesas,gpio-r8a774c0", 206 "renesas,rcar-gen3-gpio"; 207 reg = <0 0xe6053000 0 0x50>; 208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 209 #gpio-cells = <2>; 210 gpio-controller; 211 gpio-ranges = <&pfc 0 96 16>; 212 #interrupt-cells = <2>; 213 interrupt-controller; 214 clocks = <&cpg CPG_MOD 909>; 215 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 216 resets = <&cpg 909>; 217 }; 218 219 gpio4: gpio@e6054000 { 220 compatible = "renesas,gpio-r8a774c0", 221 "renesas,rcar-gen3-gpio"; 222 reg = <0 0xe6054000 0 0x50>; 223 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 224 #gpio-cells = <2>; 225 gpio-controller; 226 gpio-ranges = <&pfc 0 128 11>; 227 #interrupt-cells = <2>; 228 interrupt-controller; 229 clocks = <&cpg CPG_MOD 908>; 230 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 231 resets = <&cpg 908>; 232 }; 233 234 gpio5: gpio@e6055000 { 235 compatible = "renesas,gpio-r8a774c0", 236 "renesas,rcar-gen3-gpio"; 237 reg = <0 0xe6055000 0 0x50>; 238 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 239 #gpio-cells = <2>; 240 gpio-controller; 241 gpio-ranges = <&pfc 0 160 20>; 242 #interrupt-cells = <2>; 243 interrupt-controller; 244 clocks = <&cpg CPG_MOD 907>; 245 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 246 resets = <&cpg 907>; 247 }; 248 249 gpio6: gpio@e6055400 { 250 compatible = "renesas,gpio-r8a774c0", 251 "renesas,rcar-gen3-gpio"; 252 reg = <0 0xe6055400 0 0x50>; 253 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 254 #gpio-cells = <2>; 255 gpio-controller; 256 gpio-ranges = <&pfc 0 192 18>; 257 #interrupt-cells = <2>; 258 interrupt-controller; 259 clocks = <&cpg CPG_MOD 906>; 260 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 261 resets = <&cpg 906>; 262 }; 263 264 pfc: pinctrl@e6060000 { 265 compatible = "renesas,pfc-r8a774c0"; 266 reg = <0 0xe6060000 0 0x508>; 267 bootph-all; 268 }; 269 270 cmt0: timer@e60f0000 { 271 compatible = "renesas,r8a774c0-cmt0", 272 "renesas,rcar-gen3-cmt0"; 273 reg = <0 0xe60f0000 0 0x1004>; 274 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cpg CPG_MOD 303>; 277 clock-names = "fck"; 278 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 279 resets = <&cpg 303>; 280 status = "disabled"; 281 }; 282 283 cmt1: timer@e6130000 { 284 compatible = "renesas,r8a774c0-cmt1", 285 "renesas,rcar-gen3-cmt1"; 286 reg = <0 0xe6130000 0 0x1004>; 287 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&cpg CPG_MOD 302>; 296 clock-names = "fck"; 297 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 298 resets = <&cpg 302>; 299 status = "disabled"; 300 }; 301 302 cmt2: timer@e6140000 { 303 compatible = "renesas,r8a774c0-cmt1", 304 "renesas,rcar-gen3-cmt1"; 305 reg = <0 0xe6140000 0 0x1004>; 306 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cpg CPG_MOD 301>; 315 clock-names = "fck"; 316 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 317 resets = <&cpg 301>; 318 status = "disabled"; 319 }; 320 321 cmt3: timer@e6148000 { 322 compatible = "renesas,r8a774c0-cmt1", 323 "renesas,rcar-gen3-cmt1"; 324 reg = <0 0xe6148000 0 0x1004>; 325 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cpg CPG_MOD 300>; 334 clock-names = "fck"; 335 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 336 resets = <&cpg 300>; 337 status = "disabled"; 338 }; 339 340 cpg: clock-controller@e6150000 { 341 compatible = "renesas,r8a774c0-cpg-mssr"; 342 reg = <0 0xe6150000 0 0x1000>; 343 clocks = <&extal_clk>; 344 clock-names = "extal"; 345 #clock-cells = <2>; 346 #power-domain-cells = <0>; 347 #reset-cells = <1>; 348 bootph-all; 349 }; 350 351 rst: reset-controller@e6160000 { 352 compatible = "renesas,r8a774c0-rst"; 353 reg = <0 0xe6160000 0 0x0200>; 354 bootph-all; 355 }; 356 357 sysc: system-controller@e6180000 { 358 compatible = "renesas,r8a774c0-sysc"; 359 reg = <0 0xe6180000 0 0x0400>; 360 #power-domain-cells = <1>; 361 }; 362 363 thermal: thermal@e6190000 { 364 compatible = "renesas,thermal-r8a774c0"; 365 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 366 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cpg CPG_MOD 522>; 370 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 371 resets = <&cpg 522>; 372 #thermal-sensor-cells = <0>; 373 }; 374 375 intc_ex: interrupt-controller@e61c0000 { 376 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 377 #interrupt-cells = <2>; 378 interrupt-controller; 379 reg = <0 0xe61c0000 0 0x200>; 380 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cpg CPG_MOD 407>; 387 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 388 resets = <&cpg 407>; 389 }; 390 391 tmu0: timer@e61e0000 { 392 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 393 reg = <0 0xe61e0000 0 0x30>; 394 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "tuni0", "tuni1", "tuni2"; 398 clocks = <&cpg CPG_MOD 125>; 399 clock-names = "fck"; 400 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 401 resets = <&cpg 125>; 402 status = "disabled"; 403 }; 404 405 tmu1: timer@e6fc0000 { 406 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 407 reg = <0 0xe6fc0000 0 0x30>; 408 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 412 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 413 clocks = <&cpg CPG_MOD 124>; 414 clock-names = "fck"; 415 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 416 resets = <&cpg 124>; 417 status = "disabled"; 418 }; 419 420 tmu2: timer@e6fd0000 { 421 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 422 reg = <0 0xe6fd0000 0 0x30>; 423 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 427 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 428 clocks = <&cpg CPG_MOD 123>; 429 clock-names = "fck"; 430 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 431 resets = <&cpg 123>; 432 status = "disabled"; 433 }; 434 435 tmu3: timer@e6fe0000 { 436 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 437 reg = <0 0xe6fe0000 0 0x30>; 438 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-names = "tuni0", "tuni1", "tuni2"; 442 clocks = <&cpg CPG_MOD 122>; 443 clock-names = "fck"; 444 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 445 resets = <&cpg 122>; 446 status = "disabled"; 447 }; 448 449 tmu4: timer@ffc00000 { 450 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 451 reg = <0 0xffc00000 0 0x30>; 452 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "tuni0", "tuni1", "tuni2"; 456 clocks = <&cpg CPG_MOD 121>; 457 clock-names = "fck"; 458 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 459 resets = <&cpg 121>; 460 status = "disabled"; 461 }; 462 463 i2c0: i2c@e6500000 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 compatible = "renesas,i2c-r8a774c0", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe6500000 0 0x40>; 469 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 931>; 471 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 472 resets = <&cpg 931>; 473 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 474 <&dmac2 0x91>, <&dmac2 0x90>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 i2c-scl-internal-delay-ns = <110>; 477 status = "disabled"; 478 }; 479 480 i2c1: i2c@e6508000 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 compatible = "renesas,i2c-r8a774c0", 484 "renesas,rcar-gen3-i2c"; 485 reg = <0 0xe6508000 0 0x40>; 486 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 930>; 488 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 489 resets = <&cpg 930>; 490 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 491 <&dmac2 0x93>, <&dmac2 0x92>; 492 dma-names = "tx", "rx", "tx", "rx"; 493 i2c-scl-internal-delay-ns = <6>; 494 status = "disabled"; 495 }; 496 497 i2c2: i2c@e6510000 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 compatible = "renesas,i2c-r8a774c0", 501 "renesas,rcar-gen3-i2c"; 502 reg = <0 0xe6510000 0 0x40>; 503 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 929>; 505 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 506 resets = <&cpg 929>; 507 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 508 <&dmac2 0x95>, <&dmac2 0x94>; 509 dma-names = "tx", "rx", "tx", "rx"; 510 i2c-scl-internal-delay-ns = <6>; 511 status = "disabled"; 512 }; 513 514 i2c3: i2c@e66d0000 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 compatible = "renesas,i2c-r8a774c0", 518 "renesas,rcar-gen3-i2c"; 519 reg = <0 0xe66d0000 0 0x40>; 520 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cpg CPG_MOD 928>; 522 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 523 resets = <&cpg 928>; 524 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 525 dma-names = "tx", "rx"; 526 i2c-scl-internal-delay-ns = <110>; 527 status = "disabled"; 528 }; 529 530 i2c4: i2c@e66d8000 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 compatible = "renesas,i2c-r8a774c0", 534 "renesas,rcar-gen3-i2c"; 535 reg = <0 0xe66d8000 0 0x40>; 536 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&cpg CPG_MOD 927>; 538 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 539 resets = <&cpg 927>; 540 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 541 dma-names = "tx", "rx"; 542 i2c-scl-internal-delay-ns = <6>; 543 status = "disabled"; 544 }; 545 546 i2c5: i2c@e66e0000 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "renesas,i2c-r8a774c0", 550 "renesas,rcar-gen3-i2c"; 551 reg = <0 0xe66e0000 0 0x40>; 552 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&cpg CPG_MOD 919>; 554 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 555 resets = <&cpg 919>; 556 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 557 dma-names = "tx", "rx"; 558 i2c-scl-internal-delay-ns = <6>; 559 status = "disabled"; 560 }; 561 562 i2c6: i2c@e66e8000 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 compatible = "renesas,i2c-r8a774c0", 566 "renesas,rcar-gen3-i2c"; 567 reg = <0 0xe66e8000 0 0x40>; 568 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&cpg CPG_MOD 918>; 570 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 571 resets = <&cpg 918>; 572 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 573 dma-names = "tx", "rx"; 574 i2c-scl-internal-delay-ns = <6>; 575 status = "disabled"; 576 }; 577 578 i2c7: i2c@e6690000 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 compatible = "renesas,i2c-r8a774c0", 582 "renesas,rcar-gen3-i2c"; 583 reg = <0 0xe6690000 0 0x40>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cpg CPG_MOD 1003>; 586 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 587 resets = <&cpg 1003>; 588 i2c-scl-internal-delay-ns = <6>; 589 status = "disabled"; 590 }; 591 592 iic_pmic: i2c@e60b0000 { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 compatible = "renesas,iic-r8a774c0", 596 "renesas,rcar-gen3-iic", 597 "renesas,rmobile-iic"; 598 reg = <0 0xe60b0000 0 0x425>; 599 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 926>; 601 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 602 resets = <&cpg 926>; 603 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 604 dma-names = "tx", "rx"; 605 status = "disabled"; 606 }; 607 608 hscif0: serial@e6540000 { 609 compatible = "renesas,hscif-r8a774c0", 610 "renesas,rcar-gen3-hscif", 611 "renesas,hscif"; 612 reg = <0 0xe6540000 0 0x60>; 613 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&cpg CPG_MOD 520>, 615 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 616 <&scif_clk>; 617 clock-names = "fck", "brg_int", "scif_clk"; 618 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 619 <&dmac2 0x31>, <&dmac2 0x30>; 620 dma-names = "tx", "rx", "tx", "rx"; 621 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 622 resets = <&cpg 520>; 623 status = "disabled"; 624 }; 625 626 hscif1: serial@e6550000 { 627 compatible = "renesas,hscif-r8a774c0", 628 "renesas,rcar-gen3-hscif", 629 "renesas,hscif"; 630 reg = <0 0xe6550000 0 0x60>; 631 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 519>, 633 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 634 <&scif_clk>; 635 clock-names = "fck", "brg_int", "scif_clk"; 636 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 637 <&dmac2 0x33>, <&dmac2 0x32>; 638 dma-names = "tx", "rx", "tx", "rx"; 639 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 640 resets = <&cpg 519>; 641 status = "disabled"; 642 }; 643 644 hscif2: serial@e6560000 { 645 compatible = "renesas,hscif-r8a774c0", 646 "renesas,rcar-gen3-hscif", 647 "renesas,hscif"; 648 reg = <0 0xe6560000 0 0x60>; 649 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 518>, 651 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 652 <&scif_clk>; 653 clock-names = "fck", "brg_int", "scif_clk"; 654 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 655 <&dmac2 0x35>, <&dmac2 0x34>; 656 dma-names = "tx", "rx", "tx", "rx"; 657 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 658 resets = <&cpg 518>; 659 status = "disabled"; 660 }; 661 662 hscif3: serial@e66a0000 { 663 compatible = "renesas,hscif-r8a774c0", 664 "renesas,rcar-gen3-hscif", 665 "renesas,hscif"; 666 reg = <0 0xe66a0000 0 0x60>; 667 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&cpg CPG_MOD 517>, 669 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 670 <&scif_clk>; 671 clock-names = "fck", "brg_int", "scif_clk"; 672 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 673 dma-names = "tx", "rx"; 674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 675 resets = <&cpg 517>; 676 status = "disabled"; 677 }; 678 679 hscif4: serial@e66b0000 { 680 compatible = "renesas,hscif-r8a774c0", 681 "renesas,rcar-gen3-hscif", 682 "renesas,hscif"; 683 reg = <0 0xe66b0000 0 0x60>; 684 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cpg CPG_MOD 516>, 686 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 687 <&scif_clk>; 688 clock-names = "fck", "brg_int", "scif_clk"; 689 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 690 dma-names = "tx", "rx"; 691 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 692 resets = <&cpg 516>; 693 status = "disabled"; 694 }; 695 696 hsusb: usb@e6590000 { 697 compatible = "renesas,usbhs-r8a774c0", 698 "renesas,rcar-gen3-usbhs"; 699 reg = <0 0xe6590000 0 0x200>; 700 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 702 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 703 <&usb_dmac1 0>, <&usb_dmac1 1>; 704 dma-names = "ch0", "ch1", "ch2", "ch3"; 705 renesas,buswait = <11>; 706 phys = <&usb2_phy0 3>; 707 phy-names = "usb"; 708 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 709 resets = <&cpg 704>, <&cpg 703>; 710 status = "disabled"; 711 }; 712 713 usb_dmac0: dma-controller@e65a0000 { 714 compatible = "renesas,r8a774c0-usb-dmac", 715 "renesas,usb-dmac"; 716 reg = <0 0xe65a0000 0 0x100>; 717 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "ch0", "ch1"; 720 clocks = <&cpg CPG_MOD 330>; 721 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 722 resets = <&cpg 330>; 723 #dma-cells = <1>; 724 dma-channels = <2>; 725 }; 726 727 usb_dmac1: dma-controller@e65b0000 { 728 compatible = "renesas,r8a774c0-usb-dmac", 729 "renesas,usb-dmac"; 730 reg = <0 0xe65b0000 0 0x100>; 731 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "ch0", "ch1"; 734 clocks = <&cpg CPG_MOD 331>; 735 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 736 resets = <&cpg 331>; 737 #dma-cells = <1>; 738 dma-channels = <2>; 739 }; 740 741 dmac0: dma-controller@e6700000 { 742 compatible = "renesas,dmac-r8a774c0", 743 "renesas,rcar-dmac"; 744 reg = <0 0xe6700000 0 0x10000>; 745 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "error", 763 "ch0", "ch1", "ch2", "ch3", 764 "ch4", "ch5", "ch6", "ch7", 765 "ch8", "ch9", "ch10", "ch11", 766 "ch12", "ch13", "ch14", "ch15"; 767 clocks = <&cpg CPG_MOD 219>; 768 clock-names = "fck"; 769 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 770 resets = <&cpg 219>; 771 #dma-cells = <1>; 772 dma-channels = <16>; 773 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 774 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 775 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 776 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 777 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 778 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 779 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 780 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 781 }; 782 783 dmac1: dma-controller@e7300000 { 784 compatible = "renesas,dmac-r8a774c0", 785 "renesas,rcar-dmac"; 786 reg = <0 0xe7300000 0 0x10000>; 787 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 804 interrupt-names = "error", 805 "ch0", "ch1", "ch2", "ch3", 806 "ch4", "ch5", "ch6", "ch7", 807 "ch8", "ch9", "ch10", "ch11", 808 "ch12", "ch13", "ch14", "ch15"; 809 clocks = <&cpg CPG_MOD 218>; 810 clock-names = "fck"; 811 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 812 resets = <&cpg 218>; 813 #dma-cells = <1>; 814 dma-channels = <16>; 815 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 816 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 817 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 818 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 819 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 820 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 821 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 822 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 823 }; 824 825 dmac2: dma-controller@e7310000 { 826 compatible = "renesas,dmac-r8a774c0", 827 "renesas,rcar-dmac"; 828 reg = <0 0xe7310000 0 0x10000>; 829 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "error", 847 "ch0", "ch1", "ch2", "ch3", 848 "ch4", "ch5", "ch6", "ch7", 849 "ch8", "ch9", "ch10", "ch11", 850 "ch12", "ch13", "ch14", "ch15"; 851 clocks = <&cpg CPG_MOD 217>; 852 clock-names = "fck"; 853 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 854 resets = <&cpg 217>; 855 #dma-cells = <1>; 856 dma-channels = <16>; 857 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 858 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 859 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 860 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 861 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 862 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 863 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 864 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 865 }; 866 867 ipmmu_ds0: iommu@e6740000 { 868 compatible = "renesas,ipmmu-r8a774c0"; 869 reg = <0 0xe6740000 0 0x1000>; 870 renesas,ipmmu-main = <&ipmmu_mm 0>; 871 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 872 #iommu-cells = <1>; 873 }; 874 875 ipmmu_ds1: iommu@e7740000 { 876 compatible = "renesas,ipmmu-r8a774c0"; 877 reg = <0 0xe7740000 0 0x1000>; 878 renesas,ipmmu-main = <&ipmmu_mm 1>; 879 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 880 #iommu-cells = <1>; 881 }; 882 883 ipmmu_hc: iommu@e6570000 { 884 compatible = "renesas,ipmmu-r8a774c0"; 885 reg = <0 0xe6570000 0 0x1000>; 886 renesas,ipmmu-main = <&ipmmu_mm 2>; 887 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 888 #iommu-cells = <1>; 889 }; 890 891 ipmmu_mm: iommu@e67b0000 { 892 compatible = "renesas,ipmmu-r8a774c0"; 893 reg = <0 0xe67b0000 0 0x1000>; 894 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 896 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 897 #iommu-cells = <1>; 898 }; 899 900 ipmmu_mp: iommu@ec670000 { 901 compatible = "renesas,ipmmu-r8a774c0"; 902 reg = <0 0xec670000 0 0x1000>; 903 renesas,ipmmu-main = <&ipmmu_mm 4>; 904 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 905 #iommu-cells = <1>; 906 }; 907 908 ipmmu_pv0: iommu@fd800000 { 909 compatible = "renesas,ipmmu-r8a774c0"; 910 reg = <0 0xfd800000 0 0x1000>; 911 renesas,ipmmu-main = <&ipmmu_mm 6>; 912 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 913 #iommu-cells = <1>; 914 }; 915 916 ipmmu_vc0: iommu@fe6b0000 { 917 compatible = "renesas,ipmmu-r8a774c0"; 918 reg = <0 0xfe6b0000 0 0x1000>; 919 renesas,ipmmu-main = <&ipmmu_mm 12>; 920 power-domains = <&sysc R8A774C0_PD_A3VC>; 921 #iommu-cells = <1>; 922 }; 923 924 ipmmu_vi0: iommu@febd0000 { 925 compatible = "renesas,ipmmu-r8a774c0"; 926 reg = <0 0xfebd0000 0 0x1000>; 927 renesas,ipmmu-main = <&ipmmu_mm 14>; 928 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 929 #iommu-cells = <1>; 930 }; 931 932 ipmmu_vp0: iommu@fe990000 { 933 compatible = "renesas,ipmmu-r8a774c0"; 934 reg = <0 0xfe990000 0 0x1000>; 935 renesas,ipmmu-main = <&ipmmu_mm 16>; 936 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 937 #iommu-cells = <1>; 938 }; 939 940 avb: ethernet@e6800000 { 941 compatible = "renesas,etheravb-r8a774c0", 942 "renesas,etheravb-rcar-gen3"; 943 reg = <0 0xe6800000 0 0x800>; 944 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 969 interrupt-names = "ch0", "ch1", "ch2", "ch3", 970 "ch4", "ch5", "ch6", "ch7", 971 "ch8", "ch9", "ch10", "ch11", 972 "ch12", "ch13", "ch14", "ch15", 973 "ch16", "ch17", "ch18", "ch19", 974 "ch20", "ch21", "ch22", "ch23", 975 "ch24"; 976 clocks = <&cpg CPG_MOD 812>; 977 clock-names = "fck"; 978 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 979 resets = <&cpg 812>; 980 phy-mode = "rgmii"; 981 rx-internal-delay-ps = <0>; 982 iommus = <&ipmmu_ds0 16>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 can0: can@e6c30000 { 989 compatible = "renesas,can-r8a774c0", 990 "renesas,rcar-gen3-can"; 991 reg = <0 0xe6c30000 0 0x1000>; 992 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&cpg CPG_MOD 916>, 994 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 995 <&can_clk>; 996 clock-names = "clkp1", "clkp2", "can_clk"; 997 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 998 assigned-clock-rates = <40000000>; 999 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1000 resets = <&cpg 916>; 1001 status = "disabled"; 1002 }; 1003 1004 can1: can@e6c38000 { 1005 compatible = "renesas,can-r8a774c0", 1006 "renesas,rcar-gen3-can"; 1007 reg = <0 0xe6c38000 0 0x1000>; 1008 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&cpg CPG_MOD 915>, 1010 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1011 <&can_clk>; 1012 clock-names = "clkp1", "clkp2", "can_clk"; 1013 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1014 assigned-clock-rates = <40000000>; 1015 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1016 resets = <&cpg 915>; 1017 status = "disabled"; 1018 }; 1019 1020 canfd: can@e66c0000 { 1021 compatible = "renesas,r8a774c0-canfd", 1022 "renesas,rcar-gen3-canfd"; 1023 reg = <0 0xe66c0000 0 0x8000>; 1024 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1026 interrupt-names = "ch_int", "g_int"; 1027 clocks = <&cpg CPG_MOD 914>, 1028 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1029 <&can_clk>; 1030 clock-names = "fck", "canfd", "can_clk"; 1031 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1032 assigned-clock-rates = <40000000>; 1033 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1034 resets = <&cpg 914>; 1035 status = "disabled"; 1036 1037 channel0 { 1038 status = "disabled"; 1039 }; 1040 1041 channel1 { 1042 status = "disabled"; 1043 }; 1044 }; 1045 1046 pwm0: pwm@e6e30000 { 1047 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1048 reg = <0 0xe6e30000 0 0x8>; 1049 clocks = <&cpg CPG_MOD 523>; 1050 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1051 resets = <&cpg 523>; 1052 #pwm-cells = <2>; 1053 status = "disabled"; 1054 }; 1055 1056 pwm1: pwm@e6e31000 { 1057 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1058 reg = <0 0xe6e31000 0 0x8>; 1059 clocks = <&cpg CPG_MOD 523>; 1060 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1061 resets = <&cpg 523>; 1062 #pwm-cells = <2>; 1063 status = "disabled"; 1064 }; 1065 1066 pwm2: pwm@e6e32000 { 1067 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1068 reg = <0 0xe6e32000 0 0x8>; 1069 clocks = <&cpg CPG_MOD 523>; 1070 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1071 resets = <&cpg 523>; 1072 #pwm-cells = <2>; 1073 status = "disabled"; 1074 }; 1075 1076 pwm3: pwm@e6e33000 { 1077 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1078 reg = <0 0xe6e33000 0 0x8>; 1079 clocks = <&cpg CPG_MOD 523>; 1080 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1081 resets = <&cpg 523>; 1082 #pwm-cells = <2>; 1083 status = "disabled"; 1084 }; 1085 1086 pwm4: pwm@e6e34000 { 1087 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1088 reg = <0 0xe6e34000 0 0x8>; 1089 clocks = <&cpg CPG_MOD 523>; 1090 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1091 resets = <&cpg 523>; 1092 #pwm-cells = <2>; 1093 status = "disabled"; 1094 }; 1095 1096 pwm5: pwm@e6e35000 { 1097 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1098 reg = <0 0xe6e35000 0 0x8>; 1099 clocks = <&cpg CPG_MOD 523>; 1100 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1101 resets = <&cpg 523>; 1102 #pwm-cells = <2>; 1103 status = "disabled"; 1104 }; 1105 1106 pwm6: pwm@e6e36000 { 1107 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1108 reg = <0 0xe6e36000 0 0x8>; 1109 clocks = <&cpg CPG_MOD 523>; 1110 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1111 resets = <&cpg 523>; 1112 #pwm-cells = <2>; 1113 status = "disabled"; 1114 }; 1115 1116 scif0: serial@e6e60000 { 1117 compatible = "renesas,scif-r8a774c0", 1118 "renesas,rcar-gen3-scif", "renesas,scif"; 1119 reg = <0 0xe6e60000 0 64>; 1120 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&cpg CPG_MOD 207>, 1122 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1123 <&scif_clk>; 1124 clock-names = "fck", "brg_int", "scif_clk"; 1125 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1126 <&dmac2 0x51>, <&dmac2 0x50>; 1127 dma-names = "tx", "rx", "tx", "rx"; 1128 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1129 resets = <&cpg 207>; 1130 status = "disabled"; 1131 }; 1132 1133 scif1: serial@e6e68000 { 1134 compatible = "renesas,scif-r8a774c0", 1135 "renesas,rcar-gen3-scif", "renesas,scif"; 1136 reg = <0 0xe6e68000 0 64>; 1137 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cpg CPG_MOD 206>, 1139 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1140 <&scif_clk>; 1141 clock-names = "fck", "brg_int", "scif_clk"; 1142 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1143 <&dmac2 0x53>, <&dmac2 0x52>; 1144 dma-names = "tx", "rx", "tx", "rx"; 1145 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1146 resets = <&cpg 206>; 1147 status = "disabled"; 1148 }; 1149 1150 scif2: serial@e6e88000 { 1151 compatible = "renesas,scif-r8a774c0", 1152 "renesas,rcar-gen3-scif", "renesas,scif"; 1153 reg = <0 0xe6e88000 0 64>; 1154 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&cpg CPG_MOD 310>, 1156 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1157 <&scif_clk>; 1158 clock-names = "fck", "brg_int", "scif_clk"; 1159 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1160 <&dmac2 0x13>, <&dmac2 0x12>; 1161 dma-names = "tx", "rx", "tx", "rx"; 1162 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1163 resets = <&cpg 310>; 1164 status = "disabled"; 1165 }; 1166 1167 scif3: serial@e6c50000 { 1168 compatible = "renesas,scif-r8a774c0", 1169 "renesas,rcar-gen3-scif", "renesas,scif"; 1170 reg = <0 0xe6c50000 0 64>; 1171 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&cpg CPG_MOD 204>, 1173 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1174 <&scif_clk>; 1175 clock-names = "fck", "brg_int", "scif_clk"; 1176 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1177 dma-names = "tx", "rx"; 1178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1179 resets = <&cpg 204>; 1180 status = "disabled"; 1181 }; 1182 1183 scif4: serial@e6c40000 { 1184 compatible = "renesas,scif-r8a774c0", 1185 "renesas,rcar-gen3-scif", "renesas,scif"; 1186 reg = <0 0xe6c40000 0 64>; 1187 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&cpg CPG_MOD 203>, 1189 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1190 <&scif_clk>; 1191 clock-names = "fck", "brg_int", "scif_clk"; 1192 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1193 dma-names = "tx", "rx"; 1194 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1195 resets = <&cpg 203>; 1196 status = "disabled"; 1197 }; 1198 1199 scif5: serial@e6f30000 { 1200 compatible = "renesas,scif-r8a774c0", 1201 "renesas,rcar-gen3-scif", "renesas,scif"; 1202 reg = <0 0xe6f30000 0 64>; 1203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&cpg CPG_MOD 202>, 1205 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1206 <&scif_clk>; 1207 clock-names = "fck", "brg_int", "scif_clk"; 1208 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1209 dma-names = "tx", "rx"; 1210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1211 resets = <&cpg 202>; 1212 status = "disabled"; 1213 }; 1214 1215 msiof0: spi@e6e90000 { 1216 compatible = "renesas,msiof-r8a774c0", 1217 "renesas,rcar-gen3-msiof"; 1218 reg = <0 0xe6e90000 0 0x0064>; 1219 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&cpg CPG_MOD 211>; 1221 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1222 <&dmac2 0x41>, <&dmac2 0x40>; 1223 dma-names = "tx", "rx", "tx", "rx"; 1224 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1225 resets = <&cpg 211>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 msiof1: spi@e6ea0000 { 1232 compatible = "renesas,msiof-r8a774c0", 1233 "renesas,rcar-gen3-msiof"; 1234 reg = <0 0xe6ea0000 0 0x0064>; 1235 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&cpg CPG_MOD 210>; 1237 dmas = <&dmac0 0x43>, <&dmac0 0x42>; 1238 dma-names = "tx", "rx"; 1239 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1240 resets = <&cpg 210>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 msiof2: spi@e6c00000 { 1247 compatible = "renesas,msiof-r8a774c0", 1248 "renesas,rcar-gen3-msiof"; 1249 reg = <0 0xe6c00000 0 0x0064>; 1250 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&cpg CPG_MOD 209>; 1252 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1253 dma-names = "tx", "rx"; 1254 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1255 resets = <&cpg 209>; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 msiof3: spi@e6c10000 { 1262 compatible = "renesas,msiof-r8a774c0", 1263 "renesas,rcar-gen3-msiof"; 1264 reg = <0 0xe6c10000 0 0x0064>; 1265 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cpg CPG_MOD 208>; 1267 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1268 dma-names = "tx", "rx"; 1269 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1270 resets = <&cpg 208>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 status = "disabled"; 1274 }; 1275 1276 vin4: video@e6ef4000 { 1277 compatible = "renesas,vin-r8a774c0"; 1278 reg = <0 0xe6ef4000 0 0x1000>; 1279 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1280 clocks = <&cpg CPG_MOD 807>; 1281 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1282 resets = <&cpg 807>; 1283 renesas,id = <4>; 1284 status = "disabled"; 1285 1286 ports { 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 1290 port@1 { 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 1294 reg = <1>; 1295 1296 vin4csi40: endpoint@2 { 1297 reg = <2>; 1298 remote-endpoint = <&csi40vin4>; 1299 }; 1300 }; 1301 }; 1302 }; 1303 1304 vin5: video@e6ef5000 { 1305 compatible = "renesas,vin-r8a774c0"; 1306 reg = <0 0xe6ef5000 0 0x1000>; 1307 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&cpg CPG_MOD 806>; 1309 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1310 resets = <&cpg 806>; 1311 renesas,id = <5>; 1312 status = "disabled"; 1313 1314 ports { 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 1318 port@1 { 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 1322 reg = <1>; 1323 1324 vin5csi40: endpoint@2 { 1325 reg = <2>; 1326 remote-endpoint = <&csi40vin5>; 1327 }; 1328 }; 1329 }; 1330 }; 1331 1332 rcar_sound: sound@ec500000 { 1333 /* 1334 * #sound-dai-cells is required if simple-card 1335 * 1336 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1337 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1338 */ 1339 /* 1340 * #clock-cells is required for audio_clkout0/1/2/3 1341 * 1342 * clkout : #clock-cells = <0>; <&rcar_sound>; 1343 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1344 */ 1345 compatible = "renesas,rcar_sound-r8a774c0", 1346 "renesas,rcar_sound-gen3"; 1347 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1348 <0 0xec5a0000 0 0x100>, /* ADG */ 1349 <0 0xec540000 0 0x1000>, /* SSIU */ 1350 <0 0xec541000 0 0x280>, /* SSI */ 1351 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1352 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1353 1354 clocks = <&cpg CPG_MOD 1005>, 1355 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1356 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1357 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1358 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1359 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1360 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1361 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1362 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1363 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1364 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1365 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1366 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1367 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1368 <&audio_clk_a>, <&audio_clk_b>, 1369 <&audio_clk_c>, 1370 <&cpg CPG_MOD 922>; 1371 clock-names = "ssi-all", 1372 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1373 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1374 "ssi.1", "ssi.0", 1375 "src.9", "src.8", "src.7", "src.6", 1376 "src.5", "src.4", "src.3", "src.2", 1377 "src.1", "src.0", 1378 "mix.1", "mix.0", 1379 "ctu.1", "ctu.0", 1380 "dvc.0", "dvc.1", 1381 "clk_a", "clk_b", "clk_c", "clk_i"; 1382 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1383 resets = <&cpg 1005>, 1384 <&cpg 1006>, <&cpg 1007>, 1385 <&cpg 1008>, <&cpg 1009>, 1386 <&cpg 1010>, <&cpg 1011>, 1387 <&cpg 1012>, <&cpg 1013>, 1388 <&cpg 1014>, <&cpg 1015>; 1389 reset-names = "ssi-all", 1390 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1391 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1392 "ssi.1", "ssi.0"; 1393 status = "disabled"; 1394 1395 rcar_sound,ctu { 1396 ctu00: ctu-0 { }; 1397 ctu01: ctu-1 { }; 1398 ctu02: ctu-2 { }; 1399 ctu03: ctu-3 { }; 1400 ctu10: ctu-4 { }; 1401 ctu11: ctu-5 { }; 1402 ctu12: ctu-6 { }; 1403 ctu13: ctu-7 { }; 1404 }; 1405 1406 rcar_sound,dvc { 1407 dvc0: dvc-0 { 1408 dmas = <&audma0 0xbc>; 1409 dma-names = "tx"; 1410 }; 1411 dvc1: dvc-1 { 1412 dmas = <&audma0 0xbe>; 1413 dma-names = "tx"; 1414 }; 1415 }; 1416 1417 rcar_sound,mix { 1418 mix0: mix-0 { }; 1419 mix1: mix-1 { }; 1420 }; 1421 1422 rcar_sound,src { 1423 src0: src-0 { 1424 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1425 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1426 dma-names = "rx", "tx"; 1427 }; 1428 src1: src-1 { 1429 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1430 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1431 dma-names = "rx", "tx"; 1432 }; 1433 src2: src-2 { 1434 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1435 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1436 dma-names = "rx", "tx"; 1437 }; 1438 src3: src-3 { 1439 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1440 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1441 dma-names = "rx", "tx"; 1442 }; 1443 src4: src-4 { 1444 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1445 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1446 dma-names = "rx", "tx"; 1447 }; 1448 src5: src-5 { 1449 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1450 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1451 dma-names = "rx", "tx"; 1452 }; 1453 src6: src-6 { 1454 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1455 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1456 dma-names = "rx", "tx"; 1457 }; 1458 src7: src-7 { 1459 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1460 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1461 dma-names = "rx", "tx"; 1462 }; 1463 src8: src-8 { 1464 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1465 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1466 dma-names = "rx", "tx"; 1467 }; 1468 src9: src-9 { 1469 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1470 dmas = <&audma0 0x97>, <&audma0 0xba>; 1471 dma-names = "rx", "tx"; 1472 }; 1473 }; 1474 1475 rcar_sound,ssi { 1476 ssi0: ssi-0 { 1477 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1478 dmas = <&audma0 0x01>, <&audma0 0x02>, 1479 <&audma0 0x15>, <&audma0 0x16>; 1480 dma-names = "rx", "tx", "rxu", "txu"; 1481 }; 1482 ssi1: ssi-1 { 1483 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1484 dmas = <&audma0 0x03>, <&audma0 0x04>, 1485 <&audma0 0x49>, <&audma0 0x4a>; 1486 dma-names = "rx", "tx", "rxu", "txu"; 1487 }; 1488 ssi2: ssi-2 { 1489 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1490 dmas = <&audma0 0x05>, <&audma0 0x06>, 1491 <&audma0 0x63>, <&audma0 0x64>; 1492 dma-names = "rx", "tx", "rxu", "txu"; 1493 }; 1494 ssi3: ssi-3 { 1495 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1496 dmas = <&audma0 0x07>, <&audma0 0x08>, 1497 <&audma0 0x6f>, <&audma0 0x70>; 1498 dma-names = "rx", "tx", "rxu", "txu"; 1499 }; 1500 ssi4: ssi-4 { 1501 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1502 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1503 <&audma0 0x71>, <&audma0 0x72>; 1504 dma-names = "rx", "tx", "rxu", "txu"; 1505 }; 1506 ssi5: ssi-5 { 1507 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1508 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1509 <&audma0 0x73>, <&audma0 0x74>; 1510 dma-names = "rx", "tx", "rxu", "txu"; 1511 }; 1512 ssi6: ssi-6 { 1513 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1514 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1515 <&audma0 0x75>, <&audma0 0x76>; 1516 dma-names = "rx", "tx", "rxu", "txu"; 1517 }; 1518 ssi7: ssi-7 { 1519 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1520 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1521 <&audma0 0x79>, <&audma0 0x7a>; 1522 dma-names = "rx", "tx", "rxu", "txu"; 1523 }; 1524 ssi8: ssi-8 { 1525 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1526 dmas = <&audma0 0x11>, <&audma0 0x12>, 1527 <&audma0 0x7b>, <&audma0 0x7c>; 1528 dma-names = "rx", "tx", "rxu", "txu"; 1529 }; 1530 ssi9: ssi-9 { 1531 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1532 dmas = <&audma0 0x13>, <&audma0 0x14>, 1533 <&audma0 0x7d>, <&audma0 0x7e>; 1534 dma-names = "rx", "tx", "rxu", "txu"; 1535 }; 1536 }; 1537 }; 1538 1539 audma0: dma-controller@ec700000 { 1540 compatible = "renesas,dmac-r8a774c0", 1541 "renesas,rcar-dmac"; 1542 reg = <0 0xec700000 0 0x10000>; 1543 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "error", 1561 "ch0", "ch1", "ch2", "ch3", 1562 "ch4", "ch5", "ch6", "ch7", 1563 "ch8", "ch9", "ch10", "ch11", 1564 "ch12", "ch13", "ch14", "ch15"; 1565 clocks = <&cpg CPG_MOD 502>; 1566 clock-names = "fck"; 1567 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1568 resets = <&cpg 502>; 1569 #dma-cells = <1>; 1570 dma-channels = <16>; 1571 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1572 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1573 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1574 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1575 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1576 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1577 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1578 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1579 }; 1580 1581 xhci0: usb@ee000000 { 1582 compatible = "renesas,xhci-r8a774c0", 1583 "renesas,rcar-gen3-xhci"; 1584 reg = <0 0xee000000 0 0xc00>; 1585 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1586 clocks = <&cpg CPG_MOD 328>; 1587 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1588 resets = <&cpg 328>; 1589 status = "disabled"; 1590 }; 1591 1592 usb3_peri0: usb@ee020000 { 1593 compatible = "renesas,r8a774c0-usb3-peri", 1594 "renesas,rcar-gen3-usb3-peri"; 1595 reg = <0 0xee020000 0 0x400>; 1596 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1597 clocks = <&cpg CPG_MOD 328>; 1598 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1599 resets = <&cpg 328>; 1600 status = "disabled"; 1601 }; 1602 1603 ohci0: usb@ee080000 { 1604 compatible = "generic-ohci"; 1605 reg = <0 0xee080000 0 0x100>; 1606 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1607 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1608 phys = <&usb2_phy0 1>; 1609 phy-names = "usb"; 1610 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1611 resets = <&cpg 703>, <&cpg 704>; 1612 status = "disabled"; 1613 }; 1614 1615 ehci0: usb@ee080100 { 1616 compatible = "generic-ehci"; 1617 reg = <0 0xee080100 0 0x100>; 1618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1620 phys = <&usb2_phy0 2>; 1621 phy-names = "usb"; 1622 companion = <&ohci0>; 1623 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1624 resets = <&cpg 703>, <&cpg 704>; 1625 status = "disabled"; 1626 }; 1627 1628 usb2_phy0: usb-phy@ee080200 { 1629 compatible = "renesas,usb2-phy-r8a774c0", 1630 "renesas,rcar-gen3-usb2-phy"; 1631 reg = <0 0xee080200 0 0x700>; 1632 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1634 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1635 resets = <&cpg 703>, <&cpg 704>; 1636 #phy-cells = <1>; 1637 status = "disabled"; 1638 }; 1639 1640 sdhi0: mmc@ee100000 { 1641 compatible = "renesas,sdhi-r8a774c0", 1642 "renesas,rcar-gen3-sdhi"; 1643 reg = <0 0xee100000 0 0x2000>; 1644 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1645 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>; 1646 clock-names = "core", "clkh"; 1647 max-frequency = <200000000>; 1648 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1649 resets = <&cpg 314>; 1650 iommus = <&ipmmu_ds1 32>; 1651 status = "disabled"; 1652 }; 1653 1654 sdhi1: mmc@ee120000 { 1655 compatible = "renesas,sdhi-r8a774c0", 1656 "renesas,rcar-gen3-sdhi"; 1657 reg = <0 0xee120000 0 0x2000>; 1658 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>; 1660 clock-names = "core", "clkh"; 1661 max-frequency = <200000000>; 1662 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1663 resets = <&cpg 313>; 1664 iommus = <&ipmmu_ds1 33>; 1665 status = "disabled"; 1666 }; 1667 1668 sdhi3: mmc@ee160000 { 1669 compatible = "renesas,sdhi-r8a774c0", 1670 "renesas,rcar-gen3-sdhi"; 1671 reg = <0 0xee160000 0 0x2000>; 1672 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1673 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>; 1674 clock-names = "core", "clkh"; 1675 max-frequency = <200000000>; 1676 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1677 resets = <&cpg 311>; 1678 iommus = <&ipmmu_ds1 35>; 1679 status = "disabled"; 1680 }; 1681 1682 rpc: spi@ee200000 { 1683 compatible = "renesas,r8a774c0-rpc-if", 1684 "renesas,rcar-gen3-rpc-if"; 1685 reg = <0 0xee200000 0 0x200>, 1686 <0 0x08000000 0 0x4000000>, 1687 <0 0xee208000 0 0x100>; 1688 reg-names = "regs", "dirmap", "wbuf"; 1689 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1690 clocks = <&cpg CPG_MOD 917>; 1691 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1692 resets = <&cpg 917>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 status = "disabled"; 1696 }; 1697 1698 gic: interrupt-controller@f1010000 { 1699 compatible = "arm,gic-400"; 1700 #interrupt-cells = <3>; 1701 #address-cells = <0>; 1702 interrupt-controller; 1703 reg = <0x0 0xf1010000 0 0x1000>, 1704 <0x0 0xf1020000 0 0x20000>, 1705 <0x0 0xf1040000 0 0x20000>, 1706 <0x0 0xf1060000 0 0x20000>; 1707 interrupts = <GIC_PPI 9 1708 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1709 clocks = <&cpg CPG_MOD 408>; 1710 clock-names = "clk"; 1711 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1712 resets = <&cpg 408>; 1713 }; 1714 1715 pciec0: pcie@fe000000 { 1716 compatible = "renesas,pcie-r8a774c0", 1717 "renesas,pcie-rcar-gen3"; 1718 reg = <0 0xfe000000 0 0x80000>; 1719 #address-cells = <3>; 1720 #size-cells = <2>; 1721 bus-range = <0x00 0xff>; 1722 device_type = "pci"; 1723 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1724 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1725 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1726 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1727 /* Map all possible DDR/IOMMU as inbound ranges */ 1728 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 1729 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1732 #interrupt-cells = <1>; 1733 interrupt-map-mask = <0 0 0 0>; 1734 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1736 clock-names = "pcie", "pcie_bus"; 1737 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1738 resets = <&cpg 319>; 1739 iommu-map = <0 &ipmmu_hc 0 1>; 1740 iommu-map-mask = <0>; 1741 status = "disabled"; 1742 }; 1743 1744 pciec0_ep: pcie-ep@fe000000 { 1745 compatible = "renesas,r8a774c0-pcie-ep", 1746 "renesas,rcar-gen3-pcie-ep"; 1747 reg = <0x0 0xfe000000 0 0x80000>, 1748 <0x0 0xfe100000 0 0x100000>, 1749 <0x0 0xfe200000 0 0x200000>, 1750 <0x0 0x30000000 0 0x8000000>, 1751 <0x0 0x38000000 0 0x8000000>; 1752 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 1753 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1756 clocks = <&cpg CPG_MOD 319>; 1757 clock-names = "pcie"; 1758 resets = <&cpg 319>; 1759 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1760 status = "disabled"; 1761 }; 1762 1763 vspb0: vsp@fe960000 { 1764 compatible = "renesas,vsp2"; 1765 reg = <0 0xfe960000 0 0x8000>; 1766 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1767 clocks = <&cpg CPG_MOD 626>; 1768 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1769 resets = <&cpg 626>; 1770 renesas,fcp = <&fcpvb0>; 1771 }; 1772 1773 vspd0: vsp@fea20000 { 1774 compatible = "renesas,vsp2"; 1775 reg = <0 0xfea20000 0 0x7000>; 1776 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1777 clocks = <&cpg CPG_MOD 623>; 1778 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1779 resets = <&cpg 623>; 1780 renesas,fcp = <&fcpvd0>; 1781 }; 1782 1783 vspd1: vsp@fea28000 { 1784 compatible = "renesas,vsp2"; 1785 reg = <0 0xfea28000 0 0x7000>; 1786 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&cpg CPG_MOD 622>; 1788 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1789 resets = <&cpg 622>; 1790 renesas,fcp = <&fcpvd1>; 1791 }; 1792 1793 vspi0: vsp@fe9a0000 { 1794 compatible = "renesas,vsp2"; 1795 reg = <0 0xfe9a0000 0 0x8000>; 1796 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&cpg CPG_MOD 631>; 1798 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1799 resets = <&cpg 631>; 1800 renesas,fcp = <&fcpvi0>; 1801 }; 1802 1803 fcpvb0: fcp@fe96f000 { 1804 compatible = "renesas,fcpv"; 1805 reg = <0 0xfe96f000 0 0x200>; 1806 clocks = <&cpg CPG_MOD 607>; 1807 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1808 resets = <&cpg 607>; 1809 iommus = <&ipmmu_vp0 5>; 1810 }; 1811 1812 fcpvd0: fcp@fea27000 { 1813 compatible = "renesas,fcpv"; 1814 reg = <0 0xfea27000 0 0x200>; 1815 clocks = <&cpg CPG_MOD 603>; 1816 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1817 resets = <&cpg 603>; 1818 iommus = <&ipmmu_vi0 8>; 1819 }; 1820 1821 fcpvd1: fcp@fea2f000 { 1822 compatible = "renesas,fcpv"; 1823 reg = <0 0xfea2f000 0 0x200>; 1824 clocks = <&cpg CPG_MOD 602>; 1825 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1826 resets = <&cpg 602>; 1827 iommus = <&ipmmu_vi0 9>; 1828 }; 1829 1830 fcpvi0: fcp@fe9af000 { 1831 compatible = "renesas,fcpv"; 1832 reg = <0 0xfe9af000 0 0x200>; 1833 clocks = <&cpg CPG_MOD 611>; 1834 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1835 resets = <&cpg 611>; 1836 iommus = <&ipmmu_vp0 8>; 1837 }; 1838 1839 csi40: csi2@feaa0000 { 1840 compatible = "renesas,r8a774c0-csi2"; 1841 reg = <0 0xfeaa0000 0 0x10000>; 1842 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1843 clocks = <&cpg CPG_MOD 716>; 1844 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1845 resets = <&cpg 716>; 1846 status = "disabled"; 1847 1848 ports { 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 1852 port@0 { 1853 reg = <0>; 1854 }; 1855 1856 port@1 { 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 1860 reg = <1>; 1861 1862 csi40vin4: endpoint@0 { 1863 reg = <0>; 1864 remote-endpoint = <&vin4csi40>; 1865 }; 1866 csi40vin5: endpoint@1 { 1867 reg = <1>; 1868 remote-endpoint = <&vin5csi40>; 1869 }; 1870 }; 1871 }; 1872 }; 1873 1874 du: display@feb00000 { 1875 compatible = "renesas,du-r8a774c0"; 1876 reg = <0 0xfeb00000 0 0x40000>; 1877 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1879 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1880 clock-names = "du.0", "du.1"; 1881 resets = <&cpg 724>; 1882 reset-names = "du.0"; 1883 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1884 1885 status = "disabled"; 1886 1887 ports { 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 1891 port@0 { 1892 reg = <0>; 1893 }; 1894 1895 port@1 { 1896 reg = <1>; 1897 du_out_lvds0: endpoint { 1898 remote-endpoint = <&lvds0_in>; 1899 }; 1900 }; 1901 1902 port@2 { 1903 reg = <2>; 1904 du_out_lvds1: endpoint { 1905 remote-endpoint = <&lvds1_in>; 1906 }; 1907 }; 1908 }; 1909 }; 1910 1911 lvds0: lvds-encoder@feb90000 { 1912 compatible = "renesas,r8a774c0-lvds"; 1913 reg = <0 0xfeb90000 0 0x20>; 1914 clocks = <&cpg CPG_MOD 727>; 1915 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1916 resets = <&cpg 727>; 1917 status = "disabled"; 1918 1919 renesas,companion = <&lvds1>; 1920 1921 ports { 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 1925 port@0 { 1926 reg = <0>; 1927 lvds0_in: endpoint { 1928 remote-endpoint = <&du_out_lvds0>; 1929 }; 1930 }; 1931 1932 port@1 { 1933 reg = <1>; 1934 }; 1935 }; 1936 }; 1937 1938 lvds1: lvds-encoder@feb90100 { 1939 compatible = "renesas,r8a774c0-lvds"; 1940 reg = <0 0xfeb90100 0 0x20>; 1941 clocks = <&cpg CPG_MOD 727>; 1942 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1943 resets = <&cpg 726>; 1944 status = "disabled"; 1945 1946 ports { 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 1950 port@0 { 1951 reg = <0>; 1952 lvds1_in: endpoint { 1953 remote-endpoint = <&du_out_lvds1>; 1954 }; 1955 }; 1956 1957 port@1 { 1958 reg = <1>; 1959 }; 1960 }; 1961 }; 1962 1963 prr: chipid@fff00044 { 1964 compatible = "renesas,prr"; 1965 reg = <0 0xfff00044 0 4>; 1966 bootph-all; 1967 }; 1968 }; 1969 1970 thermal-zones { 1971 cpu-thermal { 1972 polling-delay-passive = <250>; 1973 polling-delay = <0>; 1974 thermal-sensors = <&thermal>; 1975 sustainable-power = <717>; 1976 1977 cooling-maps { 1978 map0 { 1979 trip = <&target>; 1980 cooling-device = <&a53_0 0 2>; 1981 contribution = <1024>; 1982 }; 1983 }; 1984 1985 trips { 1986 sensor1_crit: sensor1-crit { 1987 temperature = <120000>; 1988 hysteresis = <2000>; 1989 type = "critical"; 1990 }; 1991 1992 target: trip-point1 { 1993 temperature = <100000>; 1994 hysteresis = <2000>; 1995 type = "passive"; 1996 }; 1997 }; 1998 }; 1999 }; 2000 2001 timer { 2002 compatible = "arm,armv8-timer"; 2003 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2004 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2005 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2006 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 2007 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 2008 }; 2009 2010 /* External USB clocks - can be overridden by the board */ 2011 usb3s0_clk: usb3s0 { 2012 compatible = "fixed-clock"; 2013 #clock-cells = <0>; 2014 clock-frequency = <0>; 2015 }; 2016 2017 usb_extal_clk: usb_extal { 2018 compatible = "fixed-clock"; 2019 #clock-cells = <0>; 2020 clock-frequency = <0>; 2021 }; 2022}; 2023