1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Common Board Device Tree for 4 * Microsoft Mobile MSM8994 Octagon Platforms 5 * 6 * Copyright (c) 2020, Konrad Dybcio 7 * Copyright (c) 2020, Gustave Monce <gustave.monce@outlook.com> 8 */ 9 10#include "pm8994.dtsi" 11#include "pmi8994.dtsi" 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/gpio-keys.h> 14#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 15 16/* 17 * Delete all generic (msm8994.dtsi) reserved 18 * memory mappings which are different in this device. 19 */ 20/delete-node/ &adsp_mem; 21/delete-node/ &audio_mem; 22/delete-node/ &cont_splash_mem; 23/delete-node/ &mba_mem; 24/delete-node/ &mpss_mem; 25/delete-node/ &peripheral_region; 26/delete-node/ &res_hyp_mem; 27/delete-node/ &rmtfs_mem; 28/delete-node/ &smem_mem; 29 30/ { 31 /* 32 * Most Lumia 950/XL users use GRUB to load their kernels, 33 * hence there is no need for msm-id and friends. 34 */ 35 36 /* 37 * This enables graphical output via bootloader-enabled display. 38 * acpi=no is required due to WP platforms having ACPI support, but 39 * only for Windows-based OSes. 40 */ 41 chosen { 42 bootargs = "earlycon=efifb console=efifb acpi=no"; 43 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 }; 48 49 clocks { 50 divclk4: divclk4 { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 54 clock-frequency = <32768>; 55 clock-output-names = "divclk4"; 56 57 pinctrl-names = "default"; 58 pinctrl-0 = <&divclk4_pin_a>; 59 }; 60 }; 61 62 gpio-keys { 63 compatible = "gpio-keys"; 64 autorepeat; 65 66 volup-key { 67 label = "Volume Up"; 68 gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; 69 linux,input-type = <1>; 70 linux,code = <KEY_VOLUMEUP>; 71 wakeup-source; 72 debounce-interval = <15>; 73 }; 74 75 camsnap-key { 76 label = "Camera Snapshot"; 77 gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; 78 linux,input-type = <1>; 79 linux,code = <KEY_CAMERA>; 80 wakeup-source; 81 debounce-interval = <15>; 82 }; 83 84 camfocus-key { 85 label = "Camera Focus"; 86 gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; 87 linux,input-type = <1>; 88 linux,code = <KEY_VOLUMEUP>; 89 wakeup-source; 90 debounce-interval = <15>; 91 }; 92 }; 93 94 gpio-hall-sensor { 95 compatible = "gpio-keys"; 96 97 pinctrl-names = "default"; 98 pinctrl-0 = <&hall_front_default &hall_back_default>; 99 100 label = "GPIO Hall Effect Sensor"; 101 102 event-hall-front-sensor { 103 label = "Hall Effect Front Sensor"; 104 gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; 105 linux,input-type = <EV_SW>; 106 linux,code = <SW_LID>; 107 linux,can-disable; 108 }; 109 110 event-hall-back-sensor { 111 label = "Hall Effect Back Sensor"; 112 gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; 113 linux,input-type = <EV_SW>; 114 linux,code = <SW_MACHINE_COVER>; 115 linux,can-disable; 116 }; 117 }; 118 119 reserved-memory { 120 /* 121 * This device being a WP platform has a very different 122 * memory layout than other Android based devices. 123 * This memory layout is directly copied from the original 124 * device UEFI firmware, and adapted based on observations 125 * using JTAG for the Qualcomm Peripheral Image regions. 126 */ 127 128 uefi_mem: memory@200000 { 129 reg = <0 0x00200000 0 0x100000>; 130 no-map; 131 }; 132 133 mppark_mem: memory@300000 { 134 reg = <0 0x00300000 0 0x80000>; 135 no-map; 136 }; 137 138 fbpt_mem: memory@380000 { 139 reg = <0 0x00380000 0 0x1000>; 140 no-map; 141 }; 142 143 dbg2_mem: memory@381000 { 144 reg = <0 0x00381000 0 0x4000>; 145 no-map; 146 }; 147 148 capsule_mem: memory@385000 { 149 reg = <0 0x00385000 0 0x1000>; 150 no-map; 151 }; 152 153 tpmctrl_mem: memory@386000 { 154 reg = <0 0x00386000 0 0x3000>; 155 no-map; 156 }; 157 158 uefiinfo_mem: memory@389000 { 159 reg = <0 0x00389000 0 0x1000>; 160 no-map; 161 }; 162 163 reset_mem: memory@389000 { 164 reg = <0 0x00389000 0 0x1000>; 165 no-map; 166 }; 167 168 resuncached_mem: memory@38e000 { 169 reg = <0 0x0038e000 0 0x72000>; 170 no-map; 171 }; 172 173 disp_mem: memory@400000 { 174 reg = <0 0x00400000 0 0x800000>; 175 no-map; 176 }; 177 178 uefistack_mem: memory@c00000 { 179 reg = <0 0x00c00000 0 0x40000>; 180 no-map; 181 }; 182 183 cpuvect_mem: memory@c40000 { 184 reg = <0 0x00c40000 0 0x10000>; 185 no-map; 186 }; 187 188 rescached_mem: memory@400000 { 189 reg = <0 0x00c50000 0 0xb0000>; 190 no-map; 191 }; 192 193 tzapps_mem: memory@6500000 { 194 reg = <0 0x06500000 0 0x500000>; 195 no-map; 196 }; 197 198 smem_mem: memory@6a00000 { 199 reg = <0 0x06a00000 0 0x200000>; 200 no-map; 201 }; 202 203 hyp_mem: memory@6c00000 { 204 reg = <0 0x06c00000 0 0x100000>; 205 no-map; 206 }; 207 208 tz_mem: memory@6d00000 { 209 reg = <0 0x06d00000 0 0x160000>; 210 no-map; 211 }; 212 213 rfsa_adsp_mem: memory@6e60000 { 214 reg = <0 0x06e60000 0 0x10000>; 215 no-map; 216 }; 217 218 rfsa_mpss_mem: memory@6e70000 { 219 compatible = "qcom,rmtfs-mem"; 220 reg = <0 0x06e70000 0 0x10000>; 221 no-map; 222 223 qcom,client-id = <1>; 224 }; 225 226 /* 227 * Value obtained from the device original ACPI DSDT table 228 * MPSS_EFS / SBL 229 */ 230 mba_mem: memory@6e80000 { 231 reg = <0 0x06e80000 0 0x180000>; 232 no-map; 233 }; 234 235 /* 236 * Peripheral Image loader region begin! 237 * The region reserved for pil is 0x7000000-0xef00000 238 */ 239 240 mpss_mem: memory@7000000 { 241 reg = <0 0x07000000 0 0x5a00000>; 242 no-map; 243 }; 244 245 adsp_mem: memory@ca00000 { 246 reg = <0 0x0ca00000 0 0x1800000>; 247 no-map; 248 }; 249 250 venus_mem: memory@e200000 { 251 reg = <0 0x0e200000 0 0x500000>; 252 no-map; 253 }; 254 255 pil_metadata_mem: memory@e700000 { 256 reg = <0 0x0e700000 0 0x4000>; 257 no-map; 258 }; 259 260 memory@e704000 { 261 reg = <0 0x0e704000 0 0x7fc000>; 262 no-map; 263 }; 264 /* Peripheral Image loader region end */ 265 266 cnss_mem: memory@ef00000 { 267 reg = <0 0x0ef00000 0 0x300000>; 268 no-map; 269 }; 270 }; 271}; 272 273&blsp1_i2c1 { 274 status = "okay"; 275 276 rmi4-i2c-dev@4b { 277 compatible = "syna,rmi4-i2c"; 278 reg = <0x4b>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 282 interrupt-parent = <&tlmm>; 283 interrupts = <77 IRQ_TYPE_EDGE_FALLING>; 284 285 rmi4-f01@1 { 286 reg = <0x01>; 287 syna,nosleep-mode = <1>; 288 }; 289 290 rmi4-f12@12 { 291 reg = <0x12>; 292 syna,sensor-type = <1>; 293 syna,clip-x-low = <0>; 294 syna,clip-x-high = <1440>; 295 syna,clip-y-low = <0>; 296 syna,clip-y-high = <2560>; 297 }; 298 }; 299}; 300 301&blsp1_i2c2 { 302 status = "okay"; 303 304 /* 305 * This device uses the Texas Instruments TAS2553, however the TAS2552 driver 306 * seems to work here. In the future a proper driver might need to 307 * be written for this device. 308 */ 309 tas2553: tas2553@40 { 310 compatible = "ti,tas2552"; 311 reg = <0x40>; 312 313 vbat-supply = <&vph_pwr>; 314 iovdd-supply = <&vreg_s4a_1p8>; 315 avdd-supply = <&vreg_s4a_1p8>; 316 317 enable-gpio = <&pm8994_gpios 12 GPIO_ACTIVE_HIGH>; 318 }; 319}; 320 321&blsp1_i2c5 { 322 status = "okay"; 323 324 ak09912: magnetometer@c { 325 compatible = "asahi-kasei,ak09912"; 326 reg = <0xc>; 327 328 interrupt-parent = <&tlmm>; 329 interrupts = <26 IRQ_TYPE_EDGE_RISING>; 330 331 vdd-supply = <&vreg_l18a_2p85>; 332 vid-supply = <&vreg_lvs2a_1p8>; 333 }; 334 335 zpa2326: barometer@5c { 336 compatible = "murata,zpa2326"; 337 reg = <0x5c>; 338 339 interrupt-parent = <&tlmm>; 340 interrupts = <74 IRQ_TYPE_EDGE_RISING>; 341 342 vdd-supply = <&vreg_lvs2a_1p8>; 343 }; 344 345 mpu6050: accelerometer@68 { 346 compatible = "invensense,mpu6500"; 347 reg = <0x68>; 348 349 interrupt-parent = <&tlmm>; 350 interrupts = <64 IRQ_TYPE_EDGE_RISING>; 351 352 vdd-supply = <&vreg_lvs2a_1p8>; 353 vddio-supply = <&vreg_lvs2a_1p8>; 354 }; 355}; 356 357&blsp1_i2c6 { 358 status = "okay"; 359 360 pn547: pn547@28 { 361 compatible = "nxp,pn544-i2c"; 362 363 reg = <0x28>; 364 365 interrupt-parent = <&tlmm>; 366 interrupts = <29 IRQ_TYPE_EDGE_RISING>; 367 368 enable-gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>; 369 firmware-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; 370 }; 371}; 372 373&blsp1_uart2 { 374 status = "okay"; 375}; 376 377&blsp2_i2c1 { 378 status = "okay"; 379 380 sideinteraction: touch@2c { 381 compatible = "ad,ad7147_captouch"; 382 reg = <0x2c>; 383 384 pinctrl-names = "default", "sleep"; 385 pinctrl-0 = <&grip_default>; 386 pinctrl-1 = <&grip_sleep>; 387 388 interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>; 389 390 vcc-supply = <&vreg_l18a_2p85>; 391 }; 392 393 /* 394 * The QPDS-T900/QPDS-T930 is a customized part built for Nokia 395 * by Avago. It is very similar to the Avago APDS-9930 with some 396 * minor differences. In the future a proper driver might need to 397 * be written for this device. For now this works fine. 398 */ 399 qpdst900: qpdst900@39 { 400 compatible = "avago,apds9930"; 401 reg = <0x39>; 402 403 interrupt-parent = <&tlmm>; 404 interrupts = <40 IRQ_TYPE_EDGE_FALLING>; 405 }; 406}; 407 408&blsp2_i2c5 { 409 status = "okay"; 410 411 fm_radio: si4705@11 { 412 compatible = "silabs,si470x"; 413 reg = <0x11>; 414 415 interrupt-parent = <&tlmm>; 416 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 417 reset-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>; 418 }; 419 420 vreg_lpddr_1p1: fan53526a@6c { 421 compatible = "fcs,fan53526"; 422 reg = <0x6c>; 423 424 regulator-min-microvolt = <1100000>; 425 regulator-max-microvolt = <1100000>; 426 vin-supply = <&vph_pwr>; 427 fcs,suspend-voltage-selector = <1>; 428 regulator-always-on; /* Turning off DDR power doesn't sound good. */ 429 }; 430 431 /* ANX7816 HDMI bridge (needs MDSS HDMI) */ 432}; 433 434&blsp2_spi4 { 435 status = "okay"; 436 437 /* 438 * This device is a Lattice UC120 USB-C PD PHY. 439 * It is actually a Lattice iCE40 FPGA pre-programmed by 440 * the device firmware with a specific bitstream 441 * enabling USB Type C PHY functionality. 442 * Communication is done via a proprietary protocol over SPI. 443 * 444 * TODO: Once a proper driver is available, replace this. 445 */ 446 uc120: ice5lp2k@0 { 447 compatible = "lattice,ice40-fpga-mgr"; 448 reg = <0>; 449 spi-max-frequency = <5000000>; 450 cdone-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; 451 reset-gpios = <&pmi8994_gpios 4 GPIO_ACTIVE_LOW>; 452 }; 453}; 454 455&blsp2_uart2 { 456 status = "okay"; 457 458 qca6174_bt: bluetooth { 459 compatible = "qcom,qca6174-bt"; 460 461 enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; 462 clocks = <&divclk4>; 463 }; 464}; 465 466&pm8994_gpios { 467 bt_en_gpios: bt-en-gpios-state { 468 pinconf { 469 pins = "gpio19"; 470 function = PMIC_GPIO_FUNC_NORMAL; 471 output-low; 472 power-source = <PM8994_GPIO_S4>; 473 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 474 bias-pull-down; 475 }; 476 }; 477 478 divclk4_pin_a: divclk4-state { 479 pinconf { 480 pins = "gpio18"; 481 function = PMIC_GPIO_FUNC_FUNC2; 482 power-source = <PM8994_GPIO_S4>; 483 bias-disable; 484 }; 485 }; 486}; 487 488&pm8994_pon { 489 pwrkey { 490 compatible = "qcom,pm8941-pwrkey"; 491 interrupts = <0 8 0 IRQ_TYPE_EDGE_BOTH>; 492 debounce = <15625>; 493 linux,code = <KEY_POWER>; 494 }; 495 496 resin { 497 compatible = "qcom,pm8941-resin"; 498 interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>; 499 debounce = <15625>; 500 linux,code = <KEY_VOLUMEDOWN>; 501 }; 502}; 503 504&pmi8994_gpios { 505 pinctrl-0 = <&hd3ss460_pol &hd3ss460_amsel &hd3ss460_en>; 506 pinctrl-names = "default"; 507 508 /* 509 * This device uses a TI HD3SS460 Type-C MUX 510 * As this device has no driver currently, 511 * the configuration for USB Face Up is set-up here. 512 * 513 * TODO: remove once a driver is available 514 * TODO: add VBUS GPIO 5 515 */ 516 hd3ss460_pol: pol-low-state { 517 pins = "gpio8"; 518 function = PMIC_GPIO_FUNC_NORMAL; 519 qcom,drive-strength = <3>; 520 bias-pull-down; 521 }; 522 523 hd3ss460_amsel: amsel-high-state { 524 pins = "gpio9"; 525 function = PMIC_GPIO_FUNC_NORMAL; 526 qcom,drive-strength = <1>; 527 bias-pull-up; 528 }; 529 530 hd3ss460_en: en-high-state { 531 pins = "gpio10"; 532 function = PMIC_GPIO_FUNC_NORMAL; 533 qcom,drive-strength = <1>; 534 bias-pull-up; 535 }; 536}; 537 538&pmi8994_spmi_regulators { 539 vdd_gfx: s2 { 540 regulator-min-microvolt = <980000>; 541 regulator-max-microvolt = <980000>; 542 }; 543}; 544 545&rpm_requests { 546 /* These values were taken from the original firmware ACPI tables */ 547 pm8994_regulators: regulators-0 { 548 compatible = "qcom,rpm-pm8994-regulators"; 549 550 vdd_s1-supply = <&vph_pwr>; 551 vdd_s2-supply = <&vph_pwr>; 552 vdd_s3-supply = <&vph_pwr>; 553 vdd_s4-supply = <&vph_pwr>; 554 vdd_s5-supply = <&vph_pwr>; 555 vdd_s6-supply = <&vph_pwr>; 556 vdd_s7-supply = <&vph_pwr>; 557 vdd_s8-supply = <&vph_pwr>; 558 vdd_s9-supply = <&vph_pwr>; 559 vdd_s10-supply = <&vph_pwr>; 560 vdd_s11-supply = <&vph_pwr>; 561 vdd_s12-supply = <&vph_pwr>; 562 vdd_l1-supply = <&vreg_s1b_1p0>; 563 vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; 564 vdd_l3_l11-supply = <&vreg_s3a_1p3>; 565 vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; 566 vdd_l5_l7-supply = <&vreg_s5a_2p15>; 567 vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; 568 vdd_l8_l16_l30-supply = <&vph_pwr>; 569 vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; 570 vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; 571 vdd_l14_l15-supply = <&vreg_s5a_2p15>; 572 vdd_l17_l29-supply = <&vph_pwr_bbyp>; 573 vdd_l20_l21-supply = <&vph_pwr_bbyp>; 574 vdd_l25-supply = <&vreg_s5a_2p15>; 575 vdd_lvs1_2-supply = <&vreg_s4a_1p8>; 576 577 /* S1, S2, S6 and S12 are managed by RPMPD */ 578 579 vreg_s3a_1p3: s3 { 580 regulator-min-microvolt = <1300000>; 581 regulator-max-microvolt = <1300000>; 582 regulator-allow-set-load; 583 regulator-system-load = <300000>; 584 }; 585 586 vreg_s4a_1p8: s4 { 587 regulator-min-microvolt = <1800000>; 588 regulator-max-microvolt = <1800000>; 589 regulator-allow-set-load; 590 regulator-always-on; 591 regulator-system-load = <325000>; 592 }; 593 594 vreg_s5a_2p15: s5 { 595 regulator-min-microvolt = <2150000>; 596 regulator-max-microvolt = <2150000>; 597 regulator-allow-set-load; 598 regulator-system-load = <325000>; 599 }; 600 601 vreg_s7a_1p0: s7 { 602 regulator-min-microvolt = <1000000>; 603 regulator-max-microvolt = <1000000>; 604 }; 605 606 /* 607 * S8 - SPMI-managed VDD_APC0 608 * S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1 609 */ 610 611 vreg_l1a_1p0: l1 { 612 regulator-min-microvolt = <1000000>; 613 regulator-max-microvolt = <1000000>; 614 }; 615 616 vreg_l2a_1p25: l2 { 617 regulator-min-microvolt = <1250000>; 618 regulator-max-microvolt = <1250000>; 619 regulator-allow-set-load; 620 regulator-system-load = <4160>; 621 }; 622 623 vreg_l3a_1p2: l3 { 624 regulator-min-microvolt = <1200000>; 625 regulator-max-microvolt = <1200000>; 626 regulator-always-on; 627 regulator-allow-set-load; 628 regulator-system-load = <80000>; 629 }; 630 631 vreg_l4a_1p225: l4 { 632 regulator-min-microvolt = <1225000>; 633 regulator-max-microvolt = <1225000>; 634 }; 635 636 /* L5 is inaccessible from RPM */ 637 638 vreg_l6a_1p8: l6 { 639 regulator-min-microvolt = <1800000>; 640 regulator-max-microvolt = <1800000>; 641 regulator-allow-set-load; 642 regulator-system-load = <1000>; 643 }; 644 645 /* L7 is inaccessible from RPM */ 646 647 vreg_l8a_1p8: l8 { 648 regulator-min-microvolt = <1800000>; 649 regulator-max-microvolt = <1800000>; 650 }; 651 652 vreg_l9a_1p8: l9 { 653 regulator-min-microvolt = <1800000>; 654 regulator-max-microvolt = <1800000>; 655 }; 656 657 vreg_l10a_1p8: l10 { 658 regulator-min-microvolt = <1800000>; 659 regulator-max-microvolt = <1800000>; 660 }; 661 662 vreg_l11a_1p2: l11 { 663 regulator-min-microvolt = <1200000>; 664 regulator-max-microvolt = <1200000>; 665 regulator-always-on; 666 regulator-allow-set-load; 667 regulator-system-load = <35000>; 668 }; 669 670 vreg_l12a_1p8: l12 { 671 regulator-min-microvolt = <1800000>; 672 regulator-max-microvolt = <1800000>; 673 regulator-always-on; 674 regulator-allow-set-load; 675 regulator-system-load = <50000>; 676 }; 677 678 vreg_l13a_2p95: l13 { 679 regulator-min-microvolt = <1850000>; 680 regulator-max-microvolt = <2950000>; 681 regulator-always-on; 682 regulator-allow-set-load; 683 regulator-system-load = <22000>; 684 }; 685 686 vreg_l14a_1p8: l14 { 687 regulator-min-microvolt = <1800000>; 688 regulator-max-microvolt = <1800000>; 689 regulator-always-on; 690 regulator-allow-set-load; 691 regulator-system-load = <52000>; 692 }; 693 694 vreg_l15a_1p8: l15 { 695 regulator-min-microvolt = <1800000>; 696 regulator-max-microvolt = <1800000>; 697 }; 698 699 vreg_l16a_2p7: l16 { 700 regulator-min-microvolt = <2700000>; 701 regulator-max-microvolt = <2700000>; 702 }; 703 704 vreg_l17a_2p7: l17 { 705 regulator-min-microvolt = <2800000>; 706 regulator-max-microvolt = <2800000>; 707 regulator-always-on; 708 regulator-allow-set-load; 709 regulator-system-load = <300000>; 710 }; 711 712 vreg_l18a_2p85: l18 { 713 regulator-min-microvolt = <2850000>; 714 regulator-max-microvolt = <2850000>; 715 regulator-always-on; 716 regulator-allow-set-load; 717 regulator-system-load = <600000>; 718 }; 719 720 vreg_l19a_3p3: l19 { 721 regulator-min-microvolt = <3300000>; 722 regulator-max-microvolt = <3300000>; 723 regulator-always-on; 724 regulator-allow-set-load; 725 regulator-system-load = <500000>; 726 }; 727 728 vreg_l20a_2p95: l20 { 729 regulator-min-microvolt = <2950000>; 730 regulator-max-microvolt = <2950000>; 731 regulator-always-on; 732 regulator-boot-on; 733 regulator-allow-set-load; 734 regulator-system-load = <570000>; 735 }; 736 737 vreg_l21a_2p95: l21 { 738 regulator-min-microvolt = <2950000>; 739 regulator-max-microvolt = <2950000>; 740 regulator-always-on; 741 regulator-allow-set-load; 742 regulator-system-load = <800000>; 743 }; 744 745 vreg_l22a_3p0: l22 { 746 regulator-min-microvolt = <3000000>; 747 regulator-max-microvolt = <3000000>; 748 regulator-always-on; 749 regulator-allow-set-load; 750 regulator-system-load = <150000>; 751 }; 752 753 vreg_l23a_2p8: l23 { 754 regulator-min-microvolt = <2850000>; 755 regulator-max-microvolt = <2850000>; 756 regulator-always-on; 757 regulator-allow-set-load; 758 regulator-system-load = <80000>; 759 }; 760 761 vreg_l24a_3p075: l24 { 762 regulator-min-microvolt = <3075000>; 763 regulator-max-microvolt = <3150000>; 764 regulator-allow-set-load; 765 regulator-system-load = <5800>; 766 }; 767 768 vreg_l25a_1p1: l25 { 769 regulator-min-microvolt = <1150000>; 770 regulator-max-microvolt = <1150000>; 771 regulator-always-on; 772 regulator-allow-set-load; 773 regulator-system-load = <80000>; 774 }; 775 776 vreg_l26a_1p0: l26 { 777 regulator-min-microvolt = <1000000>; 778 regulator-max-microvolt = <1000000>; 779 }; 780 781 vreg_l27a_1p05: l27 { 782 regulator-min-microvolt = <1000000>; 783 regulator-max-microvolt = <1000000>; 784 regulator-always-on; 785 regulator-allow-set-load; 786 regulator-system-load = <500000>; 787 }; 788 789 vreg_l28a_1p0: l28 { 790 regulator-min-microvolt = <1000000>; 791 regulator-max-microvolt = <1000000>; 792 regulator-always-on; 793 regulator-allow-set-load; 794 regulator-system-load = <26000>; 795 }; 796 797 vreg_l29a_2p8: l29 { 798 regulator-min-microvolt = <2850000>; 799 regulator-max-microvolt = <2850000>; 800 regulator-always-on; 801 regulator-allow-set-load; 802 regulator-system-load = <80000>; 803 }; 804 805 vreg_l30a_1p8: l30 { 806 regulator-min-microvolt = <1800000>; 807 regulator-max-microvolt = <1800000>; 808 regulator-always-on; 809 regulator-allow-set-load; 810 regulator-system-load = <2500>; 811 }; 812 813 vreg_l31a_1p2: l31 { 814 regulator-min-microvolt = <1200000>; 815 regulator-max-microvolt = <1200000>; 816 regulator-always-on; 817 regulator-allow-set-load; 818 regulator-system-load = <600000>; 819 }; 820 821 vreg_l32a_1p8: l32 { 822 regulator-min-microvolt = <1800000>; 823 regulator-max-microvolt = <1800000>; 824 }; 825 826 vreg_lvs1a_1p8: lvs1 { }; 827 828 vreg_lvs2a_1p8: lvs2 { }; 829 }; 830 831 pmi8994_regulators: regulators-1 { 832 compatible = "qcom,rpm-pmi8994-regulators"; 833 834 vdd_s1-supply = <&vph_pwr>; 835 vdd_bst_byp-supply = <&vph_pwr>; 836 837 vreg_s1b_1p0: s1 { 838 regulator-min-microvolt = <1025000>; 839 regulator-max-microvolt = <1025000>; 840 }; 841 842 /* S2 & S3 - VDD_GFX */ 843 844 vph_pwr_bbyp: boost-bypass { 845 regulator-min-microvolt = <3300000>; 846 regulator-max-microvolt = <3300000>; 847 }; 848 }; 849}; 850 851&sdhc1 { 852 status = "okay"; 853 854 /* 855 * This device is shipped with HS400 capabable eMMCs 856 * However various brands have been used in various product batches, 857 * including a Samsung eMMC (BGND3R) which features a quirk with HS400. 858 * Set the speed to HS200 as a safety measure. 859 */ 860 mmc-hs200-1_8v; 861}; 862 863&sdhc2 { 864 status = "okay"; 865 866 pinctrl-names = "default", "sleep"; 867 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 868 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 869 870 vmmc-supply = <&vreg_l21a_2p95>; 871 vqmmc-supply = <&vreg_l13a_2p95>; 872 873 cd-gpios = <&pm8994_gpios 8 GPIO_ACTIVE_LOW>; 874}; 875 876&tlmm { 877 grip_default: grip-default-state { 878 pins = "gpio39"; 879 function = "gpio"; 880 drive-strength = <6>; 881 bias-pull-down; 882 }; 883 884 grip_sleep: grip-sleep-state { 885 pins = "gpio39"; 886 function = "gpio"; 887 drive-strength = <2>; 888 bias-pull-down; 889 }; 890 891 hall_front_default: hall-front-default-state { 892 pins = "gpio42"; 893 function = "gpio"; 894 drive-strength = <2>; 895 bias-disable; 896 }; 897 898 hall_back_default: hall-back-default-state { 899 pins = "gpio75"; 900 function = "gpio"; 901 drive-strength = <2>; 902 bias-disable; 903 }; 904}; 905