1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 hvddio-pex-supply = <&vdd_1v8>; 34 dvddio-pex-supply = <&vdd_pex_1v05>; 35 vddio-pex-ctl-supply = <&vdd_1v8>; 36 37 pci@1,0 { 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 43 nvidia,num-lanes = <4>; 44 status = "okay"; 45 }; 46 47 pci@2,0 { 48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 49 phy-names = "pcie-0"; 50 status = "okay"; 51 52 ethernet@0,0 { 53 reg = <0x000000 0 0 0 0>; 54 local-mac-address = [ 00 00 00 00 00 00 ]; 55 }; 56 }; 57 }; 58 59 host1x@50000000 { 60 dpaux@54040000 { 61 status = "okay"; 62 }; 63 64 vi@54080000 { 65 status = "okay"; 66 67 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 68 69 csi@838 { 70 status = "okay"; 71 }; 72 }; 73 74 sor@54540000 { 75 status = "okay"; 76 77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 79 80 nvidia,xbar-cfg = <2 1 0 3 4>; 81 nvidia,dpaux = <&dpaux>; 82 }; 83 84 sor@54580000 { 85 status = "okay"; 86 87 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 89 hdmi-supply = <&vdd_hdmi>; 90 91 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 93 GPIO_ACTIVE_LOW>; 94 nvidia,xbar-cfg = <0 1 2 3 4>; 95 }; 96 97 dpaux@545c0000 { 98 status = "okay"; 99 }; 100 101 i2c@546c0000 { 102 status = "okay"; 103 }; 104 }; 105 106 gpu@57000000 { 107 vdd-supply = <&vdd_gpu>; 108 status = "okay"; 109 }; 110 111 pinmux@700008d4 { 112 dvfs_pwm_active_state: pinmux-dvfs-pwm-active { 113 dvfs_pwm_pbb1 { 114 nvidia,pins = "dvfs_pwm_pbb1"; 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 }; 117 }; 118 119 dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { 120 dvfs_pwm_pbb1 { 121 nvidia,pins = "dvfs_pwm_pbb1"; 122 nvidia,tristate = <TEGRA_PIN_ENABLE>; 123 }; 124 }; 125 }; 126 127 /* debug port */ 128 serial@70006000 { 129 /delete-property/ dmas; 130 /delete-property/ dma-names; 131 status = "okay"; 132 }; 133 134 pwm@7000a000 { 135 status = "okay"; 136 }; 137 138 i2c@7000c500 { 139 status = "okay"; 140 clock-frequency = <100000>; 141 142 eeprom@50 { 143 compatible = "atmel,24c02"; 144 reg = <0x50>; 145 146 label = "module"; 147 vcc-supply = <&vdd_1v8>; 148 address-width = <8>; 149 pagesize = <8>; 150 size = <256>; 151 read-only; 152 }; 153 154 eeprom@57 { 155 compatible = "atmel,24c02"; 156 reg = <0x57>; 157 158 label = "system"; 159 vcc-supply = <&vdd_1v8>; 160 address-width = <8>; 161 pagesize = <8>; 162 size = <256>; 163 read-only; 164 }; 165 }; 166 167 hdmi_ddc: i2c@7000c700 { 168 status = "okay"; 169 clock-frequency = <100000>; 170 }; 171 172 i2c@7000d000 { 173 status = "okay"; 174 clock-frequency = <400000>; 175 176 pmic: pmic@3c { 177 compatible = "maxim,max77620"; 178 reg = <0x3c>; 179 interrupt-parent = <&tegra_pmc>; 180 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 181 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 185 #gpio-cells = <2>; 186 gpio-controller; 187 188 pinctrl-names = "default"; 189 pinctrl-0 = <&max77620_default>; 190 191 fps { 192 fps0 { 193 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 194 maxim,suspend-fps-time-period-us = <5120>; 195 }; 196 197 fps1 { 198 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 199 maxim,suspend-fps-time-period-us = <5120>; 200 }; 201 202 fps2 { 203 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 204 }; 205 }; 206 207 max77620_default: pinmux { 208 gpio0 { 209 pins = "gpio0"; 210 function = "gpio"; 211 }; 212 213 gpio1 { 214 pins = "gpio1"; 215 function = "fps-out"; 216 drive-push-pull = <1>; 217 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 218 maxim,active-fps-power-up-slot = <0>; 219 maxim,active-fps-power-down-slot = <7>; 220 }; 221 222 gpio2 { 223 pins = "gpio2"; 224 function = "fps-out"; 225 drive-open-drain = <1>; 226 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 227 maxim,active-fps-power-up-slot = <0>; 228 maxim,active-fps-power-down-slot = <7>; 229 }; 230 231 gpio3 { 232 pins = "gpio3"; 233 function = "fps-out"; 234 drive-open-drain = <1>; 235 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 236 maxim,active-fps-power-up-slot = <4>; 237 maxim,active-fps-power-down-slot = <3>; 238 }; 239 240 gpio4 { 241 pins = "gpio4"; 242 function = "32k-out1"; 243 }; 244 245 gpio5_6_7 { 246 pins = "gpio5", "gpio6", "gpio7"; 247 function = "gpio"; 248 drive-push-pull = <1>; 249 }; 250 }; 251 252 regulators { 253 in-ldo0-1-supply = <&vdd_pre>; 254 in-ldo2-supply = <&vdd_3v3_sys>; 255 in-ldo3-5-supply = <&vdd_1v8>; 256 in-ldo4-6-supply = <&vdd_5v0_sys>; 257 in-ldo7-8-supply = <&vdd_pre>; 258 in-sd0-supply = <&vdd_5v0_sys>; 259 in-sd1-supply = <&vdd_5v0_sys>; 260 in-sd2-supply = <&vdd_5v0_sys>; 261 in-sd3-supply = <&vdd_5v0_sys>; 262 263 vdd_soc: sd0 { 264 regulator-name = "VDD_SOC"; 265 regulator-min-microvolt = <1000000>; 266 regulator-max-microvolt = <1170000>; 267 regulator-enable-ramp-delay = <146>; 268 regulator-ramp-delay = <27500>; 269 regulator-always-on; 270 regulator-boot-on; 271 272 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 273 maxim,active-fps-power-up-slot = <1>; 274 maxim,active-fps-power-down-slot = <6>; 275 }; 276 277 vdd_ddr: sd1 { 278 regulator-name = "VDD_DDR_1V1_PMIC"; 279 regulator-min-microvolt = <1150000>; 280 regulator-max-microvolt = <1150000>; 281 regulator-enable-ramp-delay = <176>; 282 regulator-ramp-delay = <27500>; 283 regulator-always-on; 284 regulator-boot-on; 285 286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 287 maxim,active-fps-power-up-slot = <5>; 288 maxim,active-fps-power-down-slot = <2>; 289 }; 290 291 vdd_pre: sd2 { 292 regulator-name = "VDD_PRE_REG_1V35"; 293 regulator-min-microvolt = <1350000>; 294 regulator-max-microvolt = <1350000>; 295 regulator-enable-ramp-delay = <176>; 296 regulator-ramp-delay = <27500>; 297 regulator-always-on; 298 regulator-boot-on; 299 300 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 301 maxim,active-fps-power-up-slot = <2>; 302 maxim,active-fps-power-down-slot = <5>; 303 }; 304 305 vdd_1v8: sd3 { 306 regulator-name = "VDD_1V8"; 307 regulator-min-microvolt = <1800000>; 308 regulator-max-microvolt = <1800000>; 309 regulator-enable-ramp-delay = <242>; 310 regulator-ramp-delay = <27500>; 311 regulator-always-on; 312 regulator-boot-on; 313 314 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 315 maxim,active-fps-power-up-slot = <3>; 316 maxim,active-fps-power-down-slot = <4>; 317 }; 318 319 vdd_sys_1v2: ldo0 { 320 regulator-name = "AVDD_SYS_1V2"; 321 regulator-min-microvolt = <1200000>; 322 regulator-max-microvolt = <1200000>; 323 regulator-enable-ramp-delay = <26>; 324 regulator-ramp-delay = <100000>; 325 regulator-always-on; 326 regulator-boot-on; 327 328 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 329 maxim,active-fps-power-up-slot = <0>; 330 maxim,active-fps-power-down-slot = <7>; 331 }; 332 333 vdd_pex_1v05: ldo1 { 334 regulator-name = "VDD_PEX_1V05"; 335 regulator-min-microvolt = <1050000>; 336 regulator-max-microvolt = <1050000>; 337 regulator-enable-ramp-delay = <22>; 338 regulator-ramp-delay = <100000>; 339 340 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 341 maxim,active-fps-power-up-slot = <0>; 342 maxim,active-fps-power-down-slot = <7>; 343 }; 344 345 vddio_sdmmc: ldo2 { 346 regulator-name = "VDDIO_SDMMC"; 347 regulator-min-microvolt = <1800000>; 348 regulator-max-microvolt = <3300000>; 349 regulator-enable-ramp-delay = <62>; 350 regulator-ramp-delay = <100000>; 351 352 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 353 maxim,active-fps-power-up-slot = <0>; 354 maxim,active-fps-power-down-slot = <7>; 355 }; 356 357 ldo3 { 358 status = "disabled"; 359 }; 360 361 vdd_rtc: ldo4 { 362 regulator-name = "VDD_RTC"; 363 regulator-min-microvolt = <850000>; 364 regulator-max-microvolt = <1100000>; 365 regulator-enable-ramp-delay = <22>; 366 regulator-ramp-delay = <100000>; 367 regulator-disable-active-discharge; 368 regulator-always-on; 369 regulator-boot-on; 370 371 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 372 maxim,active-fps-power-up-slot = <1>; 373 maxim,active-fps-power-down-slot = <6>; 374 }; 375 376 ldo5 { 377 status = "disabled"; 378 }; 379 380 ldo6 { 381 status = "disabled"; 382 }; 383 384 avdd_1v05_pll: ldo7 { 385 regulator-name = "AVDD_1V05_PLL"; 386 regulator-min-microvolt = <1050000>; 387 regulator-max-microvolt = <1050000>; 388 regulator-enable-ramp-delay = <24>; 389 regulator-ramp-delay = <100000>; 390 391 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 392 maxim,active-fps-power-up-slot = <3>; 393 maxim,active-fps-power-down-slot = <4>; 394 }; 395 396 avdd_1v05: ldo8 { 397 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 398 regulator-min-microvolt = <1050000>; 399 regulator-max-microvolt = <1050000>; 400 regulator-enable-ramp-delay = <22>; 401 regulator-ramp-delay = <100000>; 402 403 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 404 maxim,active-fps-power-up-slot = <6>; 405 maxim,active-fps-power-down-slot = <1>; 406 }; 407 }; 408 }; 409 }; 410 411 pmc@7000e400 { 412 nvidia,invert-interrupt; 413 nvidia,suspend-mode = <0>; 414 nvidia,cpu-pwr-good-time = <0>; 415 nvidia,cpu-pwr-off-time = <0>; 416 nvidia,core-pwr-good-time = <4587 3876>; 417 nvidia,core-pwr-off-time = <39065>; 418 nvidia,core-power-req-active-high; 419 nvidia,sys-clock-req-active-high; 420 }; 421 422 hda@70030000 { 423 nvidia,model = "NVIDIA Jetson Nano HDA"; 424 425 status = "okay"; 426 }; 427 428 usb@70090000 { 429 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 430 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 431 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 432 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 433 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 434 435 avdd-usb-supply = <&vdd_3v3_sys>; 436 dvddio-pex-supply = <&vdd_pex_1v05>; 437 hvddio-pex-supply = <&vdd_1v8>; 438 439 status = "okay"; 440 }; 441 442 padctl@7009f000 { 443 status = "okay"; 444 445 avdd-pll-utmip-supply = <&vdd_1v8>; 446 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 447 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 448 hvdd-pex-pll-e-supply = <&vdd_1v8>; 449 450 pads { 451 usb2 { 452 status = "okay"; 453 454 lanes { 455 micro_b: usb2-0 { 456 nvidia,function = "xusb"; 457 status = "okay"; 458 }; 459 460 usb2-1 { 461 nvidia,function = "xusb"; 462 status = "okay"; 463 }; 464 465 usb2-2 { 466 nvidia,function = "xusb"; 467 status = "okay"; 468 }; 469 }; 470 }; 471 472 pcie { 473 status = "okay"; 474 475 lanes { 476 pcie-0 { 477 nvidia,function = "pcie-x1"; 478 status = "okay"; 479 }; 480 481 pcie-1 { 482 nvidia,function = "pcie-x4"; 483 status = "okay"; 484 }; 485 486 pcie-2 { 487 nvidia,function = "pcie-x4"; 488 status = "okay"; 489 }; 490 491 pcie-3 { 492 nvidia,function = "pcie-x4"; 493 status = "okay"; 494 }; 495 496 pcie-4 { 497 nvidia,function = "pcie-x4"; 498 status = "okay"; 499 }; 500 501 pcie-5 { 502 nvidia,function = "usb3-ss"; 503 status = "okay"; 504 }; 505 506 pcie-6 { 507 nvidia,function = "usb3-ss"; 508 status = "okay"; 509 }; 510 }; 511 }; 512 }; 513 514 ports { 515 usb2-0 { 516 status = "okay"; 517 mode = "peripheral"; 518 usb-role-switch; 519 520 vbus-supply = <&vdd_5v0_usb>; 521 522 connector { 523 compatible = "gpio-usb-b-connector", 524 "usb-b-connector"; 525 label = "micro-USB"; 526 type = "micro"; 527 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 528 GPIO_ACTIVE_LOW>; 529 }; 530 }; 531 532 usb2-1 { 533 status = "okay"; 534 mode = "host"; 535 }; 536 537 usb2-2 { 538 status = "okay"; 539 mode = "host"; 540 }; 541 542 usb3-0 { 543 status = "okay"; 544 nvidia,usb2-companion = <1>; 545 vbus-supply = <&vdd_hub_3v3>; 546 }; 547 }; 548 }; 549 550 mmc@700b0000 { 551 status = "okay"; 552 bus-width = <4>; 553 554 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 555 disable-wp; 556 557 vqmmc-supply = <&vddio_sdmmc>; 558 vmmc-supply = <&vdd_3v3_sd>; 559 }; 560 561 mmc@700b0400 { 562 status = "okay"; 563 bus-width = <4>; 564 565 vqmmc-supply = <&vdd_1v8>; 566 vmmc-supply = <&vdd_3v3_sys>; 567 568 non-removable; 569 cap-sdio-irq; 570 keep-power-in-suspend; 571 wakeup-source; 572 }; 573 574 usb@700d0000 { 575 status = "okay"; 576 phys = <µ_b>; 577 phy-names = "usb2-0"; 578 avddio-usb-supply = <&vdd_3v3_sys>; 579 hvdd-usb-supply = <&vdd_1v8>; 580 }; 581 582 clock@70110000 { 583 status = "okay"; 584 585 nvidia,cf = <6>; 586 nvidia,ci = <0>; 587 nvidia,cg = <2>; 588 nvidia,droop-ctrl = <0x00000f00>; 589 nvidia,force-mode = <1>; 590 nvidia,sample-rate = <25000>; 591 592 nvidia,pwm-min-microvolts = <708000>; 593 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 594 nvidia,pwm-to-pmic; 595 nvidia,pwm-tristate-microvolts = <1000000>; 596 nvidia,pwm-voltage-step-microvolts = <19200>; 597 598 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 599 pinctrl-0 = <&dvfs_pwm_active_state>; 600 pinctrl-1 = <&dvfs_pwm_inactive_state>; 601 }; 602 603 aconnect@702c0000 { 604 status = "okay"; 605 606 ahub@702d0800 { 607 status = "okay"; 608 609 admaif@702d0000 { 610 status = "okay"; 611 }; 612 613 i2s@702d1200 { 614 status = "okay"; 615 616 ports { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 620 port@0 { 621 reg = <0>; 622 623 i2s3_cif_ep: endpoint { 624 remote-endpoint = <&xbar_i2s3_ep>; 625 }; 626 }; 627 628 i2s3_port: port@1 { 629 reg = <1>; 630 631 i2s3_dap_ep: endpoint { 632 dai-format = "i2s"; 633 /* Placeholder for external Codec */ 634 }; 635 }; 636 }; 637 }; 638 639 i2s@702d1300 { 640 status = "okay"; 641 642 ports { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 port@0 { 647 reg = <0>; 648 649 i2s4_cif_ep: endpoint { 650 remote-endpoint = <&xbar_i2s4_ep>; 651 }; 652 }; 653 654 i2s4_port: port@1 { 655 reg = <1>; 656 657 i2s4_dap_ep: endpoint { 658 dai-format = "i2s"; 659 /* Placeholder for external Codec */ 660 }; 661 }; 662 }; 663 }; 664 665 sfc@702d2000 { 666 status = "okay"; 667 668 ports { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 672 port@0 { 673 reg = <0>; 674 675 sfc1_cif_in_ep: endpoint { 676 remote-endpoint = <&xbar_sfc1_in_ep>; 677 }; 678 }; 679 680 sfc1_out_port: port@1 { 681 reg = <1>; 682 683 sfc1_cif_out_ep: endpoint { 684 remote-endpoint = <&xbar_sfc1_out_ep>; 685 }; 686 }; 687 }; 688 }; 689 690 sfc@702d2200 { 691 status = "okay"; 692 693 ports { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 port@0 { 698 reg = <0>; 699 700 sfc2_cif_in_ep: endpoint { 701 remote-endpoint = <&xbar_sfc2_in_ep>; 702 }; 703 }; 704 705 sfc2_out_port: port@1 { 706 reg = <1>; 707 708 sfc2_cif_out_ep: endpoint { 709 remote-endpoint = <&xbar_sfc2_out_ep>; 710 }; 711 }; 712 }; 713 }; 714 715 sfc@702d2400 { 716 status = "okay"; 717 718 ports { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 722 port@0 { 723 reg = <0>; 724 725 sfc3_cif_in_ep: endpoint { 726 remote-endpoint = <&xbar_sfc3_in_ep>; 727 }; 728 }; 729 730 sfc3_out_port: port@1 { 731 reg = <1>; 732 733 sfc3_cif_out_ep: endpoint { 734 remote-endpoint = <&xbar_sfc3_out_ep>; 735 }; 736 }; 737 }; 738 }; 739 740 sfc@702d2600 { 741 status = "okay"; 742 743 ports { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 port@0 { 748 reg = <0>; 749 750 sfc4_cif_in_ep: endpoint { 751 remote-endpoint = <&xbar_sfc4_in_ep>; 752 }; 753 }; 754 755 sfc4_out_port: port@1 { 756 reg = <1>; 757 758 sfc4_cif_out_ep: endpoint { 759 remote-endpoint = <&xbar_sfc4_out_ep>; 760 }; 761 }; 762 }; 763 }; 764 765 amx@702d3000 { 766 status = "okay"; 767 768 ports { 769 #address-cells = <1>; 770 #size-cells = <0>; 771 772 port@0 { 773 reg = <0>; 774 775 amx1_in1_ep: endpoint { 776 remote-endpoint = <&xbar_amx1_in1_ep>; 777 }; 778 }; 779 780 port@1 { 781 reg = <1>; 782 783 amx1_in2_ep: endpoint { 784 remote-endpoint = <&xbar_amx1_in2_ep>; 785 }; 786 }; 787 788 port@2 { 789 reg = <2>; 790 791 amx1_in3_ep: endpoint { 792 remote-endpoint = <&xbar_amx1_in3_ep>; 793 }; 794 }; 795 796 port@3 { 797 reg = <3>; 798 799 amx1_in4_ep: endpoint { 800 remote-endpoint = <&xbar_amx1_in4_ep>; 801 }; 802 }; 803 804 amx1_out_port: port@4 { 805 reg = <4>; 806 807 amx1_out_ep: endpoint { 808 remote-endpoint = <&xbar_amx1_out_ep>; 809 }; 810 }; 811 }; 812 }; 813 814 amx@702d3100 { 815 status = "okay"; 816 817 ports { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 port@0 { 822 reg = <0>; 823 824 amx2_in1_ep: endpoint { 825 remote-endpoint = <&xbar_amx2_in1_ep>; 826 }; 827 }; 828 829 port@1 { 830 reg = <1>; 831 832 amx2_in2_ep: endpoint { 833 remote-endpoint = <&xbar_amx2_in2_ep>; 834 }; 835 }; 836 837 amx2_in3_port: port@2 { 838 reg = <2>; 839 840 amx2_in3_ep: endpoint { 841 remote-endpoint = <&xbar_amx2_in3_ep>; 842 }; 843 }; 844 845 amx2_in4_port: port@3 { 846 reg = <3>; 847 848 amx2_in4_ep: endpoint { 849 remote-endpoint = <&xbar_amx2_in4_ep>; 850 }; 851 }; 852 853 amx2_out_port: port@4 { 854 reg = <4>; 855 856 amx2_out_ep: endpoint { 857 remote-endpoint = <&xbar_amx2_out_ep>; 858 }; 859 }; 860 }; 861 }; 862 863 adx@702d3800 { 864 status = "okay"; 865 866 ports { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 870 port@0 { 871 reg = <0>; 872 873 adx1_in_ep: endpoint { 874 remote-endpoint = <&xbar_adx1_in_ep>; 875 }; 876 }; 877 878 adx1_out1_port: port@1 { 879 reg = <1>; 880 881 adx1_out1_ep: endpoint { 882 remote-endpoint = <&xbar_adx1_out1_ep>; 883 }; 884 }; 885 886 adx1_out2_port: port@2 { 887 reg = <2>; 888 889 adx1_out2_ep: endpoint { 890 remote-endpoint = <&xbar_adx1_out2_ep>; 891 }; 892 }; 893 894 adx1_out3_port: port@3 { 895 reg = <3>; 896 897 adx1_out3_ep: endpoint { 898 remote-endpoint = <&xbar_adx1_out3_ep>; 899 }; 900 }; 901 902 adx1_out4_port: port@4 { 903 reg = <4>; 904 905 adx1_out4_ep: endpoint { 906 remote-endpoint = <&xbar_adx1_out4_ep>; 907 }; 908 }; 909 }; 910 }; 911 912 adx@702d3900 { 913 status = "okay"; 914 915 ports { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 919 port@0 { 920 reg = <0>; 921 922 adx2_in_ep: endpoint { 923 remote-endpoint = <&xbar_adx2_in_ep>; 924 }; 925 }; 926 927 adx2_out1_port: port@1 { 928 reg = <1>; 929 930 adx2_out1_ep: endpoint { 931 remote-endpoint = <&xbar_adx2_out1_ep>; 932 }; 933 }; 934 935 adx2_out2_port: port@2 { 936 reg = <2>; 937 938 adx2_out2_ep: endpoint { 939 remote-endpoint = <&xbar_adx2_out2_ep>; 940 }; 941 }; 942 943 adx2_out3_port: port@3 { 944 reg = <3>; 945 946 adx2_out3_ep: endpoint { 947 remote-endpoint = <&xbar_adx2_out3_ep>; 948 }; 949 }; 950 951 adx2_out4_port: port@4 { 952 reg = <4>; 953 954 adx2_out4_ep: endpoint { 955 remote-endpoint = <&xbar_adx2_out4_ep>; 956 }; 957 }; 958 }; 959 }; 960 961 dmic@702d4000 { 962 status = "okay"; 963 964 ports { 965 #address-cells = <1>; 966 #size-cells = <0>; 967 968 port@0 { 969 reg = <0>; 970 971 dmic1_cif_ep: endpoint { 972 remote-endpoint = <&xbar_dmic1_ep>; 973 }; 974 }; 975 976 dmic1_port: port@1 { 977 reg = <1>; 978 979 dmic1_dap_ep: endpoint { 980 /* Placeholder for external Codec */ 981 }; 982 }; 983 }; 984 }; 985 986 dmic@702d4100 { 987 status = "okay"; 988 989 ports { 990 #address-cells = <1>; 991 #size-cells = <0>; 992 993 port@0 { 994 reg = <0>; 995 996 dmic2_cif_ep: endpoint { 997 remote-endpoint = <&xbar_dmic2_ep>; 998 }; 999 }; 1000 1001 dmic2_port: port@1 { 1002 reg = <1>; 1003 1004 dmic2_dap_ep: endpoint { 1005 /* Placeholder for external Codec */ 1006 }; 1007 }; 1008 }; 1009 }; 1010 1011 processing-engine@702d8000 { 1012 status = "okay"; 1013 1014 ports { 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 1018 port@0 { 1019 reg = <0x0>; 1020 1021 ope1_cif_in_ep: endpoint { 1022 remote-endpoint = <&xbar_ope1_in_ep>; 1023 }; 1024 }; 1025 1026 ope1_out_port: port@1 { 1027 reg = <0x1>; 1028 1029 ope1_cif_out_ep: endpoint { 1030 remote-endpoint = <&xbar_ope1_out_ep>; 1031 }; 1032 }; 1033 }; 1034 }; 1035 1036 processing-engine@702d8400 { 1037 status = "okay"; 1038 1039 ports { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 port@0 { 1044 reg = <0x0>; 1045 1046 ope2_cif_in_ep: endpoint { 1047 remote-endpoint = <&xbar_ope2_in_ep>; 1048 }; 1049 }; 1050 1051 ope2_out_port: port@1 { 1052 reg = <0x1>; 1053 1054 ope2_cif_out_ep: endpoint { 1055 remote-endpoint = <&xbar_ope2_out_ep>; 1056 }; 1057 }; 1058 }; 1059 }; 1060 1061 mvc@702da000 { 1062 status = "okay"; 1063 1064 ports { 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 port@0 { 1069 reg = <0>; 1070 1071 mvc1_cif_in_ep: endpoint { 1072 remote-endpoint = <&xbar_mvc1_in_ep>; 1073 }; 1074 }; 1075 1076 mvc1_out_port: port@1 { 1077 reg = <1>; 1078 1079 mvc1_cif_out_ep: endpoint { 1080 remote-endpoint = <&xbar_mvc1_out_ep>; 1081 }; 1082 }; 1083 }; 1084 }; 1085 1086 mvc@702da200 { 1087 status = "okay"; 1088 1089 ports { 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 1093 port@0 { 1094 reg = <0>; 1095 1096 mvc2_cif_in_ep: endpoint { 1097 remote-endpoint = <&xbar_mvc2_in_ep>; 1098 }; 1099 }; 1100 1101 mvc2_out_port: port@1 { 1102 reg = <1>; 1103 1104 mvc2_cif_out_ep: endpoint { 1105 remote-endpoint = <&xbar_mvc2_out_ep>; 1106 }; 1107 }; 1108 }; 1109 }; 1110 1111 amixer@702dbb00 { 1112 status = "okay"; 1113 1114 ports { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 1118 port@0 { 1119 reg = <0x0>; 1120 1121 mixer_in1_ep: endpoint { 1122 remote-endpoint = <&xbar_mixer_in1_ep>; 1123 }; 1124 }; 1125 1126 port@1 { 1127 reg = <0x1>; 1128 1129 mixer_in2_ep: endpoint { 1130 remote-endpoint = <&xbar_mixer_in2_ep>; 1131 }; 1132 }; 1133 1134 port@2 { 1135 reg = <0x2>; 1136 1137 mixer_in3_ep: endpoint { 1138 remote-endpoint = <&xbar_mixer_in3_ep>; 1139 }; 1140 }; 1141 1142 port@3 { 1143 reg = <0x3>; 1144 1145 mixer_in4_ep: endpoint { 1146 remote-endpoint = <&xbar_mixer_in4_ep>; 1147 }; 1148 }; 1149 1150 port@4 { 1151 reg = <0x4>; 1152 1153 mixer_in5_ep: endpoint { 1154 remote-endpoint = <&xbar_mixer_in5_ep>; 1155 }; 1156 }; 1157 1158 port@5 { 1159 reg = <0x5>; 1160 1161 mixer_in6_ep: endpoint { 1162 remote-endpoint = <&xbar_mixer_in6_ep>; 1163 }; 1164 }; 1165 1166 port@6 { 1167 reg = <0x6>; 1168 1169 mixer_in7_ep: endpoint { 1170 remote-endpoint = <&xbar_mixer_in7_ep>; 1171 }; 1172 }; 1173 1174 port@7 { 1175 reg = <0x7>; 1176 1177 mixer_in8_ep: endpoint { 1178 remote-endpoint = <&xbar_mixer_in8_ep>; 1179 }; 1180 }; 1181 1182 port@8 { 1183 reg = <0x8>; 1184 1185 mixer_in9_ep: endpoint { 1186 remote-endpoint = <&xbar_mixer_in9_ep>; 1187 }; 1188 }; 1189 1190 port@9 { 1191 reg = <0x9>; 1192 1193 mixer_in10_ep: endpoint { 1194 remote-endpoint = <&xbar_mixer_in10_ep>; 1195 }; 1196 }; 1197 1198 mixer_out1_port: port@a { 1199 reg = <0xa>; 1200 1201 mixer_out1_ep: endpoint { 1202 remote-endpoint = <&xbar_mixer_out1_ep>; 1203 }; 1204 }; 1205 1206 mixer_out2_port: port@b { 1207 reg = <0xb>; 1208 1209 mixer_out2_ep: endpoint { 1210 remote-endpoint = <&xbar_mixer_out2_ep>; 1211 }; 1212 }; 1213 1214 mixer_out3_port: port@c { 1215 reg = <0xc>; 1216 1217 mixer_out3_ep: endpoint { 1218 remote-endpoint = <&xbar_mixer_out3_ep>; 1219 }; 1220 }; 1221 1222 mixer_out4_port: port@d { 1223 reg = <0xd>; 1224 1225 mixer_out4_ep: endpoint { 1226 remote-endpoint = <&xbar_mixer_out4_ep>; 1227 }; 1228 }; 1229 1230 mixer_out5_port: port@e { 1231 reg = <0xe>; 1232 1233 mixer_out5_ep: endpoint { 1234 remote-endpoint = <&xbar_mixer_out5_ep>; 1235 }; 1236 }; 1237 }; 1238 }; 1239 1240 ports { 1241 xbar_i2s3_port: port@c { 1242 reg = <0xc>; 1243 1244 xbar_i2s3_ep: endpoint { 1245 remote-endpoint = <&i2s3_cif_ep>; 1246 }; 1247 }; 1248 1249 xbar_i2s4_port: port@d { 1250 reg = <0xd>; 1251 1252 xbar_i2s4_ep: endpoint { 1253 remote-endpoint = <&i2s4_cif_ep>; 1254 }; 1255 }; 1256 1257 xbar_dmic1_port: port@f { 1258 reg = <0xf>; 1259 1260 xbar_dmic1_ep: endpoint { 1261 remote-endpoint = <&dmic1_cif_ep>; 1262 }; 1263 }; 1264 1265 xbar_dmic2_port: port@10 { 1266 reg = <0x10>; 1267 1268 xbar_dmic2_ep: endpoint { 1269 remote-endpoint = <&dmic2_cif_ep>; 1270 }; 1271 }; 1272 1273 xbar_sfc1_in_port: port@12 { 1274 reg = <0x12>; 1275 1276 xbar_sfc1_in_ep: endpoint { 1277 remote-endpoint = <&sfc1_cif_in_ep>; 1278 }; 1279 }; 1280 1281 port@13 { 1282 reg = <0x13>; 1283 1284 xbar_sfc1_out_ep: endpoint { 1285 remote-endpoint = <&sfc1_cif_out_ep>; 1286 }; 1287 }; 1288 1289 xbar_sfc2_in_port: port@14 { 1290 reg = <0x14>; 1291 1292 xbar_sfc2_in_ep: endpoint { 1293 remote-endpoint = <&sfc2_cif_in_ep>; 1294 }; 1295 }; 1296 1297 port@15 { 1298 reg = <0x15>; 1299 1300 xbar_sfc2_out_ep: endpoint { 1301 remote-endpoint = <&sfc2_cif_out_ep>; 1302 }; 1303 }; 1304 1305 xbar_sfc3_in_port: port@16 { 1306 reg = <0x16>; 1307 1308 xbar_sfc3_in_ep: endpoint { 1309 remote-endpoint = <&sfc3_cif_in_ep>; 1310 }; 1311 }; 1312 1313 port@17 { 1314 reg = <0x17>; 1315 1316 xbar_sfc3_out_ep: endpoint { 1317 remote-endpoint = <&sfc3_cif_out_ep>; 1318 }; 1319 }; 1320 1321 xbar_sfc4_in_port: port@18 { 1322 reg = <0x18>; 1323 1324 xbar_sfc4_in_ep: endpoint { 1325 remote-endpoint = <&sfc4_cif_in_ep>; 1326 }; 1327 }; 1328 1329 port@19 { 1330 reg = <0x19>; 1331 1332 xbar_sfc4_out_ep: endpoint { 1333 remote-endpoint = <&sfc4_cif_out_ep>; 1334 }; 1335 }; 1336 1337 xbar_mvc1_in_port: port@1a { 1338 reg = <0x1a>; 1339 1340 xbar_mvc1_in_ep: endpoint { 1341 remote-endpoint = <&mvc1_cif_in_ep>; 1342 }; 1343 }; 1344 1345 port@1b { 1346 reg = <0x1b>; 1347 1348 xbar_mvc1_out_ep: endpoint { 1349 remote-endpoint = <&mvc1_cif_out_ep>; 1350 }; 1351 }; 1352 1353 xbar_mvc2_in_port: port@1c { 1354 reg = <0x1c>; 1355 1356 xbar_mvc2_in_ep: endpoint { 1357 remote-endpoint = <&mvc2_cif_in_ep>; 1358 }; 1359 }; 1360 1361 port@1d { 1362 reg = <0x1d>; 1363 1364 xbar_mvc2_out_ep: endpoint { 1365 remote-endpoint = <&mvc2_cif_out_ep>; 1366 }; 1367 }; 1368 1369 xbar_amx1_in1_port: port@1e { 1370 reg = <0x1e>; 1371 1372 xbar_amx1_in1_ep: endpoint { 1373 remote-endpoint = <&amx1_in1_ep>; 1374 }; 1375 }; 1376 1377 xbar_amx1_in2_port: port@1f { 1378 reg = <0x1f>; 1379 1380 xbar_amx1_in2_ep: endpoint { 1381 remote-endpoint = <&amx1_in2_ep>; 1382 }; 1383 }; 1384 1385 xbar_amx1_in3_port: port@20 { 1386 reg = <0x20>; 1387 1388 xbar_amx1_in3_ep: endpoint { 1389 remote-endpoint = <&amx1_in3_ep>; 1390 }; 1391 }; 1392 1393 xbar_amx1_in4_port: port@21 { 1394 reg = <0x21>; 1395 1396 xbar_amx1_in4_ep: endpoint { 1397 remote-endpoint = <&amx1_in4_ep>; 1398 }; 1399 }; 1400 1401 port@22 { 1402 reg = <0x22>; 1403 1404 xbar_amx1_out_ep: endpoint { 1405 remote-endpoint = <&amx1_out_ep>; 1406 }; 1407 }; 1408 1409 xbar_amx2_in1_port: port@23 { 1410 reg = <0x23>; 1411 1412 xbar_amx2_in1_ep: endpoint { 1413 remote-endpoint = <&amx2_in1_ep>; 1414 }; 1415 }; 1416 1417 xbar_amx2_in2_port: port@24 { 1418 reg = <0x24>; 1419 1420 xbar_amx2_in2_ep: endpoint { 1421 remote-endpoint = <&amx2_in2_ep>; 1422 }; 1423 }; 1424 1425 xbar_amx2_in3_port: port@25 { 1426 reg = <0x25>; 1427 1428 xbar_amx2_in3_ep: endpoint { 1429 remote-endpoint = <&amx2_in3_ep>; 1430 }; 1431 }; 1432 1433 xbar_amx2_in4_port: port@26 { 1434 reg = <0x26>; 1435 1436 xbar_amx2_in4_ep: endpoint { 1437 remote-endpoint = <&amx2_in4_ep>; 1438 }; 1439 }; 1440 1441 port@27 { 1442 reg = <0x27>; 1443 1444 xbar_amx2_out_ep: endpoint { 1445 remote-endpoint = <&amx2_out_ep>; 1446 }; 1447 }; 1448 1449 xbar_adx1_in_port: port@28 { 1450 reg = <0x28>; 1451 1452 xbar_adx1_in_ep: endpoint { 1453 remote-endpoint = <&adx1_in_ep>; 1454 }; 1455 }; 1456 1457 port@29 { 1458 reg = <0x29>; 1459 1460 xbar_adx1_out1_ep: endpoint { 1461 remote-endpoint = <&adx1_out1_ep>; 1462 }; 1463 }; 1464 1465 port@2a { 1466 reg = <0x2a>; 1467 1468 xbar_adx1_out2_ep: endpoint { 1469 remote-endpoint = <&adx1_out2_ep>; 1470 }; 1471 }; 1472 1473 port@2b { 1474 reg = <0x2b>; 1475 1476 xbar_adx1_out3_ep: endpoint { 1477 remote-endpoint = <&adx1_out3_ep>; 1478 }; 1479 }; 1480 1481 port@2c { 1482 reg = <0x2c>; 1483 1484 xbar_adx1_out4_ep: endpoint { 1485 remote-endpoint = <&adx1_out4_ep>; 1486 }; 1487 }; 1488 1489 xbar_adx2_in_port: port@2d { 1490 reg = <0x2d>; 1491 1492 xbar_adx2_in_ep: endpoint { 1493 remote-endpoint = <&adx2_in_ep>; 1494 }; 1495 }; 1496 1497 port@2e { 1498 reg = <0x2e>; 1499 1500 xbar_adx2_out1_ep: endpoint { 1501 remote-endpoint = <&adx2_out1_ep>; 1502 }; 1503 }; 1504 1505 port@2f { 1506 reg = <0x2f>; 1507 1508 xbar_adx2_out2_ep: endpoint { 1509 remote-endpoint = <&adx2_out2_ep>; 1510 }; 1511 }; 1512 1513 port@30 { 1514 reg = <0x30>; 1515 1516 xbar_adx2_out3_ep: endpoint { 1517 remote-endpoint = <&adx2_out3_ep>; 1518 }; 1519 }; 1520 1521 port@31 { 1522 reg = <0x31>; 1523 1524 xbar_adx2_out4_ep: endpoint { 1525 remote-endpoint = <&adx2_out4_ep>; 1526 }; 1527 }; 1528 1529 xbar_mixer_in1_port: port@32 { 1530 reg = <0x32>; 1531 1532 xbar_mixer_in1_ep: endpoint { 1533 remote-endpoint = <&mixer_in1_ep>; 1534 }; 1535 }; 1536 1537 xbar_mixer_in2_port: port@33 { 1538 reg = <0x33>; 1539 1540 xbar_mixer_in2_ep: endpoint { 1541 remote-endpoint = <&mixer_in2_ep>; 1542 }; 1543 }; 1544 1545 xbar_mixer_in3_port: port@34 { 1546 reg = <0x34>; 1547 1548 xbar_mixer_in3_ep: endpoint { 1549 remote-endpoint = <&mixer_in3_ep>; 1550 }; 1551 }; 1552 1553 xbar_mixer_in4_port: port@35 { 1554 reg = <0x35>; 1555 1556 xbar_mixer_in4_ep: endpoint { 1557 remote-endpoint = <&mixer_in4_ep>; 1558 }; 1559 }; 1560 1561 xbar_mixer_in5_port: port@36 { 1562 reg = <0x36>; 1563 1564 xbar_mixer_in5_ep: endpoint { 1565 remote-endpoint = <&mixer_in5_ep>; 1566 }; 1567 }; 1568 1569 xbar_mixer_in6_port: port@37 { 1570 reg = <0x37>; 1571 1572 xbar_mixer_in6_ep: endpoint { 1573 remote-endpoint = <&mixer_in6_ep>; 1574 }; 1575 }; 1576 1577 xbar_mixer_in7_port: port@38 { 1578 reg = <0x38>; 1579 1580 xbar_mixer_in7_ep: endpoint { 1581 remote-endpoint = <&mixer_in7_ep>; 1582 }; 1583 }; 1584 1585 xbar_mixer_in8_port: port@39 { 1586 reg = <0x39>; 1587 1588 xbar_mixer_in8_ep: endpoint { 1589 remote-endpoint = <&mixer_in8_ep>; 1590 }; 1591 }; 1592 1593 xbar_mixer_in9_port: port@3a { 1594 reg = <0x3a>; 1595 1596 xbar_mixer_in9_ep: endpoint { 1597 remote-endpoint = <&mixer_in9_ep>; 1598 }; 1599 }; 1600 1601 xbar_mixer_in10_port: port@3b { 1602 reg = <0x3b>; 1603 1604 xbar_mixer_in10_ep: endpoint { 1605 remote-endpoint = <&mixer_in10_ep>; 1606 }; 1607 }; 1608 1609 port@3c { 1610 reg = <0x3c>; 1611 1612 xbar_mixer_out1_ep: endpoint { 1613 remote-endpoint = <&mixer_out1_ep>; 1614 }; 1615 }; 1616 1617 port@3d { 1618 reg = <0x3d>; 1619 1620 xbar_mixer_out2_ep: endpoint { 1621 remote-endpoint = <&mixer_out2_ep>; 1622 }; 1623 }; 1624 1625 port@3e { 1626 reg = <0x3e>; 1627 1628 xbar_mixer_out3_ep: endpoint { 1629 remote-endpoint = <&mixer_out3_ep>; 1630 }; 1631 }; 1632 1633 port@3f { 1634 reg = <0x3f>; 1635 1636 xbar_mixer_out4_ep: endpoint { 1637 remote-endpoint = <&mixer_out4_ep>; 1638 }; 1639 }; 1640 1641 port@40 { 1642 reg = <0x40>; 1643 1644 xbar_mixer_out5_ep: endpoint { 1645 remote-endpoint = <&mixer_out5_ep>; 1646 }; 1647 }; 1648 1649 xbar_ope1_in_port: port@41 { 1650 reg = <0x41>; 1651 1652 xbar_ope1_in_ep: endpoint { 1653 remote-endpoint = <&ope1_cif_in_ep>; 1654 }; 1655 }; 1656 1657 port@42 { 1658 reg = <0x42>; 1659 1660 xbar_ope1_out_ep: endpoint { 1661 remote-endpoint = <&ope1_cif_out_ep>; 1662 }; 1663 }; 1664 1665 xbar_ope2_in_port: port@43 { 1666 reg = <0x43>; 1667 1668 xbar_ope2_in_ep: endpoint { 1669 remote-endpoint = <&ope2_cif_in_ep>; 1670 }; 1671 }; 1672 1673 port@44 { 1674 reg = <0x44>; 1675 1676 xbar_ope2_out_ep: endpoint { 1677 remote-endpoint = <&ope2_cif_out_ep>; 1678 }; 1679 }; 1680 }; 1681 }; 1682 1683 dma-controller@702e2000 { 1684 status = "okay"; 1685 }; 1686 1687 interrupt-controller@702f9000 { 1688 status = "okay"; 1689 }; 1690 }; 1691 1692 spi@70410000 { 1693 status = "okay"; 1694 1695 flash@0 { 1696 compatible = "jedec,spi-nor"; 1697 reg = <0>; 1698 spi-max-frequency = <104000000>; 1699 spi-tx-bus-width = <2>; 1700 spi-rx-bus-width = <2>; 1701 }; 1702 }; 1703 1704 clk32k_in: clock-32k { 1705 compatible = "fixed-clock"; 1706 clock-frequency = <32768>; 1707 #clock-cells = <0>; 1708 }; 1709 1710 cpus { 1711 cpu@0 { 1712 enable-method = "psci"; 1713 }; 1714 1715 cpu@1 { 1716 enable-method = "psci"; 1717 }; 1718 1719 cpu@2 { 1720 enable-method = "psci"; 1721 }; 1722 1723 cpu@3 { 1724 enable-method = "psci"; 1725 }; 1726 1727 idle-states { 1728 cpu-sleep { 1729 status = "okay"; 1730 }; 1731 }; 1732 }; 1733 1734 gpio-keys { 1735 compatible = "gpio-keys"; 1736 1737 key-force-recovery { 1738 label = "Force Recovery"; 1739 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1740 linux,input-type = <EV_KEY>; 1741 linux,code = <BTN_1>; 1742 debounce-interval = <30>; 1743 }; 1744 1745 key-power { 1746 label = "Power"; 1747 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1748 linux,input-type = <EV_KEY>; 1749 linux,code = <KEY_POWER>; 1750 debounce-interval = <30>; 1751 wakeup-event-action = <EV_ACT_ASSERTED>; 1752 wakeup-source; 1753 }; 1754 }; 1755 1756 psci { 1757 compatible = "arm,psci-1.0"; 1758 method = "smc"; 1759 }; 1760 1761 fan: pwm-fan { 1762 compatible = "pwm-fan"; 1763 pwms = <&pwm 3 45334>; 1764 1765 cooling-levels = <0 64 128 255>; 1766 #cooling-cells = <2>; 1767 }; 1768 1769 vdd_5v0_sys: regulator-vdd-5v0-sys { 1770 compatible = "regulator-fixed"; 1771 1772 regulator-name = "VDD_5V0_SYS"; 1773 regulator-min-microvolt = <5000000>; 1774 regulator-max-microvolt = <5000000>; 1775 regulator-always-on; 1776 regulator-boot-on; 1777 }; 1778 1779 vdd_3v3_sys: regulator-vdd-3v3-sys { 1780 compatible = "regulator-fixed"; 1781 1782 regulator-name = "VDD_3V3_SYS"; 1783 regulator-min-microvolt = <3300000>; 1784 regulator-max-microvolt = <3300000>; 1785 regulator-enable-ramp-delay = <240>; 1786 regulator-always-on; 1787 regulator-boot-on; 1788 1789 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1790 enable-active-high; 1791 1792 vin-supply = <&vdd_5v0_sys>; 1793 }; 1794 1795 vdd_3v3_sd: regulator-vdd-3v3-sd { 1796 compatible = "regulator-fixed"; 1797 1798 regulator-name = "VDD_3V3_SD"; 1799 regulator-min-microvolt = <3300000>; 1800 regulator-max-microvolt = <3300000>; 1801 1802 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1803 enable-active-high; 1804 1805 vin-supply = <&vdd_3v3_sys>; 1806 }; 1807 1808 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1809 compatible = "regulator-fixed"; 1810 1811 regulator-name = "VDD_HDMI_5V0"; 1812 regulator-min-microvolt = <5000000>; 1813 regulator-max-microvolt = <5000000>; 1814 1815 vin-supply = <&vdd_5v0_sys>; 1816 }; 1817 1818 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1819 compatible = "regulator-fixed"; 1820 1821 regulator-name = "VDD_HUB_3V3"; 1822 regulator-min-microvolt = <3300000>; 1823 regulator-max-microvolt = <3300000>; 1824 1825 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1826 enable-active-high; 1827 1828 vin-supply = <&vdd_5v0_sys>; 1829 }; 1830 1831 vdd_cpu: regulator-vdd-cpu { 1832 compatible = "regulator-fixed"; 1833 1834 regulator-name = "VDD_CPU"; 1835 regulator-min-microvolt = <5000000>; 1836 regulator-max-microvolt = <5000000>; 1837 regulator-always-on; 1838 regulator-boot-on; 1839 1840 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1841 enable-active-high; 1842 1843 vin-supply = <&vdd_5v0_sys>; 1844 }; 1845 1846 vdd_gpu: regulator-vdd-gpu { 1847 compatible = "pwm-regulator"; 1848 pwms = <&pwm 1 8000>; 1849 1850 regulator-name = "VDD_GPU"; 1851 regulator-min-microvolt = <710000>; 1852 regulator-max-microvolt = <1320000>; 1853 regulator-ramp-delay = <80>; 1854 regulator-enable-ramp-delay = <2000>; 1855 regulator-settling-time-us = <160>; 1856 1857 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1858 vin-supply = <&vdd_5v0_sys>; 1859 }; 1860 1861 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { 1862 compatible = "regulator-fixed"; 1863 1864 regulator-name = "AVDD_IO_EDP_1V05"; 1865 regulator-min-microvolt = <1050000>; 1866 regulator-max-microvolt = <1050000>; 1867 1868 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1869 enable-active-high; 1870 1871 vin-supply = <&avdd_1v05_pll>; 1872 }; 1873 1874 vdd_5v0_usb: regulator-vdd-5v-usb { 1875 compatible = "regulator-fixed"; 1876 1877 regulator-name = "VDD_5V_USB"; 1878 regulator-min-microvolt = <50000000>; 1879 regulator-max-microvolt = <50000000>; 1880 1881 vin-supply = <&vdd_5v0_sys>; 1882 }; 1883 1884 sound { 1885 compatible = "nvidia,tegra210-audio-graph-card"; 1886 status = "okay"; 1887 1888 dais = /* FE */ 1889 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1890 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1891 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1892 <&admaif10_port>, 1893 /* Router */ 1894 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1895 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1896 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1897 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1898 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1899 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1900 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1901 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1902 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1903 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1904 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1905 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1906 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1907 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1908 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1909 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, 1910 /* HW accelerators */ 1911 <&sfc1_out_port>, <&sfc2_out_port>, 1912 <&sfc3_out_port>, <&sfc4_out_port>, 1913 <&mvc1_out_port>, <&mvc2_out_port>, 1914 <&amx1_out_port>, <&amx2_out_port>, 1915 <&adx1_out1_port>, <&adx1_out2_port>, 1916 <&adx1_out3_port>, <&adx1_out4_port>, 1917 <&adx2_out1_port>, <&adx2_out2_port>, 1918 <&adx2_out3_port>, <&adx2_out4_port>, 1919 <&mixer_out1_port>, <&mixer_out2_port>, 1920 <&mixer_out3_port>, <&mixer_out4_port>, 1921 <&mixer_out5_port>, 1922 <&ope1_out_port>, <&ope2_out_port>, 1923 /* I/O DAP Ports */ 1924 <&i2s3_port>, <&i2s4_port>, 1925 <&dmic1_port>, <&dmic2_port>; 1926 1927 label = "NVIDIA Jetson Nano APE"; 1928 }; 1929 1930 thermal-zones { 1931 cpu-thermal { 1932 trips { 1933 cpu_trip_critical: critical { 1934 temperature = <96500>; 1935 hysteresis = <0>; 1936 type = "critical"; 1937 }; 1938 1939 cpu_trip_hot: hot { 1940 temperature = <70000>; 1941 hysteresis = <2000>; 1942 type = "hot"; 1943 }; 1944 1945 cpu_trip_active: active { 1946 temperature = <50000>; 1947 hysteresis = <2000>; 1948 type = "active"; 1949 }; 1950 1951 cpu_trip_passive: passive { 1952 temperature = <30000>; 1953 hysteresis = <2000>; 1954 type = "passive"; 1955 }; 1956 }; 1957 1958 cooling-maps { 1959 cpu-critical { 1960 cooling-device = <&fan 3 3>; 1961 trip = <&cpu_trip_critical>; 1962 }; 1963 1964 cpu-hot { 1965 cooling-device = <&fan 2 2>; 1966 trip = <&cpu_trip_hot>; 1967 }; 1968 1969 cpu-active { 1970 cooling-device = <&fan 1 1>; 1971 trip = <&cpu_trip_active>; 1972 }; 1973 1974 cpu-passive { 1975 cooling-device = <&fan 0 0>; 1976 trip = <&cpu_trip_passive>; 1977 }; 1978 }; 1979 }; 1980 }; 1981}; 1982