1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
15#include "mt8365.dtsi"
16#include "mt6357.dtsi"
17
18/ {
19	model = "MediaTek MT8365 Open Platform EVK";
20	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
21
22	aliases {
23		serial0 = &uart0;
24		ethernet = &ethernet;
25	};
26
27	chosen {
28		stdout-path = "serial0:921600n8";
29	};
30
31	connector {
32		compatible = "hdmi-connector";
33		label = "hdmi";
34		type = "d";
35
36		port {
37			#address-cells = <1>;
38			#size-cells = <0>;
39			hdmi_connector_in: endpoint@0 {
40				reg = <0>;
41				remote-endpoint = <&hdmi_connector_out>;
42			};
43		};
44	};
45
46	firmware {
47		optee {
48			compatible = "linaro,optee-tz";
49			method = "smc";
50		};
51	};
52
53	gpio-keys {
54		compatible = "gpio-keys";
55		pinctrl-names = "default";
56		pinctrl-0 = <&gpio_keys>;
57
58		key-volume-up {
59			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
60			label = "volume_up";
61			linux,code = <KEY_VOLUMEUP>;
62			wakeup-source;
63			debounce-interval = <15>;
64		};
65	};
66
67	memory@40000000 {
68		device_type = "memory";
69		reg = <0 0x40000000 0 0xc0000000>;
70	};
71
72	usb_otg_vbus: regulator-0 {
73		compatible = "regulator-fixed";
74		regulator-name = "otg_vbus";
75		regulator-min-microvolt = <5000000>;
76		regulator-max-microvolt = <5000000>;
77		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
78		enable-active-high;
79	};
80
81	reserved-memory {
82		#address-cells = <2>;
83		#size-cells = <2>;
84		ranges;
85
86		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
87		bl31_secmon_reserved: secmon@43000000 {
88			no-map;
89			reg = <0 0x43000000 0 0x30000>;
90		};
91
92		/* 12 MiB reserved for OP-TEE (BL32)
93		 * +-----------------------+ 0x43e0_0000
94		 * |      SHMEM 2MiB       |
95		 * +-----------------------+ 0x43c0_0000
96		 * |        | TA_RAM  8MiB |
97		 * + TZDRAM +--------------+ 0x4340_0000
98		 * |        | TEE_RAM 2MiB |
99		 * +-----------------------+ 0x4320_0000
100		 */
101		optee_reserved: optee@43200000 {
102			no-map;
103			reg = <0 0x43200000 0 0x00c00000>;
104		};
105	};
106
107	sound: sound {
108		compatible = "mediatek,mt8365-mt6357";
109		pinctrl-names = "default",
110				"dmic",
111				"miso_off",
112				"miso_on",
113				"mosi_off",
114				"mosi_on";
115		pinctrl-0 = <&aud_default_pins>;
116		pinctrl-1 = <&aud_dmic_pins>;
117		pinctrl-2 = <&aud_miso_off_pins>;
118		pinctrl-3 = <&aud_miso_on_pins>;
119		pinctrl-4 = <&aud_mosi_off_pins>;
120		pinctrl-5 = <&aud_mosi_on_pins>;
121		mediatek,platform = <&afe>;
122	};
123
124	vsys_lcm_reg: regulator-vsys-lcm {
125		compatible = "regulator-fixed";
126		enable-active-high;
127		gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
128		regulator-max-microvolt = <5000000>;
129		regulator-min-microvolt = <5000000>;
130		regulator-name = "vsys_lcm";
131	};
132
133};
134
135&afe {
136	mediatek,dmic-mode = <1>;
137	status = "okay";
138};
139
140&cpu0 {
141	proc-supply = <&mt6357_vproc_reg>;
142	sram-supply = <&mt6357_vsram_proc_reg>;
143};
144
145&cpu1 {
146	proc-supply = <&mt6357_vproc_reg>;
147	sram-supply = <&mt6357_vsram_proc_reg>;
148};
149
150&cpu2 {
151	proc-supply = <&mt6357_vproc_reg>;
152	sram-supply = <&mt6357_vsram_proc_reg>;
153};
154
155&cpu3 {
156	proc-supply = <&mt6357_vproc_reg>;
157	sram-supply = <&mt6357_vsram_proc_reg>;
158};
159
160&dither0_out {
161	remote-endpoint = <&dsi0_in>;
162};
163
164&dpi0 {
165	pinctrl-0 = <&dpi_default_pins>;
166	pinctrl-1 = <&dpi_idle_pins>;
167	pinctrl-names = "default", "sleep";
168	/*
169	 * Ethernet and HDMI (DPI0) are sharing pins.
170	 * Only one can be enabled at a time and require the physical switch
171	 * SW2101 to be set on LAN position
172	 */
173	status = "disabled";
174
175	ports {
176		#address-cells = <1>;
177		#size-cells = <0>;
178
179		port@0 {
180			#address-cells = <1>;
181			#size-cells = <0>;
182			reg = <0>;
183			dpi0_in: endpoint@1 {
184				reg = <1>;
185				remote-endpoint = <&rdma1_out>;
186			};
187		};
188
189		port@1 {
190			#address-cells = <1>;
191			#size-cells = <0>;
192			reg = <1>;
193			dpi0_out: endpoint@1 {
194				reg = <1>;
195				remote-endpoint = <&it66121_in>;
196			};
197		};
198	};
199};
200
201&dsi0 {
202	#address-cells = <1>;
203	#size-cells = <0>;
204	status = "okay";
205
206	panel@0 {
207		compatible = "startek,kd070fhfid015";
208		reg = <0>;
209		enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
210		reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
211		iovcc-supply = <&mt6357_vsim1_reg>;
212		power-supply = <&vsys_lcm_reg>;
213
214		port {
215			#address-cells = <1>;
216			#size-cells = <0>;
217			panel_in: endpoint@0 {
218				reg = <0>;
219				remote-endpoint = <&dsi0_out>;
220			};
221		};
222	};
223	ports {
224		#address-cells = <1>;
225		#size-cells = <0>;
226
227		port@0 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0>;
231			dsi0_in: endpoint@0 {
232				reg = <0>;
233				remote-endpoint = <&dither0_out>;
234			};
235		};
236
237		port@1 {
238			#address-cells = <1>;
239			#size-cells = <0>;
240			reg = <1>;
241			dsi0_out: endpoint@0 {
242				reg = <0>;
243				remote-endpoint = <&panel_in>;
244			};
245		};
246	};
247};
248
249&ethernet {
250	pinctrl-0 = <&ethernet_pins>;
251	pinctrl-names = "default";
252	phy-handle = <&eth_phy>;
253	phy-mode = "rmii";
254	/*
255	 * Ethernet and HDMI (DPI0) are sharing pins.
256	 * Only one can be enabled at a time and require the physical switch
257	 * SW2101 to be set on LAN position
258	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
259	 */
260	status = "disabled";
261
262	mdio {
263		#address-cells = <1>;
264		#size-cells = <0>;
265
266		eth_phy: ethernet-phy@0 {
267			reg = <0>;
268		};
269	};
270};
271
272&i2c0 {
273	clock-frequency = <100000>;
274	pinctrl-0 = <&i2c0_pins>;
275	pinctrl-names = "default";
276	status = "okay";
277};
278
279&i2c1 {
280	#address-cells = <1>;
281	#size-cells = <0>;
282	clock-div = <2>;
283	clock-frequency = <100000>;
284	pinctrl-0 = <&i2c1_pins>;
285	pinctrl-names = "default";
286	status = "okay";
287
288	it66121_hdmi: hdmi@4c {
289		compatible = "ite,it66121";
290		reg = <0x4c>;
291		#sound-dai-cells = <0>;
292		interrupt-parent = <&pio>;
293		interrupts = <68 IRQ_TYPE_LEVEL_LOW>;
294		pinctrl-0 = <&ite_pins>;
295		pinctrl-names = "default";
296		reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
297		vcn18-supply = <&mt6357_vsim2_reg>;
298		vcn33-supply = <&mt6357_vibr_reg>;
299		vrf12-supply = <&mt6357_vrf12_reg>;
300
301		ports {
302			#address-cells = <1>;
303			#size-cells = <0>;
304
305			port@0 {
306				#address-cells = <1>;
307				#size-cells = <0>;
308				reg = <0>;
309				it66121_in: endpoint@0 {
310					reg = <0>;
311					bus-width = <12>;
312					remote-endpoint = <&dpi0_out>;
313				};
314			};
315
316			port@1 {
317				#address-cells = <1>;
318				#size-cells = <0>;
319				reg = <1>;
320				hdmi_connector_out: endpoint@0 {
321					reg = <0>;
322					remote-endpoint = <&hdmi_connector_in>;
323				};
324			};
325		};
326	};
327};
328
329&mmc0 {
330	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
331	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
332	bus-width = <8>;
333	cap-mmc-highspeed;
334	cap-mmc-hw-reset;
335	hs400-ds-delay = <0x12012>;
336	max-frequency = <200000000>;
337	mmc-hs200-1_8v;
338	mmc-hs400-1_8v;
339	no-sd;
340	no-sdio;
341	non-removable;
342	pinctrl-0 = <&mmc0_default_pins>;
343	pinctrl-1 = <&mmc0_uhs_pins>;
344	pinctrl-names = "default", "state_uhs";
345	vmmc-supply = <&mt6357_vemc_reg>;
346	vqmmc-supply = <&mt6357_vio18_reg>;
347	status = "okay";
348};
349
350&mmc1 {
351	bus-width = <4>;
352	cap-sd-highspeed;
353	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
354	max-frequency = <200000000>;
355	pinctrl-0 = <&mmc1_default_pins>;
356	pinctrl-1 = <&mmc1_uhs_pins>;
357	pinctrl-names = "default", "state_uhs";
358	sd-uhs-sdr104;
359	sd-uhs-sdr50;
360	vmmc-supply = <&mt6357_vmch_reg>;
361	vqmmc-supply = <&mt6357_vmc_reg>;
362	status = "okay";
363};
364
365&mt6357_pmic {
366	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
367	interrupt-controller;
368	#interrupt-cells = <2>;
369	mediatek,micbias0-microvolt = <1900000>;
370	mediatek,micbias1-microvolt = <1700000>;
371};
372
373&mt6357_vsim1_reg {
374	regulator-min-microvolt = <1800000>;
375	regulator-max-microvolt = <1800000>;
376};
377
378&pio {
379	aud_default_pins: audiodefault-pins {
380		clk-dat-pins {
381			pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
382				 <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
383				 <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
384				 <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
385		};
386	};
387
388	aud_dmic_pins: audiodmic-pins {
389		clk-dat-pins {
390			pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
391				 <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
392				 <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
393		};
394	};
395
396	aud_miso_off_pins: misooff-pins {
397		clk-dat-pins {
398			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
399				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
400				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
401				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
402			input-enable;
403			bias-pull-down;
404			drive-strength = <2>;
405		};
406	};
407
408	aud_miso_on_pins: misoon-pins {
409		clk-dat-pins {
410			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
411				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
412				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
413				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
414			drive-strength = <6>;
415		};
416	};
417
418	aud_mosi_off_pins: mosioff-pins {
419		clk-dat-pins {
420			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
421				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
422				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
423				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
424			input-enable;
425			bias-pull-down;
426			drive-strength = <2>;
427		};
428	};
429
430	aud_mosi_on_pins: mosion-pins {
431		clk-dat-pins {
432			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
433				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
434				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
435				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
436			drive-strength = <6>;
437		};
438	};
439
440	dpi_default_pins: dpi-default-pins {
441		pins {
442			pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
443				 <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
444				 <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
445				 <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
446				 <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
447				 <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
448				 <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
449				 <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
450				 <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
451				 <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
452				 <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
453				 <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
454				 <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
455				 <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
456				 <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
457				 <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
458			drive-strength = <4>;
459		};
460	};
461
462	dpi_idle_pins: dpi-idle-pins {
463		pins {
464			pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
465				 <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
466				 <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
467				 <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
468				 <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
469				 <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
470				 <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
471				 <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
472				 <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
473				 <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
474				 <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
475				 <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
476				 <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
477				 <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
478				 <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
479				 <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
480		};
481	};
482
483	ethernet_pins: ethernet-pins {
484		phy_reset_pins {
485			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
486		};
487
488		rmii_pins {
489			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
490				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
491				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
492				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
493				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
494				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
495				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
496				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
497				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
498				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
499				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
500				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
501				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
502				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
503				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
504				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
505		};
506	};
507
508	gpio_keys: gpio-keys-pins {
509		pins {
510			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
511			bias-pull-up;
512			input-enable;
513		};
514	};
515
516	i2c0_pins: i2c0-pins {
517		pins {
518			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
519				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
520			bias-pull-up;
521		};
522	};
523
524	i2c1_pins: i2c1-pins {
525		pins {
526			pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
527				 <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
528			bias-pull-up;
529		};
530	};
531
532	ite_pins: ite-pins {
533		irq_ite_pins {
534			pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
535			input-enable;
536			bias-pull-up;
537		};
538
539		pwr_pins {
540			pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
541				 <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
542			output-high;
543		};
544
545		rst_ite_pins {
546			pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
547			output-high;
548		};
549	};
550
551	mmc0_default_pins: mmc0-default-pins {
552		clk-pins {
553			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
554			bias-pull-down;
555		};
556
557		cmd-dat-pins {
558			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
559				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
560				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
561				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
562				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
563				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
564				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
565				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
566				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
567			input-enable;
568			bias-pull-up;
569		};
570
571		rst-pins {
572			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
573			bias-pull-up;
574		};
575	};
576
577	mmc0_uhs_pins: mmc0-uhs-pins {
578		clk-pins {
579			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
580			drive-strength = <MTK_DRIVE_10mA>;
581			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
582		};
583
584		cmd-dat-pins {
585			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
586				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
587				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
588				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
589				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
590				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
591				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
592				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
593				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
594			input-enable;
595			drive-strength = <MTK_DRIVE_10mA>;
596			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
597		};
598
599		ds-pins {
600			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
601			drive-strength = <MTK_DRIVE_10mA>;
602			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
603		};
604
605		rst-pins {
606			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
607			drive-strength = <MTK_DRIVE_10mA>;
608			bias-pull-up;
609		};
610	};
611
612	mmc1_default_pins: mmc1-default-pins {
613		cd-pins {
614			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
615			bias-pull-up;
616		};
617
618		clk-pins {
619			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
620			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
621		};
622
623		cmd-dat-pins {
624			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
625				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
626				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
627				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
628				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
629			input-enable;
630			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
631		};
632	};
633
634	mmc1_uhs_pins: mmc1-uhs-pins {
635		clk-pins {
636			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
637			drive-strength = <8>;
638			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
639		};
640
641		cmd-dat-pins {
642			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
643				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
644				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
645				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
646				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
647			input-enable;
648			drive-strength = <6>;
649			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
650		};
651	};
652
653	uart0_pins: uart0-pins {
654		pins {
655			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
656				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
657		};
658	};
659
660	uart1_pins: uart1-pins {
661		pins {
662			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
663				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
664		};
665	};
666
667	uart2_pins: uart2-pins {
668		pins {
669			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
670				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
671		};
672	};
673
674	usb_pins: usb-pins {
675		id-pins {
676			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
677			input-enable;
678			bias-pull-up;
679		};
680
681		usb0-vbus-pins {
682			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
683			output-high;
684		};
685
686		usb1-vbus-pins {
687			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
688			output-high;
689		};
690	};
691
692	pwm_pins: pwm-pins {
693		pins {
694			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
695				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
696		};
697	};
698};
699
700&pwm {
701	pinctrl-0 = <&pwm_pins>;
702	pinctrl-names = "default";
703	status = "okay";
704};
705
706&rdma1_out {
707	remote-endpoint = <&dpi0_in>;
708};
709
710&ssusb {
711	dr_mode = "otg";
712	maximum-speed = "high-speed";
713	pinctrl-0 = <&usb_pins>;
714	pinctrl-names = "default";
715	usb-role-switch;
716	vusb33-supply = <&mt6357_vusb33_reg>;
717	status = "okay";
718
719	connector {
720		compatible = "gpio-usb-b-connector", "usb-b-connector";
721		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
722		type = "micro";
723		vbus-supply = <&usb_otg_vbus>;
724	};
725};
726
727&usb_host {
728	vusb33-supply = <&mt6357_vusb33_reg>;
729	status = "okay";
730};
731
732&uart0 {
733	pinctrl-0 = <&uart0_pins>;
734	pinctrl-names = "default";
735	status = "okay";
736};
737
738&uart1 {
739	pinctrl-0 = <&uart1_pins>;
740	pinctrl-names = "default";
741	status = "okay";
742};
743
744&uart2 {
745	pinctrl-0 = <&uart2_pins>;
746	pinctrl-names = "default";
747	status = "okay";
748};
749