1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx95-clock.h" 13#include "imx95-pinfunc.h" 14#include "imx95-power.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 idle-states { 26 entry-method = "psci"; 27 28 cpu_pd_wait: cpu-pd-wait { 29 compatible = "arm,idle-state"; 30 arm,psci-suspend-param = <0x0010033>; 31 local-timer-stop; 32 entry-latency-us = <10000>; 33 exit-latency-us = <7000>; 34 min-residency-us = <27000>; 35 wakeup-latency-us = <15000>; 36 }; 37 }; 38 39 A55_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a55"; 42 reg = <0x0>; 43 enable-method = "psci"; 44 #cooling-cells = <2>; 45 cpu-idle-states = <&cpu_pd_wait>; 46 power-domains = <&scmi_perf IMX95_PERF_A55>; 47 power-domain-names = "perf"; 48 i-cache-size = <32768>; 49 i-cache-line-size = <64>; 50 i-cache-sets = <128>; 51 d-cache-size = <32768>; 52 d-cache-line-size = <64>; 53 d-cache-sets = <128>; 54 next-level-cache = <&l2_cache_l0>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 cpu-idle-states = <&cpu_pd_wait>; 64 power-domains = <&scmi_perf IMX95_PERF_A55>; 65 power-domain-names = "perf"; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l1>; 73 }; 74 75 A55_2: cpu@200 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x200>; 79 enable-method = "psci"; 80 #cooling-cells = <2>; 81 cpu-idle-states = <&cpu_pd_wait>; 82 power-domains = <&scmi_perf IMX95_PERF_A55>; 83 power-domain-names = "perf"; 84 i-cache-size = <32768>; 85 i-cache-line-size = <64>; 86 i-cache-sets = <128>; 87 d-cache-size = <32768>; 88 d-cache-line-size = <64>; 89 d-cache-sets = <128>; 90 next-level-cache = <&l2_cache_l2>; 91 }; 92 93 A55_3: cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 enable-method = "psci"; 98 #cooling-cells = <2>; 99 cpu-idle-states = <&cpu_pd_wait>; 100 power-domains = <&scmi_perf IMX95_PERF_A55>; 101 power-domain-names = "perf"; 102 i-cache-size = <32768>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&l2_cache_l3>; 109 }; 110 111 A55_4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x400>; 115 power-domains = <&scmi_perf IMX95_PERF_A55>; 116 power-domain-names = "perf"; 117 enable-method = "psci"; 118 #cooling-cells = <2>; 119 cpu-idle-states = <&cpu_pd_wait>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l4>; 127 }; 128 129 A55_5: cpu@500 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a55"; 132 reg = <0x500>; 133 power-domains = <&scmi_perf IMX95_PERF_A55>; 134 power-domain-names = "perf"; 135 enable-method = "psci"; 136 #cooling-cells = <2>; 137 cpu-idle-states = <&cpu_pd_wait>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l5>; 145 }; 146 147 l2_cache_l0: l2-cache-l0 { 148 compatible = "cache"; 149 cache-size = <65536>; 150 cache-line-size = <64>; 151 cache-sets = <256>; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_cache>; 155 }; 156 157 l2_cache_l1: l2-cache-l1 { 158 compatible = "cache"; 159 cache-size = <65536>; 160 cache-line-size = <64>; 161 cache-sets = <256>; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_cache>; 165 }; 166 167 l2_cache_l2: l2-cache-l2 { 168 compatible = "cache"; 169 cache-size = <65536>; 170 cache-line-size = <64>; 171 cache-sets = <256>; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_cache>; 175 }; 176 177 l2_cache_l3: l2-cache-l3 { 178 compatible = "cache"; 179 cache-size = <65536>; 180 cache-line-size = <64>; 181 cache-sets = <256>; 182 cache-level = <2>; 183 cache-unified; 184 next-level-cache = <&l3_cache>; 185 }; 186 187 l2_cache_l4: l2-cache-l4 { 188 compatible = "cache"; 189 cache-size = <65536>; 190 cache-line-size = <64>; 191 cache-sets = <256>; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&l3_cache>; 195 }; 196 197 l2_cache_l5: l2-cache-l5 { 198 compatible = "cache"; 199 cache-size = <65536>; 200 cache-line-size = <64>; 201 cache-sets = <256>; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&l3_cache>; 205 }; 206 207 l3_cache: l3-cache { 208 compatible = "cache"; 209 cache-size = <524288>; 210 cache-line-size = <64>; 211 cache-sets = <512>; 212 cache-level = <3>; 213 cache-unified; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&A55_0>; 220 }; 221 222 core1 { 223 cpu = <&A55_1>; 224 }; 225 226 core2 { 227 cpu = <&A55_2>; 228 }; 229 230 core3 { 231 cpu = <&A55_3>; 232 }; 233 234 core4 { 235 cpu = <&A55_4>; 236 }; 237 238 core5 { 239 cpu = <&A55_5>; 240 }; 241 }; 242 }; 243 }; 244 245 dummy: clock-dummy { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <0>; 249 clock-output-names = "dummy"; 250 }; 251 252 clk_ext1: clock-ext1 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency = <133000000>; 256 clock-output-names = "clk_ext1"; 257 }; 258 259 sai1_mclk: clock-sai-mclk1 { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 clock-frequency= <0>; 263 clock-output-names = "sai1_mclk"; 264 }; 265 266 sai2_mclk: clock-sai-mclk2 { 267 compatible = "fixed-clock"; 268 #clock-cells = <0>; 269 clock-frequency= <0>; 270 clock-output-names = "sai2_mclk"; 271 }; 272 273 sai3_mclk: clock-sai-mclk3 { 274 compatible = "fixed-clock"; 275 #clock-cells = <0>; 276 clock-frequency= <0>; 277 clock-output-names = "sai3_mclk"; 278 }; 279 280 sai4_mclk: clock-sai-mclk4 { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency= <0>; 284 clock-output-names = "sai4_mclk"; 285 }; 286 287 sai5_mclk: clock-sai-mclk5 { 288 compatible = "fixed-clock"; 289 #clock-cells = <0>; 290 clock-frequency= <0>; 291 clock-output-names = "sai5_mclk"; 292 }; 293 294 clk_sys100m: clock-sys100m { 295 compatible = "fixed-clock"; 296 #clock-cells = <0>; 297 clock-frequency = <100000000>; 298 clock-output-names = "clk_sys100m"; 299 }; 300 301 osc_24m: clock-24m { 302 compatible = "fixed-clock"; 303 #clock-cells = <0>; 304 clock-frequency = <24000000>; 305 clock-output-names = "osc_24m"; 306 }; 307 308 sram1: sram@204c0000 { 309 compatible = "mmio-sram"; 310 reg = <0x0 0x204c0000 0x0 0x18000>; 311 ranges = <0x0 0x0 0x204c0000 0x18000>; 312 #address-cells = <1>; 313 #size-cells = <1>; 314 }; 315 316 firmware { 317 scmi { 318 compatible = "arm,scmi"; 319 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 320 shmem = <&scmi_buf0>, <&scmi_buf1>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 arm,max-rx-timeout-ms = <5000>; 324 325 scmi_devpd: protocol@11 { 326 reg = <0x11>; 327 #power-domain-cells = <1>; 328 }; 329 330 scmi_sys_power: protocol@12 { 331 reg = <0x12>; 332 }; 333 334 scmi_perf: protocol@13 { 335 reg = <0x13>; 336 #power-domain-cells = <1>; 337 }; 338 339 scmi_clk: protocol@14 { 340 reg = <0x14>; 341 #clock-cells = <1>; 342 }; 343 344 scmi_sensor: protocol@15 { 345 reg = <0x15>; 346 #thermal-sensor-cells = <1>; 347 }; 348 349 scmi_iomuxc: protocol@19 { 350 reg = <0x19>; 351 }; 352 353 scmi_bbm: protocol@81 { 354 reg = <0x81>; 355 }; 356 357 scmi_misc: protocol@84 { 358 reg = <0x84>; 359 }; 360 }; 361 }; 362 363 pmu { 364 compatible = "arm,cortex-a55-pmu"; 365 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 366 }; 367 368 thermal_zones: thermal-zones { 369 a55-thermal { 370 polling-delay-passive = <250>; 371 polling-delay = <2000>; 372 thermal-sensors = <&scmi_sensor 1>; 373 374 trips { 375 cpu_alert0: trip0 { 376 temperature = <105000>; 377 hysteresis = <2000>; 378 type = "passive"; 379 }; 380 381 cpu_crit0: trip1 { 382 temperature = <125000>; 383 hysteresis = <2000>; 384 type = "critical"; 385 }; 386 }; 387 388 cooling-maps { 389 map0 { 390 trip = <&cpu_alert0>; 391 cooling-device = 392 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 393 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 394 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 397 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 398 }; 399 }; 400 }; 401 402 ana-thermal { 403 polling-delay-passive = <250>; 404 polling-delay = <2000>; 405 thermal-sensors = <&scmi_sensor 0>; 406 trips { 407 ana_alert: trip0 { 408 temperature = <105000>; 409 hysteresis = <2000>; 410 type = "passive"; 411 }; 412 413 ana_crit0: trip1 { 414 temperature = <125000>; 415 hysteresis = <2000>; 416 type = "critical"; 417 }; 418 }; 419 420 cooling-maps { 421 map0 { 422 trip = <&ana_alert>; 423 cooling-device = 424 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 425 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 426 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 427 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 428 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 429 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 430 }; 431 }; 432 }; 433 }; 434 435 psci { 436 compatible = "arm,psci-1.0"; 437 method = "smc"; 438 }; 439 440 timer { 441 compatible = "arm,armv8-timer"; 442 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 443 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 444 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 445 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 446 clock-frequency = <24000000>; 447 arm,no-tick-in-suspend; 448 interrupt-parent = <&gic>; 449 }; 450 451 gic: interrupt-controller@48000000 { 452 compatible = "arm,gic-v3"; 453 reg = <0 0x48000000 0 0x10000>, 454 <0 0x48060000 0 0xc0000>; 455 #address-cells = <2>; 456 #size-cells = <2>; 457 #interrupt-cells = <3>; 458 interrupt-controller; 459 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-parent = <&gic>; 461 dma-noncoherent; 462 ranges; 463 464 its: msi-controller@48040000 { 465 compatible = "arm,gic-v3-its"; 466 reg = <0 0x48040000 0 0x20000>; 467 msi-controller; 468 #msi-cells = <1>; 469 dma-noncoherent; 470 }; 471 }; 472 473 soc { 474 compatible = "simple-bus"; 475 #address-cells = <2>; 476 #size-cells = <2>; 477 ranges; 478 479 aips2: bus@42000000 { 480 compatible = "fsl,aips-bus", "simple-bus"; 481 reg = <0x0 0x42000000 0x0 0x800000>; 482 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 483 <0x28000000 0x0 0x28000000 0x10000000>; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 487 edma2: dma-controller@42000000 { 488 compatible = "fsl,imx95-edma5"; 489 reg = <0x42000000 0x210000>; 490 #dma-cells = <3>; 491 dma-channels = <64>; 492 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 557 clock-names = "dma"; 558 }; 559 560 edma3: dma-controller@42210000 { 561 compatible = "fsl,imx95-edma5"; 562 reg = <0x42210000 0x210000>; 563 #dma-cells = <3>; 564 dma-channels = <64>; 565 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 630 clock-names = "dma"; 631 }; 632 633 mu7: mailbox@42430000 { 634 compatible = "fsl,imx95-mu"; 635 reg = <0x42430000 0x10000>; 636 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 638 #mbox-cells = <2>; 639 status = "disabled"; 640 }; 641 642 wdog3: watchdog@42490000 { 643 compatible = "fsl,imx93-wdt"; 644 reg = <0x42490000 0x10000>; 645 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 647 timeout-sec = <40>; 648 status = "disabled"; 649 }; 650 651 tpm3: pwm@424e0000 { 652 compatible = "fsl,imx7ulp-pwm"; 653 reg = <0x424e0000 0x1000>; 654 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 655 #pwm-cells = <3>; 656 status = "disabled"; 657 }; 658 659 tpm4: pwm@424f0000 { 660 compatible = "fsl,imx7ulp-pwm"; 661 reg = <0x424f0000 0x1000>; 662 clocks = <&scmi_clk IMX95_CLK_TPM4>; 663 #pwm-cells = <3>; 664 status = "disabled"; 665 }; 666 667 tpm5: pwm@42500000 { 668 compatible = "fsl,imx7ulp-pwm"; 669 reg = <0x42500000 0x1000>; 670 clocks = <&scmi_clk IMX95_CLK_TPM5>; 671 #pwm-cells = <3>; 672 status = "disabled"; 673 }; 674 675 tpm6: pwm@42510000 { 676 compatible = "fsl,imx7ulp-pwm"; 677 reg = <0x42510000 0x1000>; 678 clocks = <&scmi_clk IMX95_CLK_TPM6>; 679 #pwm-cells = <3>; 680 status = "disabled"; 681 }; 682 683 i3c2: i3c@42520000 { 684 compatible = "silvaco,i3c-master-v1"; 685 reg = <0x42520000 0x10000>; 686 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 687 #address-cells = <3>; 688 #size-cells = <0>; 689 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 690 <&scmi_clk IMX95_CLK_I3C2>, 691 <&scmi_clk IMX95_CLK_I3C2SLOW>; 692 clock-names = "pclk", "fast_clk", "slow_clk"; 693 status = "disabled"; 694 }; 695 696 lpi2c3: i2c@42530000 { 697 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 698 reg = <0x42530000 0x10000>; 699 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 701 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 702 clock-names = "per", "ipg"; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 706 dma-names = "tx", "rx"; 707 status = "disabled"; 708 }; 709 710 lpi2c4: i2c@42540000 { 711 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 712 reg = <0x42540000 0x10000>; 713 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 715 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 716 clock-names = "per", "ipg"; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 720 dma-names = "tx", "rx"; 721 status = "disabled"; 722 }; 723 724 lpspi3: spi@42550000 { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 728 reg = <0x42550000 0x10000>; 729 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 731 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 732 clock-names = "per", "ipg"; 733 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 734 dma-names = "tx", "rx"; 735 status = "disabled"; 736 }; 737 738 lpspi4: spi@42560000 { 739 #address-cells = <1>; 740 #size-cells = <0>; 741 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 742 reg = <0x42560000 0x10000>; 743 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 745 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 746 clock-names = "per", "ipg"; 747 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 748 dma-names = "tx", "rx"; 749 status = "disabled"; 750 }; 751 752 lpuart3: serial@42570000 { 753 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 754 "fsl,imx7ulp-lpuart"; 755 reg = <0x42570000 0x1000>; 756 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 758 clock-names = "ipg"; 759 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 760 dma-names = "rx", "tx"; 761 status = "disabled"; 762 }; 763 764 lpuart4: serial@42580000 { 765 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 766 "fsl,imx7ulp-lpuart"; 767 reg = <0x42580000 0x1000>; 768 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 770 clock-names = "ipg"; 771 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 772 dma-names = "rx", "tx"; 773 status = "disabled"; 774 }; 775 776 lpuart5: serial@42590000 { 777 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 778 "fsl,imx7ulp-lpuart"; 779 reg = <0x42590000 0x1000>; 780 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 782 clock-names = "ipg"; 783 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 784 dma-names = "rx", "tx"; 785 status = "disabled"; 786 }; 787 788 lpuart6: serial@425a0000 { 789 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 790 "fsl,imx7ulp-lpuart"; 791 reg = <0x425a0000 0x1000>; 792 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 794 clock-names = "ipg"; 795 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 796 dma-names = "rx", "tx"; 797 status = "disabled"; 798 }; 799 800 flexcan2: can@425b0000 { 801 compatible = "fsl,imx95-flexcan"; 802 reg = <0x425b0000 0x10000>; 803 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 805 <&scmi_clk IMX95_CLK_CAN2>; 806 clock-names = "ipg", "per"; 807 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 808 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 809 assigned-clock-rates = <40000000>; 810 fsl,clk-source = /bits/ 8 <0>; 811 status = "disabled"; 812 }; 813 814 flexcan3: can@42600000 { 815 compatible = "fsl,imx95-flexcan"; 816 reg = <0x42600000 0x10000>; 817 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 819 <&scmi_clk IMX95_CLK_CAN3>; 820 clock-names = "ipg", "per"; 821 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 822 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 823 assigned-clock-rates = <40000000>; 824 fsl,clk-source = /bits/ 8 <0>; 825 status = "disabled"; 826 }; 827 828 flexspi1: spi@425e0000 { 829 compatible = "nxp,imx8mm-fspi"; 830 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 831 reg-names = "fspi_base", "fspi_mmap"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 836 <&scmi_clk IMX95_CLK_FLEXSPI1>; 837 clock-names = "fspi_en", "fspi"; 838 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 839 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 840 assigned-clock-rates = <200000000>; 841 status = "disabled"; 842 }; 843 844 sai3: sai@42650000 { 845 compatible = "fsl,imx95-sai"; 846 reg = <0x42650000 0x10000>; 847 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 849 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 850 <&dummy>; 851 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 852 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 853 dma-names = "rx", "tx"; 854 status = "disabled"; 855 }; 856 857 sai4: sai@42660000 { 858 compatible = "fsl,imx95-sai"; 859 reg = <0x42660000 0x10000>; 860 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 862 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 863 <&dummy>; 864 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 865 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 866 dma-names = "rx", "tx"; 867 status = "disabled"; 868 }; 869 870 sai5: sai@42670000 { 871 compatible = "fsl,imx95-sai"; 872 reg = <0x42670000 0x10000>; 873 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 875 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 876 <&dummy>; 877 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 878 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 879 dma-names = "rx", "tx"; 880 status = "disabled"; 881 }; 882 883 xcvr: xcvr@42680000 { 884 compatible = "fsl,imx95-xcvr"; 885 reg = <0x42680000 0x800>, <0x42680800 0x400>, 886 <0x42680c00 0x080>, <0x42680e00 0x080>; 887 reg-names = "ram", "regs", "rxfifo", "txfifo"; 888 interrupts = /* XCVR IRQ 0 */ 889 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 890 /* XCVR IRQ 1 */ 891 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 893 <&scmi_clk IMX95_CLK_SPDIF>, 894 <&dummy>, 895 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 896 clock-names = "ipg", "phy", "spba", "pll_ipg"; 897 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 898 dma-names = "rx", "tx"; 899 status = "disabled"; 900 }; 901 902 lpuart7: serial@42690000 { 903 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 904 "fsl,imx7ulp-lpuart"; 905 reg = <0x42690000 0x1000>; 906 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 908 clock-names = "ipg"; 909 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; 910 dma-names = "rx", "tx"; 911 status = "disabled"; 912 }; 913 914 lpuart8: serial@426a0000 { 915 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 916 "fsl,imx7ulp-lpuart"; 917 reg = <0x426a0000 0x1000>; 918 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 920 clock-names = "ipg"; 921 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; 922 dma-names = "rx", "tx"; 923 status = "disabled"; 924 }; 925 926 lpi2c5: i2c@426b0000 { 927 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 928 reg = <0x426b0000 0x10000>; 929 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 931 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 932 clock-names = "per", "ipg"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 936 dma-names = "tx", "rx"; 937 status = "disabled"; 938 }; 939 940 lpi2c6: i2c@426c0000 { 941 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 942 reg = <0x426c0000 0x10000>; 943 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 945 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 946 clock-names = "per", "ipg"; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 950 dma-names = "tx", "rx"; 951 status = "disabled"; 952 }; 953 954 lpi2c7: i2c@426d0000 { 955 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 956 reg = <0x426d0000 0x10000>; 957 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 959 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 960 clock-names = "per", "ipg"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 964 dma-names = "tx", "rx"; 965 status = "disabled"; 966 }; 967 968 lpi2c8: i2c@426e0000 { 969 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 970 reg = <0x426e0000 0x10000>; 971 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 973 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 974 clock-names = "per", "ipg"; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 978 dma-names = "tx", "rx"; 979 status = "disabled"; 980 }; 981 982 lpspi5: spi@426f0000 { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 986 reg = <0x426f0000 0x10000>; 987 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 989 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 990 clock-names = "per", "ipg"; 991 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 992 dma-names = "tx", "rx"; 993 status = "disabled"; 994 }; 995 996 lpspi6: spi@42700000 { 997 #address-cells = <1>; 998 #size-cells = <0>; 999 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1000 reg = <0x42700000 0x10000>; 1001 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 1003 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1004 clock-names = "per", "ipg"; 1005 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1006 dma-names = "tx", "rx"; 1007 status = "disabled"; 1008 }; 1009 1010 lpspi7: spi@42710000 { 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1014 reg = <0x42710000 0x10000>; 1015 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 1017 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1018 clock-names = "per", "ipg"; 1019 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1020 dma-names = "tx", "rx"; 1021 status = "disabled"; 1022 }; 1023 1024 lpspi8: spi@42720000 { 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1028 reg = <0x42720000 0x10000>; 1029 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1031 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1032 clock-names = "per", "ipg"; 1033 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1034 dma-names = "tx", "rx"; 1035 status = "disabled"; 1036 }; 1037 1038 mu8: mailbox@42730000 { 1039 compatible = "fsl,imx95-mu"; 1040 reg = <0x42730000 0x10000>; 1041 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1043 #mbox-cells = <2>; 1044 status = "disabled"; 1045 }; 1046 1047 flexcan4: can@427c0000 { 1048 compatible = "fsl,imx95-flexcan"; 1049 reg = <0x427c0000 0x10000>; 1050 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1052 <&scmi_clk IMX95_CLK_CAN4>; 1053 clock-names = "ipg", "per"; 1054 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1055 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1056 assigned-clock-rates = <40000000>; 1057 fsl,clk-source = /bits/ 8 <0>; 1058 status = "disabled"; 1059 }; 1060 1061 flexcan5: can@427d0000 { 1062 compatible = "fsl,imx95-flexcan"; 1063 reg = <0x427d0000 0x10000>; 1064 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1066 <&scmi_clk IMX95_CLK_CAN5>; 1067 clock-names = "ipg", "per"; 1068 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1069 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1070 assigned-clock-rates = <40000000>; 1071 fsl,clk-source = /bits/ 8 <0>; 1072 status = "disabled"; 1073 }; 1074 }; 1075 1076 aips3: bus@42800000 { 1077 compatible = "fsl,aips-bus", "simple-bus"; 1078 reg = <0 0x42800000 0 0x800000>; 1079 #address-cells = <1>; 1080 #size-cells = <1>; 1081 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1082 1083 usdhc1: mmc@42850000 { 1084 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1085 reg = <0x42850000 0x10000>; 1086 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1088 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1089 <&scmi_clk IMX95_CLK_USDHC1>; 1090 clock-names = "ipg", "ahb", "per"; 1091 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1092 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1093 assigned-clock-rates = <400000000>; 1094 bus-width = <8>; 1095 fsl,tuning-start-tap = <1>; 1096 fsl,tuning-step= <2>; 1097 status = "disabled"; 1098 }; 1099 1100 usdhc2: mmc@42860000 { 1101 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1102 reg = <0x42860000 0x10000>; 1103 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1105 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1106 <&scmi_clk IMX95_CLK_USDHC2>; 1107 clock-names = "ipg", "ahb", "per"; 1108 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1109 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1110 assigned-clock-rates = <400000000>; 1111 bus-width = <4>; 1112 fsl,tuning-start-tap = <1>; 1113 fsl,tuning-step= <2>; 1114 status = "disabled"; 1115 }; 1116 1117 usdhc3: mmc@428b0000 { 1118 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1119 reg = <0x428b0000 0x10000>; 1120 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1122 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1123 <&scmi_clk IMX95_CLK_USDHC3>; 1124 clock-names = "ipg", "ahb", "per"; 1125 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1126 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1127 assigned-clock-rates = <400000000>; 1128 bus-width = <4>; 1129 fsl,tuning-start-tap = <1>; 1130 fsl,tuning-step= <2>; 1131 status = "disabled"; 1132 }; 1133 }; 1134 1135 gpio2: gpio@43810000 { 1136 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1137 reg = <0x0 0x43810000 0x0 0x1000>; 1138 gpio-controller; 1139 #gpio-cells = <2>; 1140 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1142 interrupt-controller; 1143 #interrupt-cells = <2>; 1144 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1145 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1146 clock-names = "gpio", "port"; 1147 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1148 }; 1149 1150 gpio3: gpio@43820000 { 1151 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1152 reg = <0x0 0x43820000 0x0 0x1000>; 1153 gpio-controller; 1154 #gpio-cells = <2>; 1155 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1157 interrupt-controller; 1158 #interrupt-cells = <2>; 1159 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1160 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1161 clock-names = "gpio", "port"; 1162 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1163 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1164 }; 1165 1166 gpio4: gpio@43840000 { 1167 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1168 reg = <0x0 0x43840000 0x0 0x1000>; 1169 gpio-controller; 1170 #gpio-cells = <2>; 1171 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1173 interrupt-controller; 1174 #interrupt-cells = <2>; 1175 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1176 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1177 clock-names = "gpio", "port"; 1178 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1179 }; 1180 1181 gpio5: gpio@43850000 { 1182 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1183 reg = <0x0 0x43850000 0x0 0x1000>; 1184 gpio-controller; 1185 #gpio-cells = <2>; 1186 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1188 interrupt-controller; 1189 #interrupt-cells = <2>; 1190 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1191 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1192 clock-names = "gpio", "port"; 1193 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1194 }; 1195 1196 aips1: bus@44000000 { 1197 compatible = "fsl,aips-bus", "simple-bus"; 1198 reg = <0x0 0x44000000 0x0 0x800000>; 1199 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 1203 edma1: dma-controller@44000000 { 1204 compatible = "fsl,imx93-edma3"; 1205 reg = <0x44000000 0x200000>; 1206 #dma-cells = <3>; 1207 dma-channels = <31>; 1208 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1240 clock-names = "dma"; 1241 }; 1242 1243 mu1: mailbox@44220000 { 1244 compatible = "fsl,imx95-mu"; 1245 reg = <0x44220000 0x10000>; 1246 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1248 #mbox-cells = <2>; 1249 status = "disabled"; 1250 }; 1251 1252 tpm1: pwm@44310000 { 1253 compatible = "fsl,imx7ulp-pwm"; 1254 reg = <0x44310000 0x1000>; 1255 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1256 #pwm-cells = <3>; 1257 status = "disabled"; 1258 }; 1259 1260 tpm2: pwm@44320000 { 1261 compatible = "fsl,imx7ulp-pwm"; 1262 reg = <0x44320000 0x1000>; 1263 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1264 #pwm-cells = <3>; 1265 status = "disabled"; 1266 }; 1267 1268 i3c1: i3c@44330000 { 1269 compatible = "silvaco,i3c-master-v1"; 1270 reg = <0x44330000 0x10000>; 1271 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1272 #address-cells = <3>; 1273 #size-cells = <0>; 1274 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1275 <&scmi_clk IMX95_CLK_I3C1>, 1276 <&scmi_clk IMX95_CLK_I3C1SLOW>; 1277 clock-names = "pclk", "fast_clk", "slow_clk"; 1278 status = "disabled"; 1279 }; 1280 1281 lpi2c1: i2c@44340000 { 1282 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1283 reg = <0x44340000 0x10000>; 1284 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1285 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1286 <&scmi_clk IMX95_CLK_BUSAON>; 1287 clock-names = "per", "ipg"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1291 dma-names = "tx", "rx"; 1292 status = "disabled"; 1293 }; 1294 1295 lpi2c2: i2c@44350000 { 1296 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1297 reg = <0x44350000 0x10000>; 1298 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1299 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1300 <&scmi_clk IMX95_CLK_BUSAON>; 1301 clock-names = "per", "ipg"; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1305 dma-names = "tx", "rx"; 1306 status = "disabled"; 1307 }; 1308 1309 lpspi1: spi@44360000 { 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1313 reg = <0x44360000 0x10000>; 1314 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1316 <&scmi_clk IMX95_CLK_BUSAON>; 1317 clock-names = "per", "ipg"; 1318 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1319 dma-names = "tx", "rx"; 1320 status = "disabled"; 1321 }; 1322 1323 lpspi2: spi@44370000 { 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1327 reg = <0x44370000 0x10000>; 1328 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1330 <&scmi_clk IMX95_CLK_BUSAON>; 1331 clock-names = "per", "ipg"; 1332 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1333 dma-names = "tx", "rx"; 1334 status = "disabled"; 1335 }; 1336 1337 lpuart1: serial@44380000 { 1338 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1339 "fsl,imx7ulp-lpuart"; 1340 reg = <0x44380000 0x1000>; 1341 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1343 clock-names = "ipg"; 1344 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1345 dma-names = "rx", "tx"; 1346 status = "disabled"; 1347 }; 1348 1349 lpuart2: serial@44390000 { 1350 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1351 "fsl,imx7ulp-lpuart"; 1352 reg = <0x44390000 0x1000>; 1353 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1355 clock-names = "ipg"; 1356 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1357 dma-names = "rx", "tx"; 1358 status = "disabled"; 1359 }; 1360 1361 flexcan1: can@443a0000 { 1362 compatible = "fsl,imx95-flexcan"; 1363 reg = <0x443a0000 0x10000>; 1364 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1366 <&scmi_clk IMX95_CLK_CAN1>; 1367 clock-names = "ipg", "per"; 1368 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1369 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1370 assigned-clock-rates = <40000000>; 1371 fsl,clk-source = /bits/ 8 <0>; 1372 status = "disabled"; 1373 }; 1374 1375 sai1: sai@443b0000 { 1376 compatible = "fsl,imx95-sai"; 1377 reg = <0x443b0000 0x10000>; 1378 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1380 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1381 <&dummy>; 1382 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1383 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1384 dma-names = "rx", "tx"; 1385 status = "disabled"; 1386 }; 1387 1388 micfil: micfil@44520000 { 1389 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1390 reg = <0x44520000 0x10000>; 1391 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1395 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1396 <&scmi_clk IMX95_CLK_PDM>, 1397 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1398 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1399 <&dummy>; 1400 clock-names = "ipg_clk", "ipg_clk_app", 1401 "pll8k", "pll11k", "clkext3"; 1402 dmas = <&edma1 6 0 5>; 1403 dma-names = "rx"; 1404 status = "disabled"; 1405 }; 1406 1407 adc1: adc@44530000 { 1408 compatible = "nxp,imx93-adc"; 1409 reg = <0x44530000 0x10000>; 1410 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&scmi_clk IMX95_CLK_ADC>; 1414 clock-names = "ipg"; 1415 #io-channel-cells = <1>; 1416 status = "disabled"; 1417 }; 1418 1419 mu2: mailbox@445b0000 { 1420 compatible = "fsl,imx95-mu"; 1421 reg = <0x445b0000 0x1000>; 1422 ranges; 1423 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1424 #address-cells = <1>; 1425 #size-cells = <1>; 1426 #mbox-cells = <2>; 1427 1428 sram0: sram@445b1000 { 1429 compatible = "mmio-sram"; 1430 reg = <0x445b1000 0x400>; 1431 ranges = <0x0 0x445b1000 0x400>; 1432 #address-cells = <1>; 1433 #size-cells = <1>; 1434 1435 scmi_buf0: scmi-sram-section@0 { 1436 compatible = "arm,scmi-shmem"; 1437 reg = <0x0 0x80>; 1438 }; 1439 1440 scmi_buf1: scmi-sram-section@80 { 1441 compatible = "arm,scmi-shmem"; 1442 reg = <0x80 0x80>; 1443 }; 1444 }; 1445 1446 }; 1447 1448 mu3: mailbox@445d0000 { 1449 compatible = "fsl,imx95-mu"; 1450 reg = <0x445d0000 0x10000>; 1451 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1452 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1453 #mbox-cells = <2>; 1454 status = "disabled"; 1455 }; 1456 1457 mu4: mailbox@445f0000 { 1458 compatible = "fsl,imx95-mu"; 1459 reg = <0x445f0000 0x10000>; 1460 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1461 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1462 #mbox-cells = <2>; 1463 status = "disabled"; 1464 }; 1465 1466 mu6: mailbox@44630000 { 1467 compatible = "fsl,imx95-mu"; 1468 reg = <0x44630000 0x10000>; 1469 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1471 #mbox-cells = <2>; 1472 status = "disabled"; 1473 }; 1474 }; 1475 1476 mailbox@47320000 { 1477 compatible = "fsl,imx95-mu-v2x"; 1478 reg = <0x0 0x47320000 0x0 0x10000>; 1479 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1480 #mbox-cells = <2>; 1481 }; 1482 1483 mailbox@47350000 { 1484 compatible = "fsl,imx95-mu-v2x"; 1485 reg = <0x0 0x47350000 0x0 0x10000>; 1486 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1487 #mbox-cells = <2>; 1488 }; 1489 1490 /* GPIO1 is under exclusive control of System Manager */ 1491 gpio1: gpio@47400000 { 1492 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1493 reg = <0x0 0x47400000 0x0 0x1000>; 1494 gpio-controller; 1495 #gpio-cells = <2>; 1496 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1498 interrupt-controller; 1499 #interrupt-cells = <2>; 1500 clocks = <&scmi_clk IMX95_CLK_M33>, 1501 <&scmi_clk IMX95_CLK_M33>; 1502 clock-names = "gpio", "port"; 1503 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1504 status = "disabled"; 1505 }; 1506 1507 elemu0: mailbox@47520000 { 1508 compatible = "fsl,imx95-mu-ele"; 1509 reg = <0x0 0x47520000 0x0 0x10000>; 1510 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1511 #mbox-cells = <2>; 1512 status = "disabled"; 1513 }; 1514 1515 elemu1: mailbox@47530000 { 1516 compatible = "fsl,imx95-mu-ele"; 1517 reg = <0x0 0x47530000 0x0 0x10000>; 1518 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1519 #mbox-cells = <2>; 1520 status = "disabled"; 1521 }; 1522 1523 elemu2: mailbox@47540000 { 1524 compatible = "fsl,imx95-mu-ele"; 1525 reg = <0x0 0x47540000 0x0 0x10000>; 1526 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1527 #mbox-cells = <2>; 1528 status = "disabled"; 1529 }; 1530 1531 elemu3: mailbox@47550000 { 1532 compatible = "fsl,imx95-mu-ele"; 1533 reg = <0x0 0x47550000 0x0 0x10000>; 1534 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1535 #mbox-cells = <2>; 1536 }; 1537 1538 elemu4: mailbox@47560000 { 1539 compatible = "fsl,imx95-mu-ele"; 1540 reg = <0x0 0x47560000 0x0 0x10000>; 1541 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1542 #mbox-cells = <2>; 1543 status = "disabled"; 1544 }; 1545 1546 elemu5: mailbox@47570000 { 1547 compatible = "fsl,imx95-mu-ele"; 1548 reg = <0x0 0x47570000 0x0 0x10000>; 1549 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1550 #mbox-cells = <2>; 1551 status = "disabled"; 1552 }; 1553 1554 aips4: bus@49000000 { 1555 compatible = "fsl,aips-bus", "simple-bus"; 1556 reg = <0x0 0x49000000 0x0 0x800000>; 1557 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1558 #address-cells = <1>; 1559 #size-cells = <1>; 1560 1561 smmu: iommu@490d0000 { 1562 compatible = "arm,smmu-v3"; 1563 reg = <0x490d0000 0x100000>; 1564 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1565 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1566 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1567 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1568 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1569 #iommu-cells = <1>; 1570 status = "disabled"; 1571 }; 1572 }; 1573 1574 usb3: usb@4c010010 { 1575 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; 1576 reg = <0x0 0x4c010010 0x0 0x04>, 1577 <0x0 0x4c1f0000 0x0 0x20>; 1578 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1579 <&scmi_clk IMX95_CLK_32K>; 1580 clock-names = "hsio", "suspend"; 1581 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1582 #address-cells = <2>; 1583 #size-cells = <2>; 1584 ranges; 1585 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1586 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 1587 status = "disabled"; 1588 1589 usb3_dwc3: usb@4c100000 { 1590 compatible = "snps,dwc3"; 1591 reg = <0x0 0x4c100000 0x0 0x10000>; 1592 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1593 <&scmi_clk IMX95_CLK_24M>, 1594 <&scmi_clk IMX95_CLK_32K>; 1595 clock-names = "bus_early", "ref", "suspend"; 1596 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1597 phys = <&usb3_phy>, <&usb3_phy>; 1598 phy-names = "usb2-phy", "usb3-phy"; 1599 snps,gfladj-refclk-lpm-sel-quirk; 1600 snps,parkmode-disable-ss-quirk; 1601 iommus = <&smmu 0xe>; 1602 }; 1603 }; 1604 1605 hsio_blk_ctl: syscon@4c0100c0 { 1606 compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; 1607 reg = <0x0 0x4c0100c0 0x0 0x1>; 1608 #clock-cells = <1>; 1609 clocks = <&clk_sys100m>; 1610 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1611 }; 1612 1613 usb3_phy: phy@4c1f0040 { 1614 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; 1615 reg = <0x0 0x4c1f0040 0x0 0x40>, 1616 <0x0 0x4c1fc000 0x0 0x100>; 1617 clocks = <&scmi_clk IMX95_CLK_HSIO>; 1618 clock-names = "phy"; 1619 #phy-cells = <0>; 1620 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1621 status = "disabled"; 1622 }; 1623 1624 pcie0: pcie@4c300000 { 1625 compatible = "fsl,imx95-pcie"; 1626 reg = <0 0x4c300000 0 0x10000>, 1627 <0 0x60100000 0 0xfe00000>, 1628 <0 0x4c360000 0 0x10000>, 1629 <0 0x4c340000 0 0x4000>; 1630 reg-names = "dbi", "config", "atu", "app"; 1631 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1632 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1633 #address-cells = <3>; 1634 #size-cells = <2>; 1635 device_type = "pci"; 1636 linux,pci-domain = <0>; 1637 bus-range = <0x00 0xff>; 1638 num-lanes = <1>; 1639 num-viewport = <8>; 1640 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1641 interrupt-names = "msi"; 1642 #interrupt-cells = <1>; 1643 interrupt-map-mask = <0 0 0 0x7>; 1644 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1645 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1646 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1647 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1649 <&scmi_clk IMX95_CLK_HSIOPLL>, 1650 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1651 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1652 <&hsio_blk_ctl 0>; 1653 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1654 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1655 <&scmi_clk IMX95_CLK_HSIOPLL>, 1656 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1657 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1658 assigned-clock-parents = <0>, <0>, 1659 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1660 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1661 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ 1662 msi-map = <0x0 &its 0x10 0x1>, 1663 <0x100 &its 0x11 0x7>; 1664 iommu-map = <0x000 &smmu 0x10 0x1>, 1665 <0x100 &smmu 0x11 0x7>; 1666 iommu-map-mask = <0x1ff>; 1667 fsl,max-link-speed = <3>; 1668 status = "disabled"; 1669 }; 1670 1671 pcie0_ep: pcie-ep@4c300000 { 1672 compatible = "fsl,imx95-pcie-ep"; 1673 reg = <0 0x4c300000 0 0x10000>, 1674 <0 0x4c360000 0 0x1000>, 1675 <0 0x4c320000 0 0x1000>, 1676 <0 0x4c340000 0 0x4000>, 1677 <0 0x4c370000 0 0x10000>, 1678 <0x9 0 1 0>; 1679 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1680 num-lanes = <1>; 1681 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1682 interrupt-names = "dma"; 1683 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1684 <&scmi_clk IMX95_CLK_HSIOPLL>, 1685 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1686 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1687 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1688 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1689 <&scmi_clk IMX95_CLK_HSIOPLL>, 1690 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1691 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1692 assigned-clock-parents = <0>, <0>, 1693 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1694 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1695 status = "disabled"; 1696 }; 1697 1698 pcie1: pcie@4c380000 { 1699 compatible = "fsl,imx95-pcie"; 1700 reg = <0 0x4c380000 0 0x10000>, 1701 <8 0x80100000 0 0xfe00000>, 1702 <0 0x4c3e0000 0 0x10000>, 1703 <0 0x4c3c0000 0 0x4000>; 1704 reg-names = "dbi", "config", "atu", "app"; 1705 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1706 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1707 #address-cells = <3>; 1708 #size-cells = <2>; 1709 device_type = "pci"; 1710 linux,pci-domain = <1>; 1711 bus-range = <0x00 0xff>; 1712 num-lanes = <1>; 1713 num-viewport = <8>; 1714 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1715 interrupt-names = "msi"; 1716 #interrupt-cells = <1>; 1717 interrupt-map-mask = <0 0 0 0x7>; 1718 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1719 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1720 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1721 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1723 <&scmi_clk IMX95_CLK_HSIOPLL>, 1724 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1725 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1726 <&hsio_blk_ctl 0>; 1727 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1728 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1729 <&scmi_clk IMX95_CLK_HSIOPLL>, 1730 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1731 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1732 assigned-clock-parents = <0>, <0>, 1733 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1734 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1735 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ 1736 msi-map = <0x0 &its 0x98 0x1>, 1737 <0x100 &its 0x99 0x7>; 1738 msi-map-mask = <0x1ff>; 1739 /* smmu have not Devid(BIT[7:6]) */ 1740 iommu-map = <0x000 &smmu 0x18 0x1>, 1741 <0x100 &smmu 0x19 0x7>; 1742 iommu-map-mask = <0x1ff>; 1743 fsl,max-link-speed = <3>; 1744 status = "disabled"; 1745 }; 1746 1747 pcie1_ep: pcie-ep@4c380000 { 1748 compatible = "fsl,imx95-pcie-ep"; 1749 reg = <0 0x4c380000 0 0x10000>, 1750 <0 0x4c3e0000 0 0x1000>, 1751 <0 0x4c3a0000 0 0x1000>, 1752 <0 0x4c3c0000 0 0x4000>, 1753 <0 0x4c3f0000 0 0x10000>, 1754 <0xa 0 1 0>; 1755 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1756 num-lanes = <1>; 1757 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1758 interrupt-names = "dma"; 1759 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1760 <&scmi_clk IMX95_CLK_HSIOPLL>, 1761 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1762 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1763 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1764 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1765 <&scmi_clk IMX95_CLK_HSIOPLL>, 1766 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1767 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1768 assigned-clock-parents = <0>, <0>, 1769 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1770 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1771 status = "disabled"; 1772 }; 1773 1774 netcmix_blk_ctrl: syscon@4c810000 { 1775 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 1776 reg = <0x0 0x4c810000 0x0 0x8>; 1777 #clock-cells = <1>; 1778 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1779 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1780 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1781 assigned-clock-rates = <133333333>; 1782 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1783 status = "disabled"; 1784 }; 1785 1786 sai2: sai@4c880000 { 1787 compatible = "fsl,imx95-sai"; 1788 reg = <0x0 0x4c880000 0x0 0x10000>; 1789 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1790 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 1791 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 1792 <&dummy>; 1793 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1794 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1795 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 1796 dma-names = "rx", "tx"; 1797 status = "disabled"; 1798 }; 1799 1800 netc_blk_ctrl: system-controller@4cde0000 { 1801 compatible = "nxp,imx95-netc-blk-ctrl"; 1802 reg = <0x0 0x4cde0000 0x0 0x10000>, 1803 <0x0 0x4cdf0000 0x0 0x10000>, 1804 <0x0 0x4c81000c 0x0 0x18>; 1805 reg-names = "ierb", "prb", "netcmix"; 1806 #address-cells = <2>; 1807 #size-cells = <2>; 1808 ranges; 1809 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1810 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, 1811 <&scmi_clk IMX95_CLK_ENETREF>; 1812 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 1813 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 1814 assigned-clock-rates = <666666666>, <250000000>; 1815 clocks = <&scmi_clk IMX95_CLK_ENET>; 1816 clock-names = "ipg"; 1817 status = "disabled"; 1818 1819 netc_bus0: pcie@4ca00000 { 1820 compatible = "pci-host-ecam-generic"; 1821 reg = <0x0 0x4ca00000 0x0 0x100000>; 1822 #address-cells = <3>; 1823 #size-cells = <2>; 1824 device_type = "pci"; 1825 bus-range = <0x0 0x0>; 1826 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 1827 <0x10 &its 0x61 0x1>, //ENETC0 VF0 1828 <0x20 &its 0x62 0x1>, //ENETC0 VF1 1829 <0x40 &its 0x63 0x1>, //ENETC1 PF 1830 <0x80 &its 0x64 0x1>, //ENETC2 PF 1831 <0x90 &its 0x65 0x1>, //ENETC2 VF0 1832 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 1833 <0xc0 &its 0x67 0x1>; //NETC Timer 1834 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ 1835 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 1836 /* Timer BAR2 - prefetchable memory */ 1837 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 1838 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ 1839 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 1840 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ 1841 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; 1842 1843 enetc_port0: ethernet@0,0 { 1844 compatible = "pci1131,e101"; 1845 reg = <0x000000 0 0 0 0>; 1846 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 1847 clock-names = "ref"; 1848 status = "disabled"; 1849 }; 1850 1851 enetc_port1: ethernet@8,0 { 1852 compatible = "pci1131,e101"; 1853 reg = <0x004000 0 0 0 0>; 1854 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 1855 clock-names = "ref"; 1856 status = "disabled"; 1857 }; 1858 1859 enetc_port2: ethernet@10,0 { 1860 compatible = "pci1131,e101"; 1861 reg = <0x008000 0 0 0 0>; 1862 status = "disabled"; 1863 }; 1864 1865 netc_timer: ethernet@18,0 { 1866 reg = <0x00c000 0 0 0 0>; 1867 status = "disabled"; 1868 }; 1869 }; 1870 1871 netc_bus1: pcie@4cb00000 { 1872 compatible = "pci-host-ecam-generic"; 1873 reg = <0x0 0x4cb00000 0x0 0x100000>; 1874 #address-cells = <3>; 1875 #size-cells = <2>; 1876 device_type = "pci"; 1877 bus-range = <0x1 0x1>; 1878 /* EMDIO BAR0 - non-prefetchable memory */ 1879 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 1880 /* EMDIO BAR2 - prefetchable memory */ 1881 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; 1882 1883 netc_emdio: mdio@0,0 { 1884 compatible = "pci1131,ee00"; 1885 reg = <0x010000 0 0 0 0>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 status = "disabled"; 1889 }; 1890 }; 1891 }; 1892 1893 ddr-pmu@4e090dc0 { 1894 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 1895 reg = <0x0 0x4e090dc0 0x0 0x200>; 1896 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1897 }; 1898 }; 1899}; 1900