1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017~2018 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8qxp.dtsi"
9#include <dt-bindings/usb/pd.h>
10
11/ {
12	model = "Freescale i.MX8QXP MEK";
13	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
14
15	bt_sco_codec: audio-codec-bt {
16		compatible = "linux,bt-sco";
17		#sound-dai-cells = <1>;
18	};
19
20	chosen {
21		stdout-path = &lpuart0;
22	};
23
24	imx8x_cm4: imx8x-cm4 {
25		compatible = "fsl,imx8qxp-cm4";
26		mbox-names = "tx", "rx", "rxdb";
27		mboxes = <&lsio_mu5 0 1
28			  &lsio_mu5 1 1
29			  &lsio_mu5 3 1>;
30		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
31				<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
32		power-domains = <&pd IMX_SC_R_M4_0_PID0>,
33				<&pd IMX_SC_R_M4_0_MU_1A>;
34		fsl,entry-address = <0x34fe0000>;
35		fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
36	};
37
38	memory@80000000 {
39		device_type = "memory";
40		reg = <0x00000000 0x80000000 0 0x40000000>;
41	};
42
43	reserved-memory {
44		dsp_vdev0vring0: memory@942f0000 {
45			reg = <0 0x942f0000 0 0x8000>;
46			no-map;
47		};
48
49		dsp_vdev0vring1: memory@942f8000 {
50			reg = <0 0x942f8000 0 0x8000>;
51			no-map;
52		};
53
54		dsp_vdev0buffer: memory@94300000 {
55			compatible = "shared-dma-pool";
56			reg = <0 0x94300000 0 0x100000>;
57			no-map;
58		};
59	};
60
61	reg_usdhc2_vmmc: usdhc2-vmmc {
62		compatible = "regulator-fixed";
63		regulator-name = "SD1_SPWR";
64		regulator-min-microvolt = <3000000>;
65		regulator-max-microvolt = <3000000>;
66		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
67		enable-active-high;
68	};
69
70	gpio-sbu-mux {
71		compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_typec_mux>;
74		select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
75		enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
76		orientation-switch;
77
78		port {
79			usb3_data_ss: endpoint {
80				remote-endpoint = <&typec_con_ss>;
81			};
82		};
83	};
84
85	reg_pcieb: regulator-pcie {
86		compatible = "regulator-fixed";
87		regulator-max-microvolt = <3300000>;
88		regulator-min-microvolt = <3300000>;
89		regulator-name = "mpcie_3v3";
90		gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>;
91		enable-active-high;
92	};
93
94	reg_audio: regulator-audio {
95		compatible = "regulator-fixed";
96		regulator-max-microvolt = <3300000>;
97		regulator-min-microvolt = <3300000>;
98		regulator-name = "cs42888_supply";
99	};
100
101	reg_audio_5v: regulator-audio-pwr {
102		compatible = "regulator-fixed";
103		regulator-name = "audio-5v";
104		regulator-min-microvolt = <5000000>;
105		regulator-max-microvolt = <5000000>;
106		regulator-always-on;
107		regulator-boot-on;
108	};
109
110	reg_audio_3v3: regulator-audio-3v3 {
111		compatible = "regulator-fixed";
112		regulator-name = "audio-3v3";
113		regulator-min-microvolt = <3300000>;
114		regulator-max-microvolt = <3300000>;
115		regulator-always-on;
116		regulator-boot-on;
117	};
118
119	reg_audio_1v8: regulator-audio-1v8 {
120		compatible = "regulator-fixed";
121		regulator-name = "audio-1v8";
122		regulator-min-microvolt = <1800000>;
123		regulator-max-microvolt = <1800000>;
124		regulator-always-on;
125		regulator-boot-on;
126	};
127
128	reg_can_en: regulator-can-en {
129		compatible = "regulator-fixed";
130		regulator-max-microvolt = <3300000>;
131		regulator-min-microvolt = <3300000>;
132		regulator-name = "can-en";
133		gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
134		enable-active-high;
135	};
136
137	reg_can_stby: regulator-can-stby {
138		compatible = "regulator-fixed";
139		regulator-max-microvolt = <3300000>;
140		regulator-min-microvolt = <3300000>;
141		regulator-name = "can-stby";
142		gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
143		enable-active-high;
144		vin-supply = <&reg_can_en>;
145	};
146
147	reg_usb_otg1_vbus: regulator-usbotg1-vbus {
148		compatible = "regulator-fixed";
149		regulator-max-microvolt = <5000000>;
150		regulator-min-microvolt = <5000000>;
151		regulator-name = "usb_otg1_vbus";
152		gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>;
153		enable-active-high;
154	};
155
156	reserved-memory {
157		#address-cells = <2>;
158		#size-cells = <2>;
159		ranges;
160
161		vdev0vring0: memory@90000000 {
162			reg = <0 0x90000000 0 0x8000>;
163			no-map;
164		};
165
166		vdev0vring1: memory@90008000 {
167			reg = <0 0x90008000 0 0x8000>;
168			no-map;
169		};
170
171		vdev1vring0: memory@90010000 {
172			reg = <0 0x90010000 0 0x8000>;
173			no-map;
174		};
175
176		vdev1vring1: memory@90018000 {
177			reg = <0 0x90018000 0 0x8000>;
178			no-map;
179		};
180
181		rsc_table: memory@900ff000 {
182			reg = <0 0x900ff000 0 0x1000>;
183			no-map;
184		};
185
186		vdevbuffer: memory@90400000 {
187			compatible = "shared-dma-pool";
188			reg = <0 0x90400000 0 0x100000>;
189			no-map;
190		};
191
192		gpu_reserved: memory@880000000 {
193			no-map;
194			reg = <0x8 0x80000000 0 0x10000000>;
195		};
196	};
197
198	sound-bt-sco {
199		compatible = "simple-audio-card";
200		simple-audio-card,bitclock-inversion;
201		simple-audio-card,bitclock-master = <&btcpu>;
202		simple-audio-card,format = "dsp_a";
203		simple-audio-card,frame-master = <&btcpu>;
204		simple-audio-card,name = "bt-sco-audio";
205
206		simple-audio-card,codec {
207			sound-dai = <&bt_sco_codec 1>;
208		};
209
210		btcpu: simple-audio-card,cpu {
211			dai-tdm-slot-num = <2>;
212			dai-tdm-slot-width = <16>;
213			sound-dai = <&sai0>;
214		};
215	};
216
217	sound-cs42888 {
218		compatible = "fsl,imx-audio-cs42888";
219		audio-asrc = <&asrc0>;
220		audio-codec = <&cs42888>;
221		audio-cpu = <&esai0>;
222		audio-routing =
223			"Line Out Jack", "AOUT1L",
224			"Line Out Jack", "AOUT1R",
225			"Line Out Jack", "AOUT2L",
226			"Line Out Jack", "AOUT2R",
227			"Line Out Jack", "AOUT3L",
228			"Line Out Jack", "AOUT3R",
229			"Line Out Jack", "AOUT4L",
230			"Line Out Jack", "AOUT4R",
231			"AIN1L", "Line In Jack",
232			"AIN1R", "Line In Jack",
233			"AIN2L", "Line In Jack",
234			"AIN2R", "Line In Jack";
235		model = "imx-cs42888";
236	};
237
238	sound-wm8960 {
239		compatible = "fsl,imx-audio-wm8960";
240		model = "wm8960-audio";
241		audio-cpu = <&sai1>;
242		audio-codec = <&wm8960>;
243		hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
244		audio-routing = "Headphone Jack", "HP_L",
245				"Headphone Jack", "HP_R",
246				"Ext Spk", "SPK_LP",
247				"Ext Spk", "SPK_LN",
248				"Ext Spk", "SPK_RP",
249				"Ext Spk", "SPK_RN",
250				"LINPUT1", "Mic Jack",
251				"Mic Jack", "MICB";
252	};
253};
254
255&amix {
256	status = "okay";
257};
258
259&asrc0 {
260	fsl,asrc-rate = <48000>;
261	status = "okay";
262};
263
264&dsp {
265	memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
266			<&dsp_vdev0vring1>, <&dsp_reserved>;
267	status = "okay";
268};
269
270&dsp_reserved {
271	status = "okay";
272};
273
274&esai0 {
275	assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
276			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
277			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
278			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
279			<&esai0_lpcg IMX_LPCG_CLK_0>;
280	assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
281	assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
282	pinctrl-0 = <&pinctrl_esai0>;
283	pinctrl-names = "default";
284	status = "okay";
285};
286
287&fec1 {
288	pinctrl-names = "default";
289	pinctrl-0 = <&pinctrl_fec1>;
290	phy-mode = "rgmii-id";
291	phy-handle = <&ethphy0>;
292	fsl,magic-packet;
293	status = "okay";
294
295	mdio {
296		#address-cells = <1>;
297		#size-cells = <0>;
298
299		ethphy0: ethernet-phy@0 {
300			compatible = "ethernet-phy-ieee802.3-c22";
301			reg = <0>;
302		};
303	};
304};
305
306&i2c1 {
307	#address-cells = <1>;
308	#size-cells = <0>;
309	clock-frequency = <100000>;
310	pinctrl-names = "default";
311	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
312	status = "okay";
313
314	i2c-mux@71 {
315		compatible = "nxp,pca9646", "nxp,pca9546";
316		#address-cells = <1>;
317		#size-cells = <0>;
318		reg = <0x71>;
319		reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
320
321		i2c@0 {
322			#address-cells = <1>;
323			#size-cells = <0>;
324			reg = <0>;
325
326			max7322: gpio@68 {
327				compatible = "maxim,max7322";
328				reg = <0x68>;
329				gpio-controller;
330				#gpio-cells = <2>;
331			};
332		};
333
334		i2c@1 {
335			#address-cells = <1>;
336			#size-cells = <0>;
337			reg = <1>;
338		};
339
340		i2c@2 {
341			#address-cells = <1>;
342			#size-cells = <0>;
343			reg = <2>;
344
345			pressure-sensor@60 {
346				compatible = "fsl,mpl3115";
347				reg = <0x60>;
348			};
349		};
350
351		i2c@3 {
352			#address-cells = <1>;
353			#size-cells = <0>;
354			reg = <3>;
355
356			pca9557_a: gpio@1a {
357				compatible = "nxp,pca9557";
358				reg = <0x1a>;
359				gpio-controller;
360				#gpio-cells = <2>;
361			};
362
363			pca9557_b: gpio@1d {
364				compatible = "nxp,pca9557";
365				reg = <0x1d>;
366				gpio-controller;
367				#gpio-cells = <2>;
368			};
369
370			light-sensor@44 {
371				pinctrl-names = "default";
372				pinctrl-0 = <&pinctrl_isl29023>;
373				compatible = "isil,isl29023";
374				reg = <0x44>;
375				interrupt-parent = <&lsio_gpio1>;
376				interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
377			};
378		};
379	};
380
381	ptn5110: tcpc@50 {
382		compatible = "nxp,ptn5110", "tcpci";
383		pinctrl-names = "default";
384		pinctrl-0 = <&pinctrl_typec>;
385		reg = <0x50>;
386		interrupt-parent = <&lsio_gpio1>;
387		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
388
389		usb_con1: connector {
390			compatible = "usb-c-connector";
391			label = "USB-C";
392			power-role = "source";
393			data-role = "dual";
394			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
395
396			ports {
397				#address-cells = <1>;
398				#size-cells = <0>;
399
400				port@0 {
401					reg = <0>;
402
403					typec_dr_sw: endpoint {
404						remote-endpoint = <&usb3_drd_sw>;
405					};
406				};
407
408				port@1 {
409					reg = <1>;
410
411					typec_con_ss: endpoint {
412						remote-endpoint = <&usb3_data_ss>;
413					};
414				};
415			};
416		};
417	};
418
419};
420
421&cm40_i2c {
422	#address-cells = <1>;
423	#size-cells = <0>;
424	clock-frequency = <100000>;
425	pinctrl-names = "default", "gpio";
426	pinctrl-0 = <&pinctrl_cm40_i2c>;
427	pinctrl-1 = <&pinctrl_cm40_i2c_gpio>;
428	scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>;
429	sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>;
430	status = "okay";
431
432	wm8960: audio-codec@1a {
433		compatible = "wlf,wm8960";
434		reg = <0x1a>;
435		clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
436		clock-names = "mclk";
437		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
438				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
439				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
440				  <&mclkout0_lpcg IMX_LPCG_CLK_0>;
441		assigned-clock-rates = <786432000>,
442				       <49152000>,
443				       <12288000>,
444				       <12288000>;
445		wlf,shared-lrclk;
446		wlf,hp-cfg = <2 2 3>;
447		wlf,gpio-cfg = <1 3>;
448		AVDD-supply = <&reg_audio_3v3>;
449		DBVDD-supply = <&reg_audio_1v8>;
450		DCVDD-supply = <&reg_audio_1v8>;
451		SPKVDD1-supply = <&reg_audio_5v>;
452		SPKVDD2-supply = <&reg_audio_5v>;
453	};
454
455	pca6416: gpio@20 {
456		compatible = "ti,tca6416";
457		reg = <0x20>;
458		gpio-controller;
459		#gpio-cells = <2>;
460	};
461
462	cs42888: audio-codec@48 {
463		compatible = "cirrus,cs42888";
464		reg = <0x48>;
465		clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
466		clock-names = "mclk";
467		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
468				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
469				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
470				<&mclkout0_lpcg IMX_LPCG_CLK_0>;
471		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
472		reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>;
473		VA-supply = <&reg_audio>;
474		VD-supply = <&reg_audio>;
475		VLC-supply = <&reg_audio>;
476		VLS-supply = <&reg_audio>;
477	};
478};
479
480&cm40_intmux {
481	status = "okay";
482};
483
484&hsio_phy {
485	fsl,hsio-cfg = "pciea-x2-pcieb";
486	fsl,refclk-pad-mode = "input";
487	status = "okay";
488};
489
490&flexcan1 {
491	pinctrl-0 = <&pinctrl_flexcan1>;
492	pinctrl-names = "default";
493	xceiver-supply = <&reg_can_stby>;
494	status = "okay";
495};
496
497&flexcan2 {
498	pinctrl-0 = <&pinctrl_flexcan2>;
499	pinctrl-names = "default";
500	xceiver-supply = <&reg_can_stby>;
501	status = "okay";
502};
503
504&jpegdec {
505	status = "okay";
506};
507
508&jpegenc {
509	status = "okay";
510};
511
512&lpuart0 {
513	pinctrl-names = "default";
514	pinctrl-0 = <&pinctrl_lpuart0>;
515	status = "okay";
516};
517
518&lpuart2 {
519	pinctrl-names = "default";
520	pinctrl-0 = <&pinctrl_lpuart2>;
521	status = "okay";
522};
523
524&lpuart3 {
525	pinctrl-names = "default";
526	pinctrl-0 = <&pinctrl_lpuart3>;
527	status = "okay";
528};
529
530&lsio_mu5 {
531	status = "okay";
532};
533
534&mu_m0 {
535	status = "okay";
536};
537
538&mu1_m0 {
539	status = "okay";
540};
541
542&pcieb {
543	phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
544	phy-names = "pcie-phy";
545	pinctrl-0 = <&pinctrl_pcieb>;
546	pinctrl-names = "default";
547	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
548	vpcie-supply = <&reg_pcieb>;
549	status = "okay";
550};
551
552&scu_key {
553	status = "okay";
554};
555
556&sai0 {
557	#sound-dai-cells = <0>;
558	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
559			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
560			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
561			  <&sai0_lpcg IMX_LPCG_CLK_0>;
562	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
563	pinctrl-names = "default";
564	pinctrl-0 = <&pinctrl_sai0>;
565	status = "okay";
566};
567
568&sai1 {
569	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
570			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
571			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
572			  <&sai1_lpcg IMX_LPCG_CLK_0>;
573	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
574	pinctrl-names = "default";
575	pinctrl-0 = <&pinctrl_sai1>;
576	status = "okay";
577};
578
579&sai4 {
580	assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
581			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
582			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
583			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
584			  <&sai4_lpcg IMX_LPCG_CLK_0>;
585	assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
586	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
587	fsl,sai-asynchronous;
588	status = "okay";
589};
590
591&sai5 {
592	assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
593			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
594			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
595			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
596			  <&sai5_lpcg IMX_LPCG_CLK_0>;
597	assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
598	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
599	fsl,sai-asynchronous;
600	status = "okay";
601};
602
603&thermal_zones {
604	pmic-thermal {
605		polling-delay-passive = <250>;
606		polling-delay = <2000>;
607		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
608
609		trips {
610			pmic_alert0: trip0 {
611				temperature = <110000>;
612				hysteresis = <2000>;
613				type = "passive";
614			};
615
616			pmic_crit0: trip1 {
617				temperature = <125000>;
618				hysteresis = <2000>;
619				type = "critical";
620			};
621		};
622
623		cooling-maps {
624			map0 {
625				trip = <&pmic_alert0>;
626				cooling-device =
627					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
628					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
629					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
630					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
631			};
632		};
633	};
634};
635
636&usdhc1 {
637	assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
638	assigned-clock-rates = <200000000>;
639	pinctrl-names = "default";
640	pinctrl-0 = <&pinctrl_usdhc1>;
641	bus-width = <8>;
642	no-sd;
643	no-sdio;
644	non-removable;
645	status = "okay";
646};
647
648&usdhc2 {
649	assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
650	assigned-clock-rates = <200000000>;
651	pinctrl-names = "default";
652	pinctrl-0 = <&pinctrl_usdhc2>;
653	bus-width = <4>;
654	vmmc-supply = <&reg_usdhc2_vmmc>;
655	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
656	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
657	status = "okay";
658};
659
660&usb3_phy {
661	status = "okay";
662};
663
664&usbphy1 {
665	status = "okay";
666};
667
668&usbotg1 {
669	adp-disable;
670	hnp-disable;
671	srp-disable;
672	disable-over-current;
673	power-active-high;
674	vbus-supply = <&reg_usb_otg1_vbus>;
675	status = "okay";
676};
677
678&usbotg3 {
679	status = "okay";
680};
681
682&usbotg3_cdns3 {
683	dr_mode = "otg";
684	usb-role-switch;
685	status = "okay";
686
687	port {
688		usb3_drd_sw: endpoint {
689			remote-endpoint = <&typec_dr_sw>;
690		};
691	};
692};
693
694
695&vpu {
696	compatible = "nxp,imx8qxp-vpu";
697	status = "okay";
698};
699
700&vpu_core0 {
701	reg = <0x2d040000 0x10000>;
702	memory-region = <&decoder_boot>, <&decoder_rpc>;
703	status = "okay";
704};
705
706&vpu_core1 {
707	reg = <0x2d050000 0x10000>;
708	memory-region = <&encoder_boot>, <&encoder_rpc>;
709	status = "okay";
710};
711
712&iomuxc {
713
714	pinctrl_cm40_i2c: cm40i2cgrp {
715		fsl,pins = <
716			IMX8QXP_ADC_IN1_M40_I2C0_SDA                            0x0600004c
717			IMX8QXP_ADC_IN0_M40_I2C0_SCL                            0x0600004c
718		>;
719	};
720
721	pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp {
722		fsl,pins = <
723			IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09				0xc600004c
724			IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10				0xc600004c
725		>;
726	};
727
728	pinctrl_esai0: esai0grp {
729		fsl,pins = <
730			IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR           0xc6000040
731			IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST           0xc6000040
732			IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR         0xc6000040
733			IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT         0xc6000040
734			IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0           0xc6000040
735			IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1           0xc6000040
736			IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3   0xc6000040
737			IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2   0xc6000040
738			IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1   0xc6000040
739			IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0   0xc6000040
740		>;
741	};
742
743	pinctrl_fec1: fec1grp {
744		fsl,pins = <
745			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
746			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
747			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
748			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
749			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
750			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
751			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
752			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
753			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
754			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
755			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
756			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
757			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
758			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
759		>;
760	};
761
762	pinctrl_flexcan1: flexcan0grp {
763		fsl,pins = <
764			IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX			0x21
765			IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX			0x21
766		>;
767	};
768
769	pinctrl_flexcan2: flexcan1grp {
770		fsl,pins = <
771			IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX			0x21
772			IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX			0x21
773		>;
774	};
775
776	pinctrl_ioexp_rst: ioexprstgrp {
777		fsl,pins = <
778			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021
779		>;
780	};
781
782	pinctrl_isl29023: isl29023grp {
783		fsl,pins = <
784			IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02			0x00000021
785		>;
786	};
787
788	pinctrl_lpi2c1: lpi2c1grp {
789		fsl,pins = <
790			IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
791			IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
792		>;
793	};
794
795	pinctrl_lpuart0: lpuart0grp {
796		fsl,pins = <
797			IMX8QXP_UART0_RX_ADMA_UART0_RX				0x06000020
798			IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
799		>;
800	};
801
802	pinctrl_lpuart2: lpuart2grp {
803		fsl,pins = <
804			IMX8QXP_UART2_TX_ADMA_UART2_TX          0x06000020
805			IMX8QXP_UART2_RX_ADMA_UART2_RX          0x06000020
806		>;
807	};
808
809	pinctrl_lpuart3: lpuart3grp {
810		fsl,pins = <
811			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX       0x06000020
812			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX       0x06000020
813		>;
814	};
815
816	pinctrl_pcieb: pcieagrp {
817		fsl,pins = <
818			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
819			IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B		0x06000021
820			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
821		>;
822	};
823
824	pinctrl_typec: typecgrp {
825		fsl,pins = <
826			IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03                        0x06000021
827		>;
828	};
829
830	pinctrl_typec_mux: typecmuxgrp {
831		fsl,pins = <
832			IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09           0x60
833		>;
834	};
835
836	pinctrl_sai0: sai0grp {
837		fsl,pins = <
838			IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD		0x06000060
839			IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD		0x06000040
840			IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC		0x06000040
841			IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS	0x06000040
842		>;
843	};
844
845	pinctrl_sai1: sai1grp {
846		fsl,pins = <
847			IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD     0x06000040
848			IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC     0x06000040
849			IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS   0x06000040
850			IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD     0x06000060
851			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00   0x06000040
852		>;
853	};
854
855	pinctrl_usdhc1: usdhc1grp {
856		fsl,pins = <
857			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
858			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
859			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
860			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
861			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
862			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
863			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
864			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
865			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
866			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
867			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
868		>;
869	};
870
871	pinctrl_usdhc2: usdhc2grp {
872		fsl,pins = <
873			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
874			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
875			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
876			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
877			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
878			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
879			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
880		>;
881	};
882};
883