1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2024 NXP
4 *	Richard Zhu <hongxing.zhu@nxp.com>
5 */
6
7&hsio_subsys {
8	compatible = "simple-bus";
9	ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
10		 <0x40000000 0x0 0x60000000 0x10000000>,
11		 <0x80000000 0x0 0x70000000 0x10000000>;
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	pciea: pcie@5f000000 {
16		compatible = "fsl,imx8q-pcie";
17		reg = <0x5f000000 0x10000>,
18		      <0x4ff00000 0x80000>;
19		reg-names = "dbi", "config";
20		ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>,
21			 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>;
22		#interrupt-cells = <1>;
23		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
24		interrupt-names = "msi";
25		#address-cells = <3>;
26		#size-cells = <2>;
27		clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
28			 <&pciea_lpcg IMX_LPCG_CLK_4>,
29			 <&pciea_lpcg IMX_LPCG_CLK_5>;
30		clock-names = "dbi", "mstr", "slv";
31		bus-range = <0x00 0xff>;
32		device_type = "pci";
33		interrupt-map = <0 0 0 1 &gic 0 73 4>,
34				<0 0 0 2 &gic 0 74 4>,
35				<0 0 0 3 &gic 0 75 4>,
36				<0 0 0 4 &gic 0 76 4>;
37		interrupt-map-mask = <0 0 0 0x7>;
38		num-lanes = <1>;
39		num-viewport = <4>;
40		power-domains = <&pd IMX_SC_R_PCIE_A>;
41		fsl,max-link-speed = <3>;
42		status = "disabled";
43	};
44
45	pciea_ep: pcie-ep@5f000000 {
46		compatible = "fsl,imx8q-pcie-ep";
47		reg = <0x5f000000 0x00010000>,
48		      <0x40000000 0x10000000>;
49		reg-names = "dbi", "addr_space";
50		num-lanes = <1>;
51		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
52		interrupt-names = "dma";
53		clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
54			 <&pciea_lpcg IMX_LPCG_CLK_4>,
55			 <&pciea_lpcg IMX_LPCG_CLK_5>;
56		clock-names = "dbi", "mstr", "slv";
57		power-domains = <&pd IMX_SC_R_PCIE_A>;
58		fsl,max-link-speed = <3>;
59		num-ib-windows = <6>;
60		num-ob-windows = <6>;
61		status = "disabled";
62	};
63
64	pcieb: pcie@5f010000 {
65		compatible = "fsl,imx8q-pcie";
66		reg = <0x5f010000 0x10000>,
67		      <0x8ff00000 0x80000>;
68		reg-names = "dbi", "config";
69		ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
70			 <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
71		#interrupt-cells = <1>;
72		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
73			     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
74		interrupt-names = "msi", "dma";
75		#address-cells = <3>;
76		#size-cells = <2>;
77		clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
78			 <&pcieb_lpcg IMX_LPCG_CLK_4>,
79			 <&pcieb_lpcg IMX_LPCG_CLK_5>;
80		clock-names = "dbi", "mstr", "slv";
81		bus-range = <0x00 0xff>;
82		device_type = "pci";
83		interrupt-map = <0 0 0 1 &gic 0 105 4>,
84				<0 0 0 2 &gic 0 106 4>,
85				<0 0 0 3 &gic 0 107 4>,
86				<0 0 0 4 &gic 0 108 4>;
87		interrupt-map-mask = <0 0 0 0x7>;
88		num-lanes = <1>;
89		num-viewport = <4>;
90		power-domains = <&pd IMX_SC_R_PCIE_B>;
91		fsl,max-link-speed = <3>;
92		status = "disabled";
93	};
94
95	sata: sata@5f020000 {
96		compatible = "fsl,imx8qm-ahci";
97		reg = <0x5f020000 0x10000>;
98		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
99		clocks = <&sata_lpcg IMX_LPCG_CLK_4>,
100			 <&sata_crr4_lpcg IMX_LPCG_CLK_4>;
101		clock-names = "sata", "sata_ref";
102		phy-names = "sata-phy", "cali-phy0", "cali-phy1";
103		power-domains = <&pd IMX_SC_R_SATA_0>;
104		/*
105		 * Since "REXT" pin is only present for first lane PHY
106		 * and its calibration result will be stored, and shared
107		 * by the PHY used by SATA.
108		 *
109		 * Add the calibration PHYs for SATA here, although only
110		 * the third lane PHY is used by SATA.
111		 */
112		phys = <&hsio_phy 2 PHY_TYPE_SATA 0>,
113		       <&hsio_phy 0 PHY_TYPE_PCIE 0>,
114		       <&hsio_phy 1 PHY_TYPE_PCIE 1>;
115		status = "disabled";
116	};
117
118	pciea_lpcg: clock-controller@5f050000 {
119		compatible = "fsl,imx8qxp-lpcg";
120		reg = <0x5f050000 0x10000>;
121		clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
122		#clock-cells = <1>;
123		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
124		clock-output-names = "hsio_pciea_mstr_axi_clk",
125				     "hsio_pciea_slv_axi_clk",
126				     "hsio_pciea_dbi_axi_clk";
127		power-domains = <&pd IMX_SC_R_PCIE_A>;
128	};
129
130	sata_lpcg: clock-controller@5f070000 {
131		compatible = "fsl,imx8qxp-lpcg";
132		reg = <0x5f070000 0x10000>;
133		clocks = <&hsio_axi_clk>;
134		#clock-cells = <1>;
135		clock-indices = <IMX_LPCG_CLK_4>;
136		clock-output-names = "hsio_sata_clk";
137		power-domains = <&pd IMX_SC_R_SATA_0>;
138	};
139
140	phyx2_lpcg: clock-controller@5f080000 {
141		compatible = "fsl,imx8qxp-lpcg";
142		reg = <0x5f080000 0x10000>;
143		clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
144			 <&hsio_refa_clk>, <&hsio_per_clk>;
145		#clock-cells = <1>;
146		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
147				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
148		clock-output-names = "hsio_phyx2_pclk_0",
149				     "hsio_phyx2_pclk_1",
150				     "hsio_phyx2_apbclk_0",
151				     "hsio_phyx2_apbclk_1";
152		power-domains = <&pd IMX_SC_R_SERDES_0>;
153	};
154
155	phyx1_lpcg: clock-controller@5f090000 {
156		compatible = "fsl,imx8qxp-lpcg";
157		reg = <0x5f090000 0x10000>;
158		clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
159			 <&hsio_per_clk>, <&hsio_per_clk>;
160		#clock-cells = <1>;
161		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
162				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
163		clock-output-names = "hsio_phyx1_pclk",
164				     "hsio_phyx1_epcs_tx_clk",
165				     "hsio_phyx1_epcs_rx_clk",
166				     "hsio_phyx1_apb_clk";
167		power-domains = <&pd IMX_SC_R_SERDES_1>;
168	};
169
170	phyx2_crr0_lpcg: clock-controller@5f0a0000 {
171		compatible = "fsl,imx8qxp-lpcg";
172		reg = <0x5f0a0000 0x10000>;
173		clocks = <&hsio_per_clk>;
174		#clock-cells = <1>;
175		clock-indices = <IMX_LPCG_CLK_4>;
176		clock-output-names = "hsio_phyx2_per_clk";
177		power-domains = <&pd IMX_SC_R_SERDES_0>;
178	};
179
180	pciea_crr2_lpcg: clock-controller@5f0c0000 {
181		compatible = "fsl,imx8qxp-lpcg";
182		reg = <0x5f0c0000 0x10000>;
183		clocks = <&hsio_per_clk>;
184		#clock-cells = <1>;
185		clock-indices = <IMX_LPCG_CLK_4>;
186		clock-output-names = "hsio_pciea_per_clk";
187		power-domains = <&pd IMX_SC_R_PCIE_A>;
188	};
189
190	sata_crr4_lpcg: clock-controller@5f0e0000 {
191		compatible = "fsl,imx8qxp-lpcg";
192		reg = <0x5f0e0000 0x10000>;
193		clocks = <&hsio_per_clk>;
194		#clock-cells = <1>;
195		clock-indices = <IMX_LPCG_CLK_4>;
196		clock-output-names = "hsio_sata_per_clk";
197		power-domains = <&pd IMX_SC_R_SATA_0>;
198	};
199
200	hsio_phy: phy@5f180000 {
201		compatible = "fsl,imx8qm-hsio";
202		reg = <0x5f180000 0x30000>,
203		      <0x5f110000 0x20000>,
204		      <0x5f130000 0x30000>,
205		      <0x5f160000 0x10000>;
206		reg-names = "reg", "phy", "ctrl", "misc";
207		clocks = <&phyx2_lpcg IMX_LPCG_CLK_0>,
208			 <&phyx2_lpcg IMX_LPCG_CLK_1>,
209			 <&phyx2_lpcg IMX_LPCG_CLK_4>,
210			 <&phyx2_lpcg IMX_LPCG_CLK_5>,
211			 <&phyx1_lpcg IMX_LPCG_CLK_0>,
212			 <&phyx1_lpcg IMX_LPCG_CLK_1>,
213			 <&phyx1_lpcg IMX_LPCG_CLK_2>,
214			 <&phyx1_lpcg IMX_LPCG_CLK_4>,
215			 <&phyx2_crr0_lpcg IMX_LPCG_CLK_4>,
216			 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
217			 <&pciea_crr2_lpcg IMX_LPCG_CLK_4>,
218			 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
219			 <&sata_crr4_lpcg IMX_LPCG_CLK_4>,
220			 <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
221		clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1",
222			      "pclk2", "epcs_tx", "epcs_rx", "apb_pclk2",
223			      "phy0_crr", "phy1_crr", "ctl0_crr",
224			      "ctl1_crr", "ctl2_crr", "misc_crr";
225		#phy-cells = <3>;
226		power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>;
227		status = "disabled";
228	};
229};
230