1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx8qm.dtsi" 11 12/ { 13 model = "Freescale i.MX8QM MEK"; 14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 15 16 chosen { 17 stdout-path = &lpuart0; 18 }; 19 20 cpus { 21 /delete-node/ cpu-map; 22 /delete-node/ cpu@100; 23 /delete-node/ cpu@101; 24 }; 25 26 thermal-zones { 27 /delete-node/ cpu1-thermal; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 reg = <0x00000000 0x80000000 0 0x40000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 vdev0vring0: memory@90000000 { 41 reg = <0 0x90000000 0 0x8000>; 42 no-map; 43 }; 44 45 vdev0vring1: memory@90008000 { 46 reg = <0 0x90008000 0 0x8000>; 47 no-map; 48 }; 49 50 vdev1vring0: memory@90010000 { 51 reg = <0 0x90010000 0 0x8000>; 52 no-map; 53 }; 54 55 vdev1vring1: memory@90018000 { 56 reg = <0 0x90018000 0 0x8000>; 57 no-map; 58 }; 59 60 rsc_table0: memory@900ff000 { 61 reg = <0 0x900ff000 0 0x1000>; 62 no-map; 63 }; 64 65 vdev2vring0: memory@90100000 { 66 reg = <0 0x90100000 0 0x8000>; 67 no-map; 68 }; 69 70 vdev2vring1: memory@90108000 { 71 reg = <0 0x90108000 0 0x8000>; 72 no-map; 73 }; 74 75 vdev3vring0: memory@90110000 { 76 reg = <0 0x90110000 0 0x8000>; 77 no-map; 78 }; 79 80 vdev3vring1: memory@90118000 { 81 reg = <0 0x90118000 0 0x8000>; 82 no-map; 83 }; 84 85 rsc_table1: memory@901ff000 { 86 reg = <0 0x901ff000 0 0x1000>; 87 no-map; 88 }; 89 90 vdevbuffer: memory@90400000 { 91 compatible = "shared-dma-pool"; 92 reg = <0 0x90400000 0 0x100000>; 93 no-map; 94 }; 95 96 dsp_reserved: memory@92400000 { 97 reg = <0 0x92400000 0 0x1000000>; 98 no-map; 99 }; 100 101 dsp_vdev0vring0: memory@942f0000 { 102 reg = <0 0x942f0000 0 0x8000>; 103 no-map; 104 }; 105 106 dsp_vdev0vring1: memory@942f8000 { 107 reg = <0 0x942f8000 0 0x8000>; 108 no-map; 109 }; 110 111 dsp_vdev0buffer: memory@94300000 { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x94300000 0 0x100000>; 114 no-map; 115 }; 116 }; 117 118 lvds_backlight0: backlight-lvds0 { 119 compatible = "pwm-backlight"; 120 pwms = <&qm_pwm_lvds0 0 100000 0>; 121 brightness-levels = <0 100>; 122 num-interpolated-steps = <100>; 123 default-brightness-level = <80>; 124 }; 125 126 lvds_backlight1: backlight-lvds1 { 127 compatible = "pwm-backlight"; 128 pwms = <&pwm_lvds1 0 100000 0>; 129 brightness-levels = <0 100>; 130 num-interpolated-steps = <100>; 131 default-brightness-level = <80>; 132 }; 133 134 mux-controller { 135 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_typec_mux>; 138 select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; 139 enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 140 orientation-switch; 141 142 port { 143 usb3_data_ss: endpoint { 144 remote-endpoint = <&typec_con_ss>; 145 }; 146 }; 147 }; 148 149 reg_usdhc2_vmmc: usdhc2-vmmc { 150 compatible = "regulator-fixed"; 151 regulator-name = "SD1_SPWR"; 152 regulator-min-microvolt = <3000000>; 153 regulator-max-microvolt = <3000000>; 154 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; 155 enable-active-high; 156 }; 157 158 reg_audio: regulator-audio { 159 compatible = "regulator-fixed"; 160 regulator-name = "cs42888_supply"; 161 regulator-min-microvolt = <3300000>; 162 regulator-max-microvolt = <3300000>; 163 }; 164 165 reg_fec2_supply: regulator-fec2-nvcc { 166 compatible = "regulator-fixed"; 167 regulator-name = "fec2_nvcc"; 168 regulator-min-microvolt = <1800000>; 169 regulator-max-microvolt = <1800000>; 170 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 171 enable-active-high; 172 }; 173 174 reg_can01_en: regulator-can01-gen { 175 compatible = "regulator-fixed"; 176 regulator-name = "can01-en"; 177 regulator-min-microvolt = <3300000>; 178 regulator-max-microvolt = <3300000>; 179 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 180 enable-active-high; 181 }; 182 183 reg_can2_en: regulator-can2-gen { 184 compatible = "regulator-fixed"; 185 regulator-name = "can2-en"; 186 regulator-min-microvolt = <3300000>; 187 regulator-max-microvolt = <3300000>; 188 gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; 189 enable-active-high; 190 }; 191 192 reg_can01_stby: regulator-can01-stby { 193 compatible = "regulator-fixed"; 194 regulator-name = "can01-stby"; 195 regulator-min-microvolt = <3300000>; 196 regulator-max-microvolt = <3300000>; 197 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 198 enable-active-high; 199 vin-supply = <®_can01_en>; 200 }; 201 202 reg_can2_stby: regulator-can2-stby { 203 compatible = "regulator-fixed"; 204 regulator-name = "can2-stby"; 205 regulator-min-microvolt = <3300000>; 206 regulator-max-microvolt = <3300000>; 207 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 208 enable-active-high; 209 vin-supply = <®_can2_en>; 210 }; 211 212 reg_pciea: regulator-pcie { 213 compatible = "regulator-fixed"; 214 pinctrl-0 = <&pinctrl_pciea_reg>; 215 pinctrl-names = "default"; 216 regulator-max-microvolt = <3300000>; 217 regulator-min-microvolt = <3300000>; 218 regulator-name = "mpcie_3v3"; 219 gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; 220 enable-active-high; 221 }; 222 223 reg_vref_1v8: regulator-adc-vref { 224 compatible = "regulator-fixed"; 225 regulator-name = "vref_1v8"; 226 regulator-min-microvolt = <1800000>; 227 regulator-max-microvolt = <1800000>; 228 }; 229 230 reg_audio_5v: regulator-audio-pwr { 231 compatible = "regulator-fixed"; 232 regulator-name = "audio-5v"; 233 regulator-min-microvolt = <5000000>; 234 regulator-max-microvolt = <5000000>; 235 regulator-always-on; 236 regulator-boot-on; 237 }; 238 239 reg_audio_3v3: regulator-audio-3v3 { 240 compatible = "regulator-fixed"; 241 regulator-name = "audio-3v3"; 242 regulator-min-microvolt = <3300000>; 243 regulator-max-microvolt = <3300000>; 244 regulator-always-on; 245 regulator-boot-on; 246 }; 247 248 reg_audio_1v8: regulator-audio-1v8 { 249 compatible = "regulator-fixed"; 250 regulator-name = "audio-1v8"; 251 regulator-min-microvolt = <1800000>; 252 regulator-max-microvolt = <1800000>; 253 regulator-always-on; 254 regulator-boot-on; 255 }; 256 257 bt_sco_codec: audio-codec-bt { 258 compatible = "linux,bt-sco"; 259 #sound-dai-cells = <1>; 260 }; 261 262 sound-bt-sco { 263 compatible = "simple-audio-card"; 264 simple-audio-card,name = "bt-sco-audio"; 265 simple-audio-card,format = "dsp_a"; 266 simple-audio-card,bitclock-inversion; 267 simple-audio-card,frame-master = <&btcpu>; 268 simple-audio-card,bitclock-master = <&btcpu>; 269 270 btcpu: simple-audio-card,cpu { 271 sound-dai = <&sai0>; 272 dai-tdm-slot-num = <2>; 273 dai-tdm-slot-width = <16>; 274 }; 275 276 simple-audio-card,codec { 277 sound-dai = <&bt_sco_codec 1>; 278 }; 279 }; 280 281 sound-cs42888 { 282 compatible = "fsl,imx-audio-cs42888"; 283 model = "imx-cs42888"; 284 audio-cpu = <&esai0>; 285 audio-codec = <&cs42888>; 286 audio-asrc = <&asrc0>; 287 audio-routing = "Line Out Jack", "AOUT1L", 288 "Line Out Jack", "AOUT1R", 289 "Line Out Jack", "AOUT2L", 290 "Line Out Jack", "AOUT2R", 291 "Line Out Jack", "AOUT3L", 292 "Line Out Jack", "AOUT3R", 293 "Line Out Jack", "AOUT4L", 294 "Line Out Jack", "AOUT4R", 295 "AIN1L", "Line In Jack", 296 "AIN1R", "Line In Jack", 297 "AIN2L", "Line In Jack", 298 "AIN2R", "Line In Jack"; 299 }; 300 301 sound-wm8960 { 302 compatible = "fsl,imx-audio-wm8960"; 303 model = "wm8960-audio"; 304 audio-cpu = <&sai1>; 305 audio-codec = <&wm8960>; 306 hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 307 audio-routing = "Headphone Jack", "HP_L", 308 "Headphone Jack", "HP_R", 309 "Ext Spk", "SPK_LP", 310 "Ext Spk", "SPK_LN", 311 "Ext Spk", "SPK_RP", 312 "Ext Spk", "SPK_RN", 313 "LINPUT1", "Mic Jack", 314 "Mic Jack", "MICB"; 315 }; 316 317 imx8qm-cm4-0 { 318 compatible = "fsl,imx8qm-cm4"; 319 clocks = <&clk_dummy>; 320 mbox-names = "tx", "rx", "rxdb"; 321 mboxes = <&lsio_mu5 0 1 322 &lsio_mu5 1 1 323 &lsio_mu5 3 1>; 324 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 325 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; 326 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 327 328 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 329 fsl,entry-address = <0x34fe0000>; 330 }; 331 332 imx8qm-cm4-1 { 333 compatible = "fsl,imx8qm-cm4"; 334 clocks = <&clk_dummy>; 335 mbox-names = "tx", "rx", "rxdb"; 336 mboxes = <&lsio_mu6 0 1 337 &lsio_mu6 1 1 338 &lsio_mu6 3 1>; 339 memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, 340 <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; 341 power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>; 342 343 fsl,resource-id = <IMX_SC_R_M4_1_PID0>; 344 fsl,entry-address = <0x38fe0000>; 345 }; 346 347}; 348 349&adc0 { 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_adc0>; 352 vref-supply = <®_vref_1v8>; 353 status = "okay"; 354}; 355 356&amix { 357 status = "okay"; 358}; 359 360&asrc0 { 361 fsl,asrc-rate = <48000>; 362 status = "okay"; 363}; 364 365&cm41_i2c { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clock-frequency = <100000>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_cm41_i2c>; 371 status = "okay"; 372 373 pca6416: gpio@20 { 374 compatible = "ti,tca6416"; 375 reg = <0x20>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 }; 379 380 cs42888: audio-codec@48 { 381 compatible = "cirrus,cs42888"; 382 reg = <0x48>; 383 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 384 clock-names = "mclk"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_cs42888_reset>; 387 VA-supply = <®_audio>; 388 VD-supply = <®_audio>; 389 VLS-supply = <®_audio>; 390 VLC-supply = <®_audio>; 391 reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; 392 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 393 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 394 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 395 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 396 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 397 }; 398}; 399 400&cm41_intmux { 401 status = "okay"; 402}; 403 404&esai0 { 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_esai0>; 407 assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 408 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 409 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 410 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 411 <&esai0_lpcg IMX_LPCG_CLK_4>; 412 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 413 assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 414 status = "okay"; 415}; 416 417&hsio_phy { 418 fsl,hsio-cfg = "pciea-pcieb-sata"; 419 fsl,refclk-pad-mode = "input"; 420 status = "okay"; 421}; 422 423&i2c0 { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clock-frequency = <100000>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_i2c0>; 429 status = "okay"; 430 431 accelerometer@19 { 432 compatible = "st,lsm303agr-accel"; 433 reg = <0x19>; 434 }; 435 436 gyrometer@20 { 437 compatible = "nxp,fxas21002c"; 438 reg = <0x20>; 439 }; 440 441 light-sensor@44 { 442 compatible = "isil,isl29023"; 443 reg = <0x44>; 444 interrupt-parent = <&lsio_gpio4>; 445 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 446 }; 447 448 pressure-sensor@60 { 449 compatible = "fsl,mpl3115"; 450 reg = <0x60>; 451 }; 452 453 max7322: gpio@68 { 454 compatible = "maxim,max7322"; 455 reg = <0x68>; 456 gpio-controller; 457 #gpio-cells = <2>; 458 }; 459 460 gyrometer@69 { 461 compatible = "st,l3g4200d-gyro"; 462 reg = <0x69>; 463 }; 464 465 ptn5110: tcpc@51 { 466 compatible = "nxp,ptn5110", "tcpci"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_typec>; 469 reg = <0x51>; 470 interrupt-parent = <&lsio_gpio4>; 471 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 472 status = "okay"; 473 474 usb_con1: connector { 475 compatible = "usb-c-connector"; 476 label = "USB-C"; 477 power-role = "source"; 478 data-role = "dual"; 479 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 480 481 ports { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 port@0 { 486 reg = <0>; 487 488 typec_dr_sw: endpoint { 489 remote-endpoint = <&usb3_drd_sw>; 490 }; 491 }; 492 493 port@1 { 494 reg = <1>; 495 typec_con_ss: endpoint { 496 remote-endpoint = <&usb3_data_ss>; 497 }; 498 }; 499 }; 500 }; 501 }; 502}; 503 504&i2c1 { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 clock-frequency = <100000>; 508 pinctrl-names = "default", "gpio"; 509 pinctrl-0 = <&pinctrl_i2c1>; 510 pinctrl-1 = <&pinctrl_i2c1_gpio>; 511 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 512 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 513 status = "okay"; 514 515 wm8960: audio-codec@1a { 516 compatible = "wlf,wm8960"; 517 reg = <0x1a>; 518 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 519 clock-names = "mclk"; 520 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 521 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 522 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 523 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 524 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 525 wlf,shared-lrclk; 526 wlf,hp-cfg = <2 2 3>; 527 wlf,gpio-cfg = <1 3>; 528 AVDD-supply = <®_audio_3v3>; 529 DBVDD-supply = <®_audio_1v8>; 530 DCVDD-supply = <®_audio_1v8>; 531 SPKVDD1-supply = <®_audio_5v>; 532 SPKVDD2-supply = <®_audio_5v>; 533 }; 534}; 535 536&i2c1_lvds0 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; 539 clock-frequency = <100000>; 540 status = "okay"; 541}; 542 543&i2c1_lvds1 { 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; 546 clock-frequency = <100000>; 547 status = "okay"; 548}; 549 550&i2c0_mipi0 { 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; 553 clock-frequency = <100000>; 554 status = "okay"; 555}; 556 557&i2c0_mipi1 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; 560 clock-frequency = <100000>; 561 status = "okay"; 562}; 563 564&flexcan1 { 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_flexcan1>; 567 xceiver-supply = <®_can01_stby>; 568 status = "okay"; 569}; 570 571&flexcan2 { 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_flexcan2>; 574 xceiver-supply = <®_can01_stby>; 575 status = "okay"; 576}; 577 578&flexcan3 { 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pinctrl_flexcan3>; 581 xceiver-supply = <®_can2_stby>; 582 status = "okay"; 583}; 584 585&lpuart0 { 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_lpuart0>; 588 status = "okay"; 589}; 590 591&lpuart2 { 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_lpuart2>; 594 status = "okay"; 595}; 596 597&lpuart3 { 598 pinctrl-names = "default"; 599 pinctrl-0 = <&pinctrl_lpuart3>; 600 status = "okay"; 601}; 602 603&lpspi2 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; 608 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 609 status = "okay"; 610}; 611 612&lsio_mu5 { 613 status = "okay"; 614}; 615 616&lsio_mu6 { 617 status = "okay"; 618}; 619 620&flexspi0 { 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_flexspi0>; 623 status = "okay"; 624 625 flash0: flash@0 { 626 reg = <0>; 627 #address-cells = <1>; 628 #size-cells = <1>; 629 compatible = "jedec,spi-nor"; 630 spi-max-frequency = <133000000>; 631 spi-tx-bus-width = <8>; 632 spi-rx-bus-width = <8>; 633 }; 634}; 635 636&fec1 { 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_fec1>; 639 phy-mode = "rgmii-id"; 640 phy-handle = <ðphy0>; 641 fsl,magic-packet; 642 status = "okay"; 643 644 mdio { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 ethphy0: ethernet-phy@0 { 649 compatible = "ethernet-phy-ieee802.3-c22"; 650 reg = <0>; 651 }; 652 653 ethphy1: ethernet-phy@1 { 654 compatible = "ethernet-phy-ieee802.3-c22"; 655 reg = <1>; 656 }; 657 }; 658}; 659 660&fec2 { 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_fec2>; 663 phy-mode = "rgmii-txid"; 664 phy-handle = <ðphy1>; 665 phy-supply = <®_fec2_supply>; 666 nvmem-cells = <&fec_mac1>; 667 nvmem-cell-names = "mac-address"; 668 rx-internal-delay-ps = <2000>; 669 fsl,magic-packet; 670 status = "okay"; 671}; 672 673&pciea { 674 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 675 phy-names = "pcie-phy"; 676 pinctrl-0 = <&pinctrl_pciea>; 677 pinctrl-names = "default"; 678 reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; 679 vpcie-supply = <®_pciea>; 680 status = "okay"; 681}; 682 683&pcieb { 684 phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; 685 phy-names = "pcie-phy"; 686 pinctrl-0 = <&pinctrl_pcieb>; 687 pinctrl-names = "default"; 688 reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; 689 status = "disabled"; 690}; 691 692&qm_pwm_lvds0 { 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_pwm_lvds0>; 695 status = "okay"; 696}; 697 698&pwm_lvds1 { 699 pinctrl-names = "default"; 700 pinctrl-0 = <&pinctrl_pwm_lvds1>; 701 status = "okay"; 702}; 703 704&usdhc1 { 705 pinctrl-names = "default"; 706 pinctrl-0 = <&pinctrl_usdhc1>; 707 bus-width = <8>; 708 no-sd; 709 no-sdio; 710 non-removable; 711 status = "okay"; 712}; 713 714&usdhc2 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_usdhc2>; 717 bus-width = <4>; 718 vmmc-supply = <®_usdhc2_vmmc>; 719 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 720 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 721 status = "okay"; 722}; 723 724&usb3_phy { 725 status = "okay"; 726}; 727 728&usbotg3 { 729 status = "okay"; 730}; 731 732&usbotg3_cdns3 { 733 dr_mode = "otg"; 734 usb-role-switch; 735 status = "okay"; 736 737 port { 738 usb3_drd_sw: endpoint { 739 remote-endpoint = <&typec_dr_sw>; 740 }; 741 }; 742}; 743 744&sai0 { 745 #sound-dai-cells = <0>; 746 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 747 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 748 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 749 <&sai0_lpcg IMX_LPCG_CLK_4>; 750 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pinctrl_sai0>; 753 status = "okay"; 754}; 755 756&sai1 { 757 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 758 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 759 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 760 <&sai1_lpcg IMX_LPCG_CLK_4>; 761 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 762 pinctrl-names = "default"; 763 pinctrl-0 = <&pinctrl_sai1>; 764 status = "okay"; 765}; 766 767&sai6 { 768 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 769 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 770 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 771 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 772 <&sai6_lpcg IMX_LPCG_CLK_4>; 773 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 774 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 775 fsl,sai-asynchronous; 776 status = "okay"; 777}; 778 779&sai7 { 780 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 781 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 782 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 783 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 784 <&sai7_lpcg IMX_LPCG_CLK_4>; 785 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 786 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 787 fsl,sai-asynchronous; 788 status = "okay"; 789}; 790 791&sata { 792 status = "okay"; 793}; 794 795&vpu_dsp { 796 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 797 <&dsp_vdev0vring1>, <&dsp_reserved>; 798 status = "okay"; 799}; 800 801&iomuxc { 802 pinctrl-names = "default"; 803 pinctrl-0 = <&pinctrl_hog>; 804 805 pinctrl_hog: hoggrp { 806 fsl,pins = < 807 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 808 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 809 >; 810 }; 811 812 pinctrl_cs42888_reset: cs42888_resetgrp { 813 fsl,pins = < 814 IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c 815 >; 816 }; 817 818 pinctrl_i2c0: i2c0grp { 819 fsl,pins = < 820 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 821 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 822 >; 823 }; 824 825 pinctrl_i2c1: i2c1grp { 826 fsl,pins = < 827 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c 828 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c 829 >; 830 }; 831 832 pinctrl_i2c1_gpio: i2c1gpio-grp { 833 fsl,pins = < 834 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c 835 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c 836 >; 837 }; 838 839 pinctrl_adc0: adc0grp { 840 fsl,pins = < 841 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 842 >; 843 }; 844 845 pinctrl_cm41_i2c: cm41i2cgrp { 846 fsl,pins = < 847 IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c 848 IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c 849 >; 850 }; 851 852 pinctrl_esai0: esai0grp { 853 fsl,pins = < 854 IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 855 IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 856 IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 857 IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 858 IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 859 IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 860 IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 861 IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 862 IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 863 IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 864 >; 865 }; 866 867 pinctrl_fec1: fec1grp { 868 fsl,pins = < 869 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 870 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 871 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 872 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 873 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 874 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 875 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 876 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 877 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 878 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 879 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 880 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 881 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 882 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 883 >; 884 }; 885 886 pinctrl_lpspi2: lpspi2grp { 887 fsl,pins = < 888 IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 889 IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 890 IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 891 >; 892 }; 893 894 pinctrl_lpspi2_cs: lpspi2csgrp { 895 fsl,pins = < 896 IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 897 >; 898 }; 899 900 pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { 901 fsl,pins = < 902 IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 903 IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 904 IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 905 >; 906 }; 907 908 pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { 909 fsl,pins = < 910 IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 911 IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 912 IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 913 >; 914 }; 915 916 pinctrl_flexspi0: flexspi0grp { 917 fsl,pins = < 918 IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 919 IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 920 IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 921 IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 922 IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 923 IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 924 IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 925 IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 926 IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 927 IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 928 IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 929 IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 930 IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 931 IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 932 IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 933 IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 934 >; 935 }; 936 937 pinctrl_fec2: fec2grp { 938 fsl,pins = < 939 IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 940 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 941 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 942 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 943 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 944 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 945 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 946 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 947 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 948 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 949 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 950 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 951 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 952 >; 953 }; 954 955 pinctrl_flexcan1: flexcan0grp { 956 fsl,pins = < 957 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 958 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 959 >; 960 }; 961 962 pinctrl_flexcan2: flexcan1grp { 963 fsl,pins = < 964 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 965 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 966 >; 967 }; 968 969 pinctrl_flexcan3: flexcan3grp { 970 fsl,pins = < 971 IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 972 IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 973 >; 974 }; 975 976 pinctrl_lpuart0: lpuart0grp { 977 fsl,pins = < 978 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 979 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 980 >; 981 }; 982 983 pinctrl_lpuart2: lpuart2grp { 984 fsl,pins = < 985 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 986 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 987 >; 988 }; 989 990 pinctrl_lpuart3: lpuart3grp { 991 fsl,pins = < 992 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 993 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 994 >; 995 }; 996 997 pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { 998 fsl,pins = < 999 IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c 1000 IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c 1001 >; 1002 }; 1003 1004 pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { 1005 fsl,pins = < 1006 IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c 1007 IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c 1008 >; 1009 }; 1010 1011 pinctrl_pciea: pcieagrp { 1012 fsl,pins = < 1013 IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 1014 IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 1015 IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 1016 >; 1017 }; 1018 1019 pinctrl_pciea_reg: pcieareggrp { 1020 fsl,pins = < 1021 IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 1022 >; 1023 }; 1024 1025 pinctrl_pcieb: pciebgrp { 1026 fsl,pins = < 1027 IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 1028 IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 1029 IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 1030 >; 1031 }; 1032 1033 pinctrl_pwm_lvds0: pwmlvds0grp { 1034 fsl,pins = < 1035 IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 1036 >; 1037 }; 1038 1039 pinctrl_pwm_lvds1: pwmlvds1grp { 1040 fsl,pins = < 1041 IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 1042 >; 1043 }; 1044 1045 pinctrl_sai0: sai0grp { 1046 fsl,pins = < 1047 IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c 1048 IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c 1049 IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c 1050 IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c 1051 >; 1052 }; 1053 1054 pinctrl_sai1: sai1grp { 1055 fsl,pins = < 1056 IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 1057 IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 1058 IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 1059 IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 1060 >; 1061 }; 1062 1063 pinctrl_typec: typecgrp { 1064 fsl,pins = < 1065 IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 1066 >; 1067 }; 1068 1069 pinctrl_typec_mux: typecmuxgrp { 1070 fsl,pins = < 1071 IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 1072 IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 1073 >; 1074 }; 1075 1076 pinctrl_usdhc1: usdhc1grp { 1077 fsl,pins = < 1078 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 1079 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 1080 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 1081 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 1082 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 1083 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 1084 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 1085 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 1086 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 1087 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 1088 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 1089 >; 1090 }; 1091 1092 pinctrl_usdhc2: usdhc2grp { 1093 fsl,pins = < 1094 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 1095 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 1096 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 1097 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 1098 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 1099 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 1100 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 1101 >; 1102 }; 1103}; 1104