1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2024 Variscite Ltd.
4 *
5 * Author: Tarang Raval <tarang.raval@siliconsignals.io>
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/phy/phy-imx8-pcie.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/usb/pd.h>
13#include "imx8mp.dtsi"
14
15/ {
16	model = "Variscite VAR-SOM-MX8M Plus module";
17
18	chosen {
19		stdout-path = &uart2;
20	};
21
22	gpio-leds {
23	        compatible = "gpio-leds";
24
25	        led-0 {
26	                function = LED_FUNCTION_POWER;
27	                gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
28	                linux,default-trigger = "heartbeat";
29	        };
30	};
31
32	memory@40000000 {
33		device_type = "memory";
34		reg = <0x0 0x40000000 0 0xc0000000>,
35		      <0x1 0x00000000 0 0xc0000000>;
36	};
37
38	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
39	        compatible = "regulator-fixed";
40	        regulator-name = "VSD_3V3";
41	        regulator-min-microvolt = <3300000>;
42	        regulator-max-microvolt = <3300000>;
43	        gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
44	        enable-active-high;
45	        startup-delay-us = <100>;
46	        off-on-delay-us = <12000>;
47	};
48
49	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
50		compatible = "regulator-gpio";
51		regulator-name = "VSD_VSEL";
52		regulator-min-microvolt = <1800000>;
53		regulator-max-microvolt = <3300000>;
54		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
55		states = <3300000 0x0 1800000 0x1>;
56		vin-supply = <&ldo5>;
57	};
58};
59
60&A53_0 {
61	cpu-supply = <&buck2>;
62};
63
64&A53_1 {
65	cpu-supply = <&buck2>;
66};
67
68&A53_2 {
69	cpu-supply = <&buck2>;
70};
71
72&A53_3 {
73	cpu-supply = <&buck2>;
74};
75
76&i2c1 {
77	clock-frequency = <400000>;
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_i2c1>;
80	status = "okay";
81
82	pmic@25 {
83		compatible = "nxp,pca9450c";
84		reg = <0x25>;
85		pinctrl-names = "default";
86		pinctrl-0 = <&pinctrl_pmic>;
87		interrupt-parent = <&gpio5>;
88		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
89
90		regulators {
91			buck1: BUCK1 {
92				regulator-name = "BUCK1";
93				regulator-min-microvolt = <600000>;
94				regulator-max-microvolt = <2187500>;
95				regulator-boot-on;
96				regulator-always-on;
97				regulator-ramp-delay = <3125>;
98			};
99
100			buck2: BUCK2 {
101				regulator-name = "BUCK2";
102				regulator-min-microvolt = <600000>;
103				regulator-max-microvolt = <2187500>;
104				regulator-boot-on;
105				regulator-always-on;
106				regulator-ramp-delay = <3125>;
107				nxp,dvs-run-voltage = <950000>;
108				nxp,dvs-standby-voltage = <850000>;
109			};
110
111			buck4: BUCK4 {
112				regulator-name = "BUCK4";
113				regulator-min-microvolt = <600000>;
114				regulator-max-microvolt = <3400000>;
115				regulator-boot-on;
116				regulator-always-on;
117			};
118
119			buck5: BUCK5 {
120				regulator-name = "BUCK5";
121				regulator-min-microvolt = <600000>;
122				regulator-max-microvolt = <3400000>;
123				regulator-boot-on;
124				regulator-always-on;
125			};
126
127			buck6: BUCK6 {
128				regulator-name = "BUCK6";
129				regulator-min-microvolt = <600000>;
130				regulator-max-microvolt = <3400000>;
131				regulator-boot-on;
132				regulator-always-on;
133			};
134
135			ldo1: LDO1 {
136				regulator-name = "LDO1";
137				regulator-min-microvolt = <1600000>;
138				regulator-max-microvolt = <3300000>;
139				regulator-boot-on;
140				regulator-always-on;
141			};
142
143			ldo2: LDO2 {
144				regulator-name = "LDO2";
145				regulator-min-microvolt = <800000>;
146				regulator-max-microvolt = <1150000>;
147				regulator-boot-on;
148				regulator-always-on;
149			};
150
151			ldo3: LDO3 {
152				regulator-name = "LDO3";
153				regulator-min-microvolt = <800000>;
154				regulator-max-microvolt = <3300000>;
155				regulator-boot-on;
156				regulator-always-on;
157			};
158
159			ldo4: LDO4 {
160				regulator-name = "LDO4";
161				regulator-min-microvolt = <1800000>;
162				regulator-max-microvolt = <1800000>;
163				regulator-always-on;
164			};
165
166			ldo5: LDO5 {
167				regulator-name = "LDO5";
168				regulator-min-microvolt = <1800000>;
169				regulator-max-microvolt = <3300000>;
170			};
171		};
172	};
173};
174
175&i2c3 {
176        clock-frequency = <400000>;
177        pinctrl-names = "default";
178        pinctrl-0 = <&pinctrl_i2c3>;
179        status = "okay";
180
181	/* GPIO expander */
182	pca9534: gpio@20 {
183	        compatible = "nxp,pca9534";
184	        reg = <0x20>;
185	        pinctrl-names = "default";
186	        pinctrl-0 = <&pinctrl_pca9534>;
187	        gpio-controller;
188	        #gpio-cells = <2>;
189	        interrupt-parent = <&gpio1>;
190	        interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
191	        wakeup-source;
192
193	        usb3-sata-sel-hog {
194	                gpio-hog;
195	                gpios = <4 0>;
196	                output-low;
197	                line-name = "usb3_sata_sel";
198	        };
199	};
200};
201
202/* Console */
203&uart2 {
204        pinctrl-names = "default";
205        pinctrl-0 = <&pinctrl_uart2>;
206        status = "okay";
207};
208
209/* SD-card */
210&usdhc2 {
211        pinctrl-names = "default", "state_100mhz", "state_200mhz";
212        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
213        pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
214        pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
215        cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
216        vmmc-supply = <&reg_usdhc2_vmmc>;
217	vqmmc-supply = <&reg_usdhc2_vqmmc>;
218        bus-width = <4>;
219        status = "okay";
220};
221
222/* eMMC */
223&usdhc3 {
224	pinctrl-names = "default", "state_100mhz", "state_200mhz";
225	pinctrl-0 = <&pinctrl_usdhc3>;
226	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
227	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
228	bus-width = <8>;
229	non-removable;
230	status = "okay";
231};
232
233&wdog1 {
234	pinctrl-names = "default";
235	pinctrl-0 = <&pinctrl_wdog>;
236	fsl,ext-reset-output;
237	status = "okay";
238};
239
240&iomuxc {
241
242	pinctrl_i2c1: i2c1grp {
243		fsl,pins = <
244			MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL				0x400001c2
245			MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA				0x400001c2
246		>;
247	};
248
249	pinctrl_i2c3: i2c3grp {
250	        fsl,pins = <
251	                MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2
252	                MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2
253	        >;
254	};
255
256	pinctrl_pca9534: pca9534grp {
257	        fsl,pins = <
258	                MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
259	        >;
260	};
261
262	pinctrl_pmic: pmicgrp {
263		fsl,pins = <
264			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04				0x1c0
265		>;
266	};
267
268	pinctrl_uart2: uart2grp {
269	        fsl,pins = <
270		        MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40
271			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x40
272		>;
273	};
274
275	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
276	        fsl,pins = <
277	                MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                             0x1c4
278	                MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                               0x10
279	                MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12                               0xc0
280	        >;
281	};
282
283	pinctrl_usdhc2: usdhc2grp {
284	        fsl,pins = <
285	                MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x190
286	                MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d0
287	                MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d0
288	                MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d0
289	                MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d0
290	                MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d0
291	        >;
292	};
293
294	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
295	        fsl,pins = <
296	                MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x194
297	                MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d4
298	                MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d4
299	                MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d4
300	                MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d4
301	                MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d4
302	        >;
303	};
304
305	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
306	        fsl,pins = <
307	                MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x196
308	                MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d6
309	                MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d6
310	                MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d6
311	                MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d6
312	                MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d6
313	        >;
314	};
315
316	pinctrl_usdhc3: usdhc3grp {
317		fsl,pins = <
318			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
319			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
320			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
321			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
322			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
323			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
324			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
325			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
326			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
327			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
328			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
329		>;
330	};
331
332	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
333		fsl,pins = <
334			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
335			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
336			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
337			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
338			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
339			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
340			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
341			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
342			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
343			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
344			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
345		>;
346	};
347
348	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
349		fsl,pins = <
350			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
351			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
352			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
353			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
354			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
355			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
356			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
357			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
358			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
359			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
360			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
361		>;
362	};
363
364	pinctrl_wdog: wdoggrp {
365		fsl,pins = <
366			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
367		>;
368	};
369};
370