1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
12	compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
13
14	memory@40000000 {
15		device_type = "memory";
16		reg = <0x0 0x40000000 0 0x80000000>;
17	};
18
19	/* identical to buck4_reg, but should never change */
20	reg_vcc3v3: regulator-vcc3v3 {
21		compatible = "regulator-fixed";
22		regulator-name = "VCC3V3";
23		regulator-min-microvolt = <3300000>;
24		regulator-max-microvolt = <3300000>;
25		regulator-always-on;
26	};
27};
28
29&A53_0 {
30	cpu-supply = <&buck2_reg>;
31};
32
33&flexspi {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_flexspi0>;
36	status = "okay";
37
38	flash0: flash@0 {
39		reg = <0>;
40		compatible = "jedec,spi-nor";
41		spi-max-frequency = <80000000>;
42		spi-tx-bus-width = <1>;
43		spi-rx-bus-width = <4>;
44		vcc-supply = <&buck5_reg>;
45
46		partitions {
47			compatible = "fixed-partitions";
48			#address-cells = <1>;
49			#size-cells = <1>;
50		};
51	};
52};
53
54&i2c1 {
55	clock-frequency = <384000>;
56	pinctrl-names = "default", "gpio";
57	pinctrl-0 = <&pinctrl_i2c1>;
58	pinctrl-1 = <&pinctrl_i2c1_gpio>;
59	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
60	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
61	status = "okay";
62
63	se97: temperature-sensor@1b {
64		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
65		reg = <0x1b>;
66	};
67
68	pmic: pmic@25 {
69		reg = <0x25>;
70		compatible = "nxp,pca9450c";
71
72		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
73		pinctrl-0 = <&pinctrl_pmic>;
74		pinctrl-names = "default";
75		interrupt-parent = <&gpio1>;
76		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
77
78		regulators {
79			/* V_0V85_SOC: 0.85 .. 0.95 */
80			buck1_reg: BUCK1 {
81				regulator-name = "BUCK1";
82				regulator-min-microvolt = <850000>;
83				regulator-max-microvolt = <950000>;
84				regulator-boot-on;
85				regulator-always-on;
86				regulator-ramp-delay = <3125>;
87			};
88
89			/* VDD_ARM */
90			buck2_reg: BUCK2 {
91				regulator-name = "BUCK2";
92				regulator-min-microvolt = <850000>;
93				regulator-max-microvolt = <1000000>;
94				regulator-boot-on;
95				regulator-always-on;
96				nxp,dvs-run-voltage = <950000>;
97				nxp,dvs-standby-voltage = <850000>;
98				regulator-ramp-delay = <3125>;
99			};
100
101			/* VCC3V3 -> VMMC, ... must not be changed */
102			buck4_reg: BUCK4 {
103				regulator-name = "BUCK4";
104				regulator-min-microvolt = <3300000>;
105				regulator-max-microvolt = <3300000>;
106				regulator-boot-on;
107				regulator-always-on;
108			};
109
110			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
111			buck5_reg: BUCK5 {
112				regulator-name = "BUCK5";
113				regulator-min-microvolt = <1800000>;
114				regulator-max-microvolt = <1800000>;
115				regulator-boot-on;
116				regulator-always-on;
117			};
118
119			/* V_1V1 -> RAM, ... must not be changed */
120			buck6_reg: BUCK6 {
121				regulator-name = "BUCK6";
122				regulator-min-microvolt = <1100000>;
123				regulator-max-microvolt = <1100000>;
124				regulator-boot-on;
125				regulator-always-on;
126			};
127
128			/* V_1V8_SNVS */
129			ldo1_reg: LDO1 {
130				regulator-name = "LDO1";
131				regulator-min-microvolt = <1800000>;
132				regulator-max-microvolt = <1800000>;
133				regulator-boot-on;
134				regulator-always-on;
135			};
136
137			/* V_1V8_ANA */
138			ldo3_reg: LDO3 {
139				regulator-name = "LDO3";
140				regulator-min-microvolt = <1800000>;
141				regulator-max-microvolt = <1800000>;
142				regulator-boot-on;
143				regulator-always-on;
144			};
145
146			/* unused */
147			ldo4_reg: LDO4 {
148				regulator-name = "LDO4";
149				regulator-min-microvolt = <800000>;
150				regulator-max-microvolt = <3300000>;
151			};
152
153			/* VCC SD IO - switched using SD2 VSELECT */
154			ldo5_reg: LDO5 {
155				regulator-name = "LDO5";
156				regulator-min-microvolt = <1800000>;
157				regulator-max-microvolt = <3300000>;
158			};
159		};
160	};
161
162	pcf85063: rtc@51 {
163		compatible = "nxp,pcf85063a";
164		reg = <0x51>;
165	};
166
167	at24c02: eeprom@53 {
168		compatible = "nxp,se97b", "atmel,24c02";
169		read-only;
170		reg = <0x53>;
171		pagesize = <16>;
172		vcc-supply = <&reg_vcc3v3>;
173	};
174
175	m24c64: eeprom@57 {
176		compatible = "atmel,24c64";
177		reg = <0x57>;
178		pagesize = <32>;
179		vcc-supply = <&reg_vcc3v3>;
180	};
181};
182
183&usdhc3 {
184	pinctrl-names = "default", "state_100mhz", "state_200mhz";
185	pinctrl-0 = <&pinctrl_usdhc3>;
186	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
187	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
188	bus-width = <8>;
189	non-removable;
190	no-sd;
191	no-sdio;
192	vmmc-supply = <&reg_vcc3v3>;
193	vqmmc-supply = <&buck5_reg>;
194	status = "okay";
195};
196
197&wdog1 {
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_wdog>;
200	fsl,ext-reset-output;
201	status = "okay";
202};
203
204&iomuxc {
205	pinctrl_flexspi0: flexspi0grp {
206		fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK	0x142>,
207			   <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
208			   <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
209			   <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
210			   <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
211			   <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>;
212	};
213
214	pinctrl_i2c1: i2c1grp {
215		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e2>,
216			   <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e2>;
217	};
218
219	pinctrl_i2c1_gpio: i2c1-gpiogrp {
220		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001e2>,
221			   <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001e2>;
222	};
223
224	pinctrl_pmic: pmicirqgrp {
225		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x1c0>;
226	};
227
228	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
229		fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10>;
230	};
231
232	pinctrl_usdhc3: usdhc3grp {
233		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
234			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
235			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
236			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
237			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
238			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
239			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
240			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
241			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
242			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
243			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
244			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
245	};
246
247	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
248		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
249			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
250			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
251			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
252			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
253			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
254			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
255			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
256			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
257			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
258			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
259			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
260	};
261
262	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
263		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
264			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
265			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
266			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
267			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
268			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
269			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
270			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
271			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
272			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
273			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
274			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
275	};
276
277	pinctrl_wdog: wdoggrp {
278		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x1c4>;
279	};
280};
281