1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 3#include "imx8mp.dtsi" 4#include "imx8mp-nominal.dtsi" 5 6#include <dt-bindings/leds/common.h> 7 8/ { 9 aliases { 10 /* some of this aliases like backlight0, ethernetX and switch0 11 * are needed for the bootloader. 12 */ 13 backlight0 = &backlight; 14 ethernet0 = &eqos; 15 ethernet1 = &lan1; 16 ethernet2 = &lan2; 17 rtc0 = &i2c_rtc; 18 rtc1 = &snvs_rtc; 19 switch0 = &switch; 20 }; 21 22 /* 23 * Backlight is present only on some of boards, so it is disabled by 24 * default. 25 */ 26 backlight: backlight { 27 compatible = "pwm-backlight"; 28 pinctrl-0 = <&pinctrl_backlight>; 29 pwms = <&pwm1 0 20000 0>; 30 power-supply = <®_24v>; 31 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 32 brightness-levels = <0 255>; 33 num-interpolated-steps = <17>; 34 default-brightness-level = <8>; 35 status = "disabled"; 36 }; 37 38 leds { 39 compatible = "gpio-leds"; 40 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_gpio_led>; 42 43 led-0 { 44 label = "D1"; 45 color = <LED_COLOR_ID_GREEN>; 46 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 47 function = LED_FUNCTION_STATUS; 48 default-state = "on"; 49 linux,default-trigger = "heartbeat"; 50 }; 51 52 led-1 { 53 label = "D2"; 54 color = <LED_COLOR_ID_GREEN>; 55 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 56 default-state = "off"; 57 }; 58 59 led-2 { 60 label = "D3"; 61 color = <LED_COLOR_ID_GREEN>; 62 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 63 default-state = "on"; 64 }; 65 }; 66 67 reg_1v2: regulator-1v2 { 68 compatible = "regulator-fixed"; 69 vin-supply = <®_5v_p>; 70 regulator-name = "1V2"; 71 regulator-min-microvolt = <1200000>; 72 regulator-max-microvolt = <1200000>; 73 }; 74 75 reg_2v5: regulator-2v5 { 76 compatible = "regulator-fixed"; 77 vin-supply = <®_5v_s>; 78 regulator-name = "2V5"; 79 regulator-min-microvolt = <2500000>; 80 regulator-max-microvolt = <2500000>; 81 }; 82 83 reg_3v3: regulator-3v3 { 84 compatible = "regulator-fixed"; 85 vin-supply = <®_5v_s>; 86 regulator-name = "3V3"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 }; 90 91 /* 92 * This regulator will provide power as long as possible even if 93 * undervoltage is detected. 94 */ 95 reg_5v_p: regulator-5v-p { 96 compatible = "regulator-fixed"; 97 regulator-name = "5V_P"; 98 vin-supply = <®_24v>; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 }; 102 103 /* 104 * This regulator will be automatically shutdown if undervoltage is 105 * detected. 106 */ 107 reg_5v_s: regulator-5v-s { 108 compatible = "regulator-fixed"; 109 regulator-name = "5V_S"; 110 vin-supply = <®_24v>; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 }; 114 115 reg_24v: regulator-24v { 116 compatible = "regulator-fixed"; 117 regulator-name = "24V"; 118 regulator-min-microvolt = <24000000>; 119 regulator-max-microvolt = <24000000>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_reg24v>; 122 interrupts-extended = <&gpio4 23 IRQ_TYPE_EDGE_FALLING>; 123 system-critical-regulator; 124 regulator-uv-less-critical-window-ms = <50>; 125 }; 126 127 reg_can2rs: regulator-can2rs { 128 compatible = "regulator-fixed"; 129 regulator-name = "CAN2RS"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_can2rs>; 132 regulator-min-microvolt = <3300000>; 133 regulator-max-microvolt = <3300000>; 134 gpio = <&gpio4 22 GPIO_ACTIVE_LOW>; 135 }; 136 137 reg_canrs: regulator-canrs { 138 compatible = "regulator-fixed"; 139 regulator-name = "CANRS"; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_canrs>; 142 regulator-min-microvolt = <3300000>; 143 regulator-max-microvolt = <3300000>; 144 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; 145 }; 146 147 reg_tft_vcom: regulator-tft-vcom { 148 compatible = "pwm-regulator"; 149 pwms = <&pwm4 0 20000 0>; 150 regulator-name = "VCOM"; 151 vin-supply = <®_5v_s>; 152 regulator-min-microvolt = <3600000>; 153 regulator-max-microvolt = <3600000>; 154 regulator-always-on; 155 voltage-table = <3600000 26>; 156 status = "disabled"; 157 }; 158 159 reg_vsd_3v3: regulator-vsd-3v3 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_reg_vsd_3v3>; 162 vin-supply = <®_vdd_3v3>; 163 compatible = "regulator-fixed"; 164 regulator-name = "VSD_3V3"; 165 regulator-min-microvolt = <3300000>; 166 regulator-max-microvolt = <3300000>; 167 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 168 enable-active-high; 169 }; 170}; 171 172/* 173 * Board is passively cooled and heatsink is specced for continuous operation 174 * at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done 175 * intentionally, not as part of suspend/resume cycles. 176 */ 177&{/opp-table/opp-1600000000} { 178 /delete-property/ opp-suspend; 179}; 180 181&{/opp-table/opp-1800000000} { 182 /delete-property/ opp-suspend; 183}; 184 185&A53_0 { 186 cpu-supply = <®_vdd_arm>; 187}; 188 189&A53_1 { 190 cpu-supply = <®_vdd_arm>; 191}; 192 193&A53_2 { 194 cpu-supply = <®_vdd_arm>; 195}; 196 197&A53_3 { 198 cpu-supply = <®_vdd_arm>; 199}; 200 201&ecspi2 { 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_ecspi2>; 204 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 205 status = "okay"; 206 207 adc: adc@0 { 208 compatible = "microchip,mcp3002"; 209 reg = <0>; 210 vref-supply = <®_vdd_3v3>; 211 spi-max-frequency = <1000000>; 212 #io-channel-cells = <1>; 213 }; 214}; 215 216&eqos { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_eqos>; 219 phy-mode = "rgmii-rxid"; 220 status = "okay"; 221 222 fixed-link { 223 speed = <1000>; 224 full-duplex; 225 }; 226}; 227 228&flexcan1 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_flexcan1>; 231 xceiver-supply = <®_canrs>; 232 status = "okay"; 233}; 234 235&flexcan2 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_flexcan2>; 238 xceiver-supply = <®_can2rs>; 239 status = "okay"; 240}; 241 242&i2c1 { 243 clock-frequency = <100000>; 244 pinctrl-names = "default", "gpio"; 245 pinctrl-0 = <&pinctrl_i2c1>; 246 pinctrl-1 = <&pinctrl_i2c1_gpio>; 247 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 248 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 249 status = "okay"; 250 251 pmic@25 { 252 compatible = "nxp,pca9450c"; 253 reg = <0x25>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_pmic>; 256 interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>; 257 258 regulators { 259 reg_vdd_soc: BUCK1 { 260 regulator-name = "VDD_SOC"; 261 regulator-min-microvolt = <850000>; 262 regulator-max-microvolt = <850000>; 263 vin-supply = <®_5v_p>; 264 regulator-boot-on; 265 regulator-always-on; 266 regulator-ramp-delay = <3125>; 267 }; 268 269 reg_vdd_arm: BUCK2 { 270 regulator-name = "VDD_ARM"; 271 regulator-min-microvolt = <850000>; 272 regulator-max-microvolt = <1000000>; 273 vin-supply = <®_5v_p>; 274 regulator-boot-on; 275 regulator-always-on; 276 regulator-ramp-delay = <3125>; 277 nxp,dvs-run-voltage = <850000>; 278 nxp,dvs-standby-voltage = <850000>; 279 }; 280 281 reg_vdd_3v3: BUCK4 { 282 regulator-name = "VDD_3V3"; 283 regulator-min-microvolt = <3300000>; 284 regulator-max-microvolt = <3300000>; 285 vin-supply = <®_5v_p>; 286 regulator-boot-on; 287 regulator-always-on; 288 }; 289 290 reg_vdd_1v8: BUCK5 { 291 regulator-name = "VDD_1V8"; 292 regulator-min-microvolt = <1800000>; 293 regulator-max-microvolt = <1800000>; 294 vin-supply = <®_5v_p>; 295 regulator-boot-on; 296 regulator-always-on; 297 }; 298 299 reg_nvcc_dram_1v1: BUCK6 { 300 regulator-name = "NVCC_DRAM_1V1"; 301 regulator-min-microvolt = <1100000>; 302 regulator-max-microvolt = <1100000>; 303 vin-supply = <®_5v_p>; 304 regulator-boot-on; 305 regulator-always-on; 306 }; 307 308 reg_nvcc_snvs_1v8: LDO1 { 309 regulator-name = "NVCC_SNVS_1V8"; 310 regulator-min-microvolt = <1800000>; 311 regulator-max-microvolt = <1800000>; 312 vin-supply = <®_5v_p>; 313 regulator-boot-on; 314 regulator-always-on; 315 }; 316 317 reg_vdda_1v8: LDO3 { 318 regulator-name = "VDDA_1V8"; 319 regulator-min-microvolt = <1800000>; 320 regulator-max-microvolt = <1800000>; 321 vin-supply = <®_5v_p>; 322 regulator-boot-on; 323 regulator-always-on; 324 }; 325 326 reg_nvcc_sd2: LDO5 { 327 regulator-name = "NVCC_SD2"; 328 regulator-min-microvolt = <1800000>; 329 regulator-max-microvolt = <3300000>; 330 vin-supply = <®_5v_p>; 331 regulator-boot-on; 332 regulator-always-on; 333 }; 334 }; 335 }; 336}; 337 338&i2c2 { 339 pinctrl-names = "default", "gpio"; 340 pinctrl-0 = <&pinctrl_i2c2>; 341 pinctrl-1 = <&pinctrl_i2c2_gpio>; 342 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 343 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 344}; 345 346&i2c3 { 347 clock-frequency = <400000>; 348 pinctrl-names = "default", "gpio"; 349 pinctrl-0 = <&pinctrl_i2c3>; 350 pinctrl-1 = <&pinctrl_i2c3_gpio>; 351 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 352 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 353 status = "okay"; 354 355 i2c_rtc: rtc@51 { 356 compatible = "nxp,pcf85063tp"; 357 reg = <0x51>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_rtc>; 360 interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>; 361 quartz-load-femtofarads = <12500>; 362 }; 363}; 364 365&i2c4 { 366 clock-frequency = <380000>; 367 pinctrl-names = "default", "gpio"; 368 pinctrl-0 = <&pinctrl_i2c4>; 369 pinctrl-1 = <&pinctrl_i2c4_gpio>; 370 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 371 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 372 status = "okay"; 373 374 switch: switch@5f { 375 compatible = "microchip,ksz9893"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_switch>; 378 reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 379 reg = <0x5f>; 380 381 ethernet-ports { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 385 lan1: port@0 { 386 reg = <0>; 387 phy-mode = "internal"; 388 label = "lan1"; 389 }; 390 391 lan2: port@1 { 392 reg = <1>; 393 phy-mode = "internal"; 394 label = "lan2"; 395 }; 396 397 port@2 { 398 reg = <2>; 399 label = "cpu"; 400 ethernet = <&eqos>; 401 phy-mode = "rgmii"; 402 /* 2ns RX delay is implemented on PCB */ 403 tx-internal-delay-ps = <2000>; 404 rx-internal-delay-ps = <0>; 405 406 fixed-link { 407 speed = <1000>; 408 full-duplex; 409 }; 410 }; 411 }; 412 }; 413}; 414 415&pwm1 { 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_pwm1>; 418}; 419 420&pwm4 { 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_pwm4>; 423}; 424 425&uart1 { 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_uart1>; 428 status = "okay"; 429 /* 430 * While there is no CTS line, the property "uart-has-rtscts" is still 431 * the right thing to do to enable the UART to do RS485. In RS485-Mode 432 * CTS isn't used anyhow and there is no dedicated property 433 * "uart-has-rts-but-no-cts". 434 */ 435 uart-has-rtscts; 436}; 437 438&uart2 { 439 /* console */ 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pinctrl_uart2>; 442 status = "okay"; 443}; 444 445&usb3_0 { 446 status = "okay"; 447}; 448 449&usb3_1 { 450 status = "okay"; 451}; 452 453&usb3_phy0 { 454 vbus-supply = <®_3v3>; 455 status = "okay"; 456}; 457 458&usb3_phy1 { 459 vbus-supply = <®_3v3>; 460 status = "okay"; 461}; 462 463&usb_dwc3_0 { 464 dr_mode = "host"; 465}; 466 467&usb_dwc3_1 { 468 dr_mode = "host"; 469}; 470 471/* SD Card */ 472&usdhc2 { 473 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 474 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 475 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 476 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 477 vmmc-supply = <®_vsd_3v3>; 478 vqmmc-supply = <®_nvcc_sd2>; 479 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 480 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 481 bus-width = <4>; 482 status = "okay"; 483}; 484 485/* eMMC */ 486&usdhc3 { 487 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 488 assigned-clock-rates = <400000000>; 489 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 490 pinctrl-0 = <&pinctrl_usdhc3>; 491 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 492 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 493 vmmc-supply = <®_vdd_3v3>; 494 vqmmc-supply = <®_vdd_1v8>; 495 bus-width = <8>; 496 no-sd; 497 no-sdio; 498 non-removable; 499 status = "okay"; 500}; 501 502&wdog1 { 503 pinctrl-names = "default"; 504 pinctrl-0 = <&pinctrl_wdog>; 505 fsl,ext-reset-output; 506 status = "okay"; 507}; 508 509&iomuxc { 510 pinctrl_backlight: backlightgrp { 511 fsl,pins = < 512 MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0100 513 >; 514 }; 515 516 pinctrl_can2rs: can2rsgrp { 517 fsl,pins = < 518 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x154 519 >; 520 }; 521 522 pinctrl_canrs: canrsgrp { 523 fsl,pins = < 524 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x154 525 >; 526 }; 527 528 pinctrl_ecspi2: ecspi2grp { 529 fsl,pins = < 530 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 531 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 532 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 533 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 534 >; 535 }; 536 537 pinctrl_eqos: eqosgrp { 538 fsl,pins = < 539 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 540 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 541 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 542 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 543 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 544 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 545 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 546 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 547 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 548 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 549 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 550 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 551 >; 552 }; 553 554 pinctrl_flexcan1: flexcan1grp { 555 fsl,pins = < 556 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 557 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 558 >; 559 }; 560 561 pinctrl_flexcan2: flexcan2grp { 562 fsl,pins = < 563 MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 564 MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 565 >; 566 }; 567 568 pinctrl_gpio_led: gpioledgrp { 569 fsl,pins = < 570 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 571 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 572 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 573 >; 574 }; 575 576 pinctrl_i2c1: i2c1grp { 577 fsl,pins = < 578 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 579 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 580 >; 581 }; 582 583 pinctrl_i2c1_gpio: i2c1gpiogrp { 584 fsl,pins = < 585 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 586 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 587 >; 588 }; 589 590 pinctrl_i2c2: i2c2grp { 591 fsl,pins = < 592 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 593 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 594 >; 595 }; 596 597 pinctrl_i2c2_gpio: i2c2gpiogrp { 598 fsl,pins = < 599 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 600 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 601 >; 602 }; 603 604 pinctrl_i2c3: i2c3grp { 605 fsl,pins = < 606 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 607 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 608 >; 609 }; 610 611 pinctrl_i2c3_gpio: i2c3gpiogrp { 612 fsl,pins = < 613 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 614 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 615 >; 616 }; 617 618 pinctrl_i2c4: i2c4grp { 619 fsl,pins = < 620 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 621 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 622 >; 623 }; 624 625 pinctrl_i2c4_gpio: i2c4gpiogrp { 626 fsl,pins = < 627 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 628 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 629 >; 630 }; 631 632 pinctrl_pmic: pmicirqgrp { 633 fsl,pins = < 634 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 635 >; 636 }; 637 638 pinctrl_pwm1: pwm1grp { 639 fsl,pins = < 640 MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 641 >; 642 }; 643 644 pinctrl_pwm4: pwm4grp { 645 fsl,pins = < 646 MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116 647 >; 648 }; 649 650 pinctrl_reg24v: reg24vgrp { 651 fsl,pins = < 652 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x154 653 >; 654 }; 655 656 pinctrl_reg_vsd_3v3: regvsd3v3grp { 657 fsl,pins = < 658 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 659 >; 660 }; 661 662 pinctrl_rtc: rtcgrp { 663 fsl,pins = < 664 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x41 665 >; 666 }; 667 668 pinctrl_switch: switchgrp { 669 fsl,pins = < 670 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x41 671 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41 672 >; 673 }; 674 675 pinctrl_touchscreen: touchscreengrp { 676 fsl,pins = < 677 /* external 10 k pull up */ 678 /* CTP_INT */ 679 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 680 /* CTP_RST */ 681 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41 682 >; 683 }; 684 685 pinctrl_uart1: uart1grp { 686 fsl,pins = < 687 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 688 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 689 MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140 690 /* CTS pin is not connected, but needed as workaround */ 691 MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x140 692 >; 693 }; 694 695 pinctrl_uart2: uart2grp { 696 fsl,pins = < 697 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f 698 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f 699 >; 700 }; 701 702 pinctrl_usdhc2: usdhc2grp { 703 fsl,pins = < 704 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 705 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 706 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 707 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 708 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 709 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 710 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 711 >; 712 }; 713 714 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 715 fsl,pins = < 716 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 717 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 718 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 719 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 720 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 721 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 722 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 723 >; 724 }; 725 726 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 727 fsl,pins = < 728 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 729 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 730 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 731 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 732 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 733 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 734 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 735 >; 736 }; 737 738 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 739 fsl,pins = < 740 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 741 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4 742 >; 743 }; 744 745 pinctrl_usdhc3: usdhc3grp { 746 fsl,pins = < 747 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 748 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 749 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 750 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 751 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 752 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 753 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 754 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 755 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 756 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 757 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 758 >; 759 }; 760 761 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 762 fsl,pins = < 763 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 764 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 765 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 766 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 767 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 768 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 769 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 770 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 771 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 772 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 773 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 774 >; 775 }; 776 777 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 778 fsl,pins = < 779 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 780 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 781 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 782 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 783 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 784 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 785 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 786 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 787 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 788 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 789 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 790 >; 791 }; 792 793 pinctrl_wdog: wdoggrp { 794 fsl,pins = < 795 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 796 >; 797 }; 798}; 799