1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright (C) 2022 Kontron Electronics GmbH 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include "imx8mp.dtsi" 8 9/ { 10 model = "Kontron OSM-S i.MX8MP"; 11 compatible = "kontron,imx8mp-osm-s", "fsl,imx8mp"; 12 13 aliases { 14 rtc0 = &rv3028; 15 rtc1 = &snvs_rtc; 16 }; 17 18 memory@40000000 { 19 device_type = "memory"; 20 /* 21 * There are multiple SoM flavors with different DDR sizes. 22 * The smallest is 1GB. For larger sizes the bootloader will 23 * update the reg property. 24 */ 25 reg = <0x0 0x40000000 0 0x80000000>; 26 }; 27 28 chosen { 29 stdout-path = &uart3; 30 }; 31 32 reg_usb1_vbus: regulator-usb1-vbus { 33 compatible = "regulator-fixed"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&pinctrl_reg_usb1_vbus>; 36 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 37 enable-active-high; 38 regulator-min-microvolt = <5000000>; 39 regulator-max-microvolt = <5000000>; 40 regulator-name = "VBUS_USB_A"; 41 }; 42 43 reg_usb2_vbus: regulator-usb2-vbus { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usb2_vbus>; 47 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 48 enable-active-high; 49 regulator-min-microvolt = <5000000>; 50 regulator-max-microvolt = <5000000>; 51 regulator-name = "VBUS_USB_B"; 52 }; 53 54 reg_usdhc2_vcc: regulator-usdhc2-vcc { 55 compatible = "regulator-fixed"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; 58 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 59 enable-active-high; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 regulator-name = "VCC_SDIO_A"; 63 }; 64 65 reg_usdhc3_vcc: regulator-usdhc3-vcc { 66 compatible = "regulator-fixed"; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; 69 gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; 70 enable-active-high; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 regulator-name = "VCC_SDIO_B"; 74 }; 75 76 reg_vdd_carrier: regulator-vdd-carrier { 77 compatible = "regulator-fixed"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_reg_vdd_carrier>; 80 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; 81 enable-active-high; 82 regulator-always-on; 83 regulator-boot-on; 84 regulator-name = "VDD_CARRIER"; 85 86 regulator-state-standby { 87 regulator-on-in-suspend; 88 }; 89 90 regulator-state-mem { 91 regulator-off-in-suspend; 92 }; 93 94 regulator-state-disk { 95 regulator-off-in-suspend; 96 }; 97 }; 98}; 99 100&A53_0 { 101 cpu-supply = <®_vdd_arm>; 102}; 103 104&A53_1 { 105 cpu-supply = <®_vdd_arm>; 106}; 107 108&A53_2 { 109 cpu-supply = <®_vdd_arm>; 110}; 111 112&A53_3 { 113 cpu-supply = <®_vdd_arm>; 114}; 115 116&ecspi1 { /* OSM-S SPI_A */ 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_ecspi1>; 119 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 120}; 121 122&ecspi2 { /* OSM-S SPI_B */ 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_ecspi2>; 125 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 126}; 127 128&flexcan1 { /* OSM-S CAN_A */ 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_flexcan1>; 131}; 132 133&flexcan2 { /* OSM-S CAN_B */ 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_flexcan2>; 136}; 137 138&gpio1 { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_gpio1>; 141 gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "", 142 "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", 143 "GPIO_A_5", "USB_B_EN", "USB_A_ID", "USB_B_ID", 144 "USB_A_EN", "USB_A_OC","CAM_MCK", "USB_B_OC", 145 "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2", 146 "ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK", 147 "ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1", 148 "ETH_B_RXD2", "ETH_B_RXD3"; 149}; 150 151&gpio2 { 152 gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", 153 "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", 154 "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", 155 "SDIO_A_WP"; 156}; 157 158&gpio3 { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_gpio3>; 161 gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5", 162 "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD", 163 "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1", 164 "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4", 165 "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_0", 166 "GPIO_B_1", "", "BOOT_SEL0", "BOOT_SEL1", 167 "", "", "SDIO_B_CD", "SDIO_B_PWR_EN", 168 "HDMI_CEC", "HDMI_HPD"; 169}; 170 171&gpio4 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_gpio4>; 174 gpio-line-names = "GPIO_B_5", "GPIO_B_6", "GPIO_B_7", "GPIO_C_0", 175 "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", 176 "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", 177 "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", 178 "ETH_A_TX_EN", "ETH_A_TX_CLK", "GPIO_B_3", "GPIO_B_4", 179 "GPIO_B_2", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS", 180 "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX", 181 "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; 182}; 183 184&gpio5 { 185 gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2", 186 "PWM_1", "PWM_0", "SPI_A_SCK", "SPI_A_SDO", 187 "SPI_A_SDI", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO", 188 "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA", 189 "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT", 190 "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX", 191 "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX", 192 "UART_B_RX", "UART_B_TX"; 193}; 194 195&i2c1 { /* OSM-S I2C_A */ 196 clock-frequency = <400000>; 197 pinctrl-names = "default", "gpio"; 198 pinctrl-0 = <&pinctrl_i2c1>; 199 pinctrl-1 = <&pinctrl_i2c1_gpio>; 200 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 201 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 202}; 203 204&i2c2 { /* OSM-S I2C_B */ 205 clock-frequency = <400000>; 206 pinctrl-names = "default", "gpio"; 207 pinctrl-0 = <&pinctrl_i2c2>; 208 pinctrl-1 = <&pinctrl_i2c2_gpio>; 209 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 210 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 211}; 212 213&i2c3 { /* OSM-S PCIe SMDAT/SMCLK */ 214 clock-frequency = <400000>; 215 pinctrl-names = "default", "gpio"; 216 pinctrl-0 = <&pinctrl_i2c3>; 217 pinctrl-1 = <&pinctrl_i2c3_gpio>; 218 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 219 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 220}; 221 222&i2c4 { /* OSM-S I2C_CAM */ 223 clock-frequency = <400000>; 224 pinctrl-names = "default", "gpio"; 225 pinctrl-0 = <&pinctrl_i2c4>; 226 pinctrl-1 = <&pinctrl_i2c4_gpio>; 227 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 228 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 229}; 230 231&i2c5 { /* PMIC, EEPROM, RTC */ 232 clock-frequency = <400000>; 233 pinctrl-names = "default", "gpio"; 234 pinctrl-0 = <&pinctrl_i2c5>; 235 pinctrl-1 = <&pinctrl_i2c5_gpio>; 236 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 237 sda-gpios = <&gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 238 status = "okay"; 239 240 pca9450: pmic@25 { 241 compatible = "nxp,pca9450c"; 242 reg = <0x25>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_pmic>; 245 interrupt-parent = <&gpio1>; 246 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 247 nxp,i2c-lt-enable; 248 249 regulators { 250 reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */ 251 regulator-name = "+0V8_VDD_SOC (BUCK1)"; 252 regulator-min-microvolt = <850000>; 253 regulator-max-microvolt = <950000>; 254 regulator-boot-on; 255 regulator-always-on; 256 regulator-ramp-delay = <3125>; 257 }; 258 259 reg_vdd_arm: BUCK2 { 260 regulator-name = "+0V9_VDD_ARM (BUCK2)"; 261 regulator-min-microvolt = <850000>; 262 regulator-max-microvolt = <950000>; 263 regulator-boot-on; 264 regulator-always-on; 265 regulator-ramp-delay = <3125>; 266 nxp,dvs-run-voltage = <950000>; 267 nxp,dvs-standby-voltage = <850000>; 268 }; 269 270 reg_vdd_3v3: BUCK4 { 271 regulator-name = "+3V3 (BUCK4)"; 272 regulator-min-microvolt = <3300000>; 273 regulator-max-microvolt = <3300000>; 274 regulator-boot-on; 275 regulator-always-on; 276 }; 277 278 reg_vdd_1v8: BUCK5 { 279 regulator-name = "+1V8 (BUCK5)"; 280 regulator-min-microvolt = <1800000>; 281 regulator-max-microvolt = <1800000>; 282 regulator-boot-on; 283 regulator-always-on; 284 }; 285 286 reg_nvcc_dram: BUCK6 { 287 regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; 288 regulator-min-microvolt = <1100000>; 289 regulator-max-microvolt = <1100000>; 290 regulator-boot-on; 291 regulator-always-on; 292 }; 293 294 reg_nvcc_snvs: LDO1 { 295 regulator-name = "+1V8_NVCC_SNVS (LDO1)"; 296 regulator-min-microvolt = <1800000>; 297 regulator-max-microvolt = <1800000>; 298 regulator-boot-on; 299 regulator-always-on; 300 }; 301 302 reg_vdda: LDO3 { 303 regulator-name = "+1V8_VDDA (LDO3)"; 304 regulator-min-microvolt = <1800000>; 305 regulator-max-microvolt = <1800000>; 306 regulator-boot-on; 307 regulator-always-on; 308 }; 309 310 reg_nvcc_sd: LDO5 { 311 regulator-name = "NVCC_SD (LDO5)"; 312 regulator-min-microvolt = <1800000>; 313 regulator-max-microvolt = <3300000>; 314 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 315 }; 316 }; 317 }; 318 319 eeprom@50 { 320 compatible = "onnn,n24s64b", "atmel,24c64"; 321 reg = <0x50>; 322 pagesize = <32>; 323 size = <8192>; 324 num-addresses = <1>; 325 }; 326 327 rv3028: rtc@52 { 328 compatible = "microcrystal,rv3028"; 329 reg = <0x52>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_rtc>; 332 interrupts-extended = <&gpio3 24 IRQ_TYPE_LEVEL_LOW>; 333 }; 334}; 335 336&pwm1 { /* OSM-S PWM_0 */ 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_pwm1>; 339}; 340 341&pwm2 { /* OSM-S PWM_1 */ 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_pwm2>; 344}; 345 346&pwm3 { /* OSM-S PWM_2 */ 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_pwm3>; 349}; 350 351&sai3 { /* OSM-S I2S_A */ 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_sai3>; 354}; 355 356&uart1 { /* OSM-S UART_A */ 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_uart1>; 359}; 360 361&uart2 { /* OSM-S UART_C */ 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_uart2>; 364}; 365 366&uart3 { /* OSM-S UART_CON */ 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_uart3>; 369 status = "okay"; 370}; 371 372&uart4 { /* OSM-S UART_B */ 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_uart4>; 375}; 376 377&usb3_0 { /* OSM-S USB_A */ 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_usb1_oc>; 380 fsl,over-current-active-low; 381}; 382 383&usb3_1 { /* OSM-S USB_B */ 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_usb2_oc>; 386 fsl,over-current-active-low; 387}; 388 389&usdhc1 { /* eMMC */ 390 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 391 pinctrl-0 = <&pinctrl_usdhc1>; 392 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 393 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 394 vmmc-supply = <®_vdd_3v3>; 395 vqmmc-supply = <®_vdd_1v8>; 396 bus-width = <8>; 397 non-removable; 398 status = "okay"; 399}; 400 401&usdhc2 { /* OSM-S SDIO_A */ 402 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 403 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>; 404 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>; 405 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>; 406 vmmc-supply = <®_usdhc2_vcc>; 407 vqmmc-supply = <®_nvcc_sd>; 408 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 409}; 410 411&usdhc3 { /* OSM-S SDIO_B */ 412 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 413 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; 414 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; 415 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; 416 vmmc-supply = <®_usdhc3_vcc>; 417 vqmmc-supply = <®_nvcc_sd>; 418 cd-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 419 wp-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 420}; 421 422&wdog1 { 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_wdog>; 425 fsl,ext-reset-output; 426 status = "okay"; 427}; 428 429&iomuxc { 430 pinctrl_csi_mck: csimckgrp { 431 fsl,pins = < 432 MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 /* CAM_MCK */ 433 >; 434 }; 435 436 pinctrl_ecspi1: ecspi1grp { 437 fsl,pins = < 438 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 /* SPI_A_SDI_(IO0) */ 439 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 /* SPI_A_SDO_(IO1) */ 440 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 /* SPI_A_SCK */ 441 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* SPI_A_CS0# */ 442 >; 443 }; 444 445 pinctrl_ecspi2: ecspi2grp { 446 fsl,pins = < 447 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 /* SPI_B_SDI */ 448 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 /* SPI_B_SDO */ 449 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 /* SPI_B_SCK */ 450 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* SPI_B_CS0# */ 451 >; 452 }; 453 454 pinctrl_enet_rgmii: enetrgmiigrp { 455 fsl,pins = < 456 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 /* ETH_MDC */ 457 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 /* ETH_MDIO */ 458 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ 459 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ 460 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ 461 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ 462 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ 463 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ 464 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ 465 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ 466 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ 467 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ 468 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ 469 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ 470 >; 471 }; 472 473 pinctrl_eqos_rgmii: eqosrgmiigrp { 474 fsl,pins = < 475 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 /* ETH_B_MDC */ 476 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 /* ETH_B_MDIO */ 477 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 /* ETH_B_(S)(R)(G)MII_RXD0 */ 478 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 /* ETH_B_(S)(R)(G)MII_RXD1 */ 479 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 /* ETH_B_(R)(G)MII_RXD2 */ 480 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 /* ETH_B_(R)(G)MII_RXD3 */ 481 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 /* ETH_B_(R)(G)MII_RX_CLK */ 482 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 /* ETH_B_(R)(G)MII_RX_DV(_ER) */ 483 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f /* ETH_B_(S)(R)(G)MII_TXD0 */ 484 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f /* ETH_B_(S)(R)(G)MII_TXD1 */ 485 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f /* ETH_B_(S)(R)(G)MII_TXD2 */ 486 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f /* ETH_B_(S)(R)(G)MII_TXD3 */ 487 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f /* ETH_B_(R)(G)MII_TX_CLK */ 488 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f /* ETH_B_(R)(G)MII_TX_EN(_ER) */ 489 >; 490 }; 491 492 pinctrl_flexcan1: flexcan1grp { 493 fsl,pins = < 494 MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN_A_TX */ 495 MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN_A_RX */ 496 >; 497 }; 498 499 pinctrl_flexcan2: flexcan2grp { 500 fsl,pins = < 501 MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN_B_TX */ 502 MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 /* CAN_B_RX */ 503 >; 504 }; 505 506 pinctrl_gpio1: gpio1grp { 507 fsl,pins = < 508 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x19 /* GPIO_A_0 */ 509 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x19 /* GPIO_A_1 */ 510 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* GPIO_A_2 */ 511 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 /* GPIO_A_3 */ 512 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 /* GPIO_A_4 */ 513 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 /* GPIO_A_5 */ 514 >; 515 }; 516 517 pinctrl_gpio3: gpio3grp { 518 fsl,pins = < 519 MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x19 /* GPIO_A_7 */ 520 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x19 /* GPIO_B_0 */ 521 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x19 /* GPIO_B_1 */ 522 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x19 /* BOOT_SEL0# */ 523 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x19 /* BOOT_SEL1# */ 524 >; 525 }; 526 527 pinctrl_gpio4: gpio4grp { 528 fsl,pins = < 529 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* GPIO_B_5 */ 530 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 /* GPIO_B_6 */ 531 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 /* GPIO_B_7 */ 532 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x19 /* GPIO_C_0 */ 533 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 /* GPIO_B_3 */ 534 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 /* GPIO_B_4 */ 535 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x19 /* GPIO_B_2 */ 536 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19 /* GPIO_A_6 */ 537 >; 538 }; 539 540 pinctrl_hdmi: hdmigrp { 541 fsl,pins = < 542 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 /* HDMI_HPD */ 543 >; 544 }; 545 546 pinctrl_i2c1: i2c1grp { 547 fsl,pins = < 548 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 /* I2C_A_SCL */ 549 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 /* I2C_A_SDA */ 550 >; 551 }; 552 553 pinctrl_i2c1_gpio: i2c1gpiogrp { 554 fsl,pins = < 555 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 /* I2C_A_SCL */ 556 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 /* I2C_A_SDA */ 557 >; 558 }; 559 560 pinctrl_i2c2: i2c2grp { 561 fsl,pins = < 562 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 /* I2C_B_SCL */ 563 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 /* I2C_B_SDA */ 564 >; 565 }; 566 567 pinctrl_i2c2_gpio: i2c2gpiogrp { 568 fsl,pins = < 569 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 /* I2C_B_SCL */ 570 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 /* I2C_B_SDA */ 571 >; 572 }; 573 574 pinctrl_i2c3: i2c3grp { 575 fsl,pins = < 576 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 /* PCIe_SMCLK */ 577 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 /* PCIe_SMDAT */ 578 >; 579 }; 580 581 pinctrl_i2c3_gpio: i2c3gpiogrp { 582 fsl,pins = < 583 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 /* PCIe_SMCLK */ 584 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 /* PCIe_SMDAT */ 585 >; 586 }; 587 588 pinctrl_i2c4: i2c4grp { 589 fsl,pins = < 590 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 /* I2C_CAM_SCL/CSI_TX_P */ 591 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 /* I2C_CAM_SDA/CSI_TX_N */ 592 >; 593 }; 594 595 pinctrl_i2c4_gpio: i2c4gpiogrp { 596 fsl,pins = < 597 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 /* I2C_CAM_SCL/CSI_TX_P */ 598 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 /* I2C_CAM_SDA/CSI_TX_N */ 599 >; 600 }; 601 602 pinctrl_i2c5: i2c5grp { 603 fsl,pins = < 604 MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x40000084 605 MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x40000084 606 >; 607 }; 608 609 pinctrl_i2c5_gpio: i2c5gpiogrp { 610 fsl,pins = < 611 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x84 612 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x84 613 >; 614 }; 615 616 pinctrl_pcie: pciegrp { 617 fsl,pins = < 618 MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x19 /* PCIe_CLKREQ# */ 619 MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x19 /* PCIe_A_PERST# */ 620 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x19 /* PCIe_WAKE# */ 621 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 /* PCIe_SM_ALERT */ 622 >; 623 }; 624 625 pinctrl_pmic: pmicgrp { 626 fsl,pins = < 627 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 628 >; 629 }; 630 631 pinctrl_pwm1: pwm1grp { 632 fsl,pins = < 633 MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6 /* PWM_0 */ 634 >; 635 }; 636 637 pinctrl_pwm2: pwm2grp { 638 fsl,pins = < 639 MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x6 /* PWM_1 */ 640 >; 641 }; 642 643 pinctrl_pwm3: pwm3grp { 644 fsl,pins = < 645 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x6 /* PWM_2 */ 646 >; 647 }; 648 649 pinctrl_reg_usb1_vbus: regusb1vbusgrp { 650 fsl,pins = < 651 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 /* USB_A_EN */ 652 >; 653 }; 654 655 pinctrl_reg_usb2_vbus: regusb2vbusgrp { 656 fsl,pins = < 657 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 /* USB_B_EN */ 658 >; 659 }; 660 661 pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { 662 fsl,pins = < 663 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ 664 >; 665 }; 666 667 pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { 668 fsl,pins = < 669 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x19 /* SDIO_B_PWR_EN */ 670 >; 671 }; 672 673 pinctrl_reg_vdd_carrier: regvddcarriergrp { 674 fsl,pins = < 675 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x19 /* CARRIER_PWR_EN */ 676 >; 677 }; 678 679 pinctrl_rtc: rtcgrp { 680 fsl,pins = < 681 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1c0 682 >; 683 }; 684 685 pinctrl_sai3: sai3grp { 686 fsl,pins = < 687 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 /* I2S_A_DATA_IN */ 688 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 /* I2S_A_DATA_OUT */ 689 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0xd6 /* I2S_B_DATA_IN */ 690 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0xd6 /* I2S_B_DATA_OUT */ 691 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 /* I2S_MCLK */ 692 MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0xd6 /* I2S_LRCLK */ 693 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 /* I2S_BITCLK */ 694 >; 695 }; 696 697 pinctrl_uart1: uart1grp { 698 fsl,pins = < 699 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 /* UART_A_RX */ 700 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 /* UART_A_TX */ 701 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x140 /* UART_A_CTS */ 702 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x140 /* UART_A_RTS */ 703 >; 704 }; 705 706 pinctrl_uart2: uart2grp { 707 fsl,pins = < 708 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 /* UART_C_RX */ 709 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 /* UART_C_TX */ 710 >; 711 }; 712 713 pinctrl_uart3: uart3grp { 714 fsl,pins = < 715 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* UART_CON_RX */ 716 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* UART_CON_TX */ 717 >; 718 }; 719 720 pinctrl_uart4: uart4grp { 721 fsl,pins = < 722 MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x140 /* UART_B_RX */ 723 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART_B_TX */ 724 MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x140 /* UART_B_CTS */ 725 MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140 /* UART_B_RTS */ 726 >; 727 }; 728 729 pinctrl_usb1_id: usb1idgrp { 730 fsl,pins = < 731 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4 /* USB_A_ID */ 732 >; 733 }; 734 735 pinctrl_usb1_oc: usb1ocgrp { 736 fsl,pins = < 737 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0 /* USB_A_OC# */ 738 >; 739 }; 740 741 pinctrl_usb2_id: usb2idgrp { 742 fsl,pins = < 743 MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x1c4 /* USB_B_ID */ 744 >; 745 }; 746 747 pinctrl_usb2_oc: usb2ocgrp { 748 fsl,pins = < 749 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0 /* USB_B_OC# */ 750 >; 751 }; 752 753 pinctrl_usdhc1: usdhc1grp { 754 fsl,pins = < 755 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 756 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 757 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 758 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 759 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 760 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 761 MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d0 762 MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d0 763 MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d0 764 MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d0 765 MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141 766 MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x190 767 >; 768 }; 769 770 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 771 fsl,pins = < 772 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 773 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 774 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 775 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 776 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 777 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 778 MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d4 779 MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d4 780 MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d4 781 MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d4 782 MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141 783 MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x194 784 >; 785 }; 786 787 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 788 fsl,pins = < 789 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 790 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 791 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 792 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 793 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 794 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 795 MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d6 796 MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d6 797 MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d6 798 MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d6 799 MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141 800 MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x196 801 >; 802 }; 803 804 pinctrl_usdhc2: usdhc2grp { 805 fsl,pins = < 806 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDIO_A_CLK */ 807 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ 808 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ 809 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ 810 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ 811 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ 812 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 813 >; 814 }; 815 816 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 817 fsl,pins = < 818 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDIO_A_CLK */ 819 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ 820 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ 821 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ 822 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ 823 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ 824 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 825 >; 826 }; 827 828 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 829 fsl,pins = < 830 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDIO_A_CLK */ 831 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ 832 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ 833 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ 834 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ 835 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ 836 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 837 >; 838 }; 839 840 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 841 fsl,pins = < 842 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x19 /* SDIO_A_CD# */ 843 >; 844 }; 845 846 pinctrl_usdhc2_wp: usdhc2wpgrp { 847 fsl,pins = < 848 MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x400000d6 /* SDIO_A_WP */ 849 >; 850 }; 851 852 pinctrl_usdhc3: usdhc3grp { 853 fsl,pins = < 854 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 /* SDIO_B_CLK */ 855 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 /* SDIO_B_CMD */ 856 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 /* SDIO_B_D0 */ 857 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 /* SDIO_B_D1 */ 858 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 /* SDIO_B_D2 */ 859 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 /* SDIO_B_D3 */ 860 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 /* SDIO_B_D4 */ 861 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 /* SDIO_B_D5 */ 862 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 /* SDIO_B_D6 */ 863 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 /* SDIO_B_D7 */ 864 >; 865 }; 866 867 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 868 fsl,pins = < 869 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 /* SDIO_B_CLK */ 870 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 /* SDIO_B_CMD */ 871 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 /* SDIO_B_D0 */ 872 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 /* SDIO_B_D1 */ 873 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 /* SDIO_B_D2 */ 874 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 /* SDIO_B_D3 */ 875 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 /* SDIO_B_D4 */ 876 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 /* SDIO_B_D5 */ 877 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 /* SDIO_B_D6 */ 878 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 /* SDIO_B_D7 */ 879 >; 880 }; 881 882 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 883 fsl,pins = < 884 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 /* SDIO_B_CLK */ 885 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 /* SDIO_B_CMD */ 886 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 /* SDIO_B_D0 */ 887 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 /* SDIO_B_D1 */ 888 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 /* SDIO_B_D2 */ 889 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 /* SDIO_B_D3 */ 890 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 /* SDIO_B_D4 */ 891 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 /* SDIO_B_D5 */ 892 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 /* SDIO_B_D6 */ 893 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 /* SDIO_B_D7 */ 894 >; 895 }; 896 897 pinctrl_usdhc3_gpio: usdhc3gpiogrp { 898 fsl,pins = < 899 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x19 /* SDIO_B_CD# */ 900 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19 /* SDIO_B_WP */ 901 >; 902 }; 903 904 pinctrl_wdog: wdoggrp { 905 fsl,pins = < 906 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 907 >; 908 }; 909}; 910