1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include "imx8mp.dtsi"
10
11/ {
12	model = "NXP i.MX8MPlus EVK board";
13	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
14
15	chosen {
16		stdout-path = &uart2;
17	};
18
19	backlight_lvds: backlight-lvds {
20		compatible = "pwm-backlight";
21		pwms = <&pwm2 0 100000 0>;
22		brightness-levels = <0 100>;
23		num-interpolated-steps = <100>;
24		default-brightness-level = <100>;
25		power-supply = <&reg_per_12v>;
26		status = "disabled";
27	};
28
29	hdmi-connector {
30		compatible = "hdmi-connector";
31		label = "hdmi";
32		type = "a";
33
34		port {
35			hdmi_connector_in: endpoint {
36				remote-endpoint = <&adv7535_out>;
37			};
38		};
39	};
40
41	gpio-leds {
42		compatible = "gpio-leds";
43		pinctrl-names = "default";
44		pinctrl-0 = <&pinctrl_gpio_led>;
45
46		status {
47			label = "yellow:status";
48			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
49			default-state = "on";
50		};
51	};
52
53	memory@40000000 {
54		device_type = "memory";
55		reg = <0x0 0x40000000 0 0xc0000000>,
56		      <0x1 0x00000000 0 0xc0000000>;
57	};
58
59	native-hdmi-connector {
60		compatible = "hdmi-connector";
61		label = "HDMI OUT";
62		type = "a";
63
64		port {
65			hdmi_in: endpoint {
66				remote-endpoint = <&hdmi_tx_out>;
67			};
68		};
69	};
70
71	pcie0_refclk: pcie0-refclk {
72		compatible = "fixed-clock";
73		#clock-cells = <0>;
74		clock-frequency = <100000000>;
75	};
76
77	reg_audio_3v3: regulator-audio-3v3 {
78		compatible = "regulator-fixed";
79		regulator-name = "audio-3v3";
80		regulator-min-microvolt = <3300000>;
81		regulator-max-microvolt = <3300000>;
82		regulator-always-on;
83		regulator-boot-on;
84	};
85
86	reg_audio_1v8: regulator-audio-1v8 {
87		compatible = "regulator-fixed";
88		regulator-name = "audio-1v8";
89		regulator-min-microvolt = <1800000>;
90		regulator-max-microvolt = <1800000>;
91		regulator-always-on;
92		regulator-boot-on;
93	};
94
95	reg_audio_pwr: regulator-audio-pwr {
96		compatible = "regulator-fixed";
97		pinctrl-names = "default";
98		pinctrl-0 = <&pinctrl_audio_pwr_reg>;
99		regulator-name = "audio-pwr";
100		regulator-min-microvolt = <3300000>;
101		regulator-max-microvolt = <3300000>;
102		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
103		enable-active-high;
104	};
105
106	reg_can1_stby: regulator-can1-stby {
107		compatible = "regulator-fixed";
108		regulator-name = "can1-stby";
109		pinctrl-names = "default";
110		pinctrl-0 = <&pinctrl_flexcan1_reg>;
111		regulator-min-microvolt = <3300000>;
112		regulator-max-microvolt = <3300000>;
113		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
114		enable-active-high;
115	};
116
117	reg_can2_stby: regulator-can2-stby {
118		compatible = "regulator-fixed";
119		regulator-name = "can2-stby";
120		pinctrl-names = "default";
121		pinctrl-0 = <&pinctrl_flexcan2_reg>;
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
125		enable-active-high;
126	};
127
128	reg_pcie0: regulator-pcie {
129		compatible = "regulator-fixed";
130		pinctrl-names = "default";
131		pinctrl-0 = <&pinctrl_pcie0_reg>;
132		regulator-name = "MPCIE_3V3";
133		regulator-min-microvolt = <3300000>;
134		regulator-max-microvolt = <3300000>;
135		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
136		enable-active-high;
137	};
138
139	reg_per_12v: regulator-per-12v {
140		compatible = "regulator-fixed";
141		regulator-name = "PER_12V";
142		regulator-min-microvolt = <12000000>;
143		regulator-max-microvolt = <12000000>;
144		gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>;
145		enable-active-high;
146	};
147
148	reg_usdhc2_vmmc: regulator-usdhc2 {
149		compatible = "regulator-fixed";
150		pinctrl-names = "default";
151		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
152		regulator-name = "VSD_3V3";
153		regulator-min-microvolt = <3300000>;
154		regulator-max-microvolt = <3300000>;
155		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
156		enable-active-high;
157	};
158
159	reg_vext_3v3: regulator-vext-3v3 {
160		compatible = "regulator-fixed";
161		regulator-name = "VEXT_3V3";
162		regulator-min-microvolt = <3300000>;
163		regulator-max-microvolt = <3300000>;
164	};
165
166	audio_codec_bt_sco: audio-codec-bt-sco {
167		compatible = "linux,bt-sco";
168		#sound-dai-cells = <1>;
169	};
170
171	sound {
172		compatible = "simple-audio-card";
173		simple-audio-card,name = "wm8960-audio";
174		simple-audio-card,format = "i2s";
175		simple-audio-card,frame-master = <&cpudai>;
176		simple-audio-card,bitclock-master = <&cpudai>;
177		simple-audio-card,widgets =
178			"Headphone", "Headphone Jack",
179			"Speaker", "External Speaker",
180			"Microphone", "Mic Jack";
181		simple-audio-card,routing =
182			"Headphone Jack", "HP_L",
183			"Headphone Jack", "HP_R",
184			"External Speaker", "SPK_LP",
185			"External Speaker", "SPK_LN",
186			"External Speaker", "SPK_RP",
187			"External Speaker", "SPK_RN",
188			"LINPUT1", "Mic Jack",
189			"LINPUT3", "Mic Jack",
190			"Mic Jack", "MICB";
191
192		cpudai: simple-audio-card,cpu {
193			sound-dai = <&sai3>;
194		};
195
196		simple-audio-card,codec {
197			sound-dai = <&wm8960>;
198		};
199
200	};
201
202	sound-bt-sco {
203		compatible = "simple-audio-card";
204		simple-audio-card,name = "bt-sco-audio";
205		simple-audio-card,format = "dsp_a";
206		simple-audio-card,bitclock-inversion;
207		simple-audio-card,frame-master = <&btcpu>;
208		simple-audio-card,bitclock-master = <&btcpu>;
209
210		btcpu: simple-audio-card,cpu {
211			sound-dai = <&sai2>;
212			dai-tdm-slot-num = <2>;
213			dai-tdm-slot-width = <16>;
214		};
215
216		simple-audio-card,codec {
217			sound-dai = <&audio_codec_bt_sco 1>;
218		};
219	};
220
221	sound-hdmi {
222		compatible = "fsl,imx-audio-hdmi";
223		model = "audio-hdmi";
224		audio-cpu = <&aud2htx>;
225		hdmi-out;
226	};
227
228	sound-micfil {
229		compatible = "fsl,imx-audio-card";
230		model = "micfil-audio";
231
232		pri-dai-link {
233			link-name = "micfil hifi";
234			format = "i2s";
235
236			cpu {
237				sound-dai = <&micfil>;
238			};
239		};
240	};
241
242	sound-xcvr {
243		compatible = "fsl,imx-audio-card";
244		model = "imx-audio-xcvr";
245
246		pri-dai-link {
247			link-name = "XCVR PCM";
248
249			cpu {
250				sound-dai = <&xcvr>;
251			};
252		};
253	};
254
255	reserved-memory {
256		#address-cells = <2>;
257		#size-cells = <2>;
258		ranges;
259
260		dsp_vdev0vring0: vdev0vring0@942f0000 {
261			reg = <0 0x942f0000 0 0x8000>;
262			no-map;
263		};
264
265		dsp_vdev0vring1: vdev0vring1@942f8000 {
266			reg = <0 0x942f8000 0 0x8000>;
267			no-map;
268		};
269
270		dsp_vdev0buffer: vdev0buffer@94300000 {
271			compatible = "shared-dma-pool";
272			reg = <0 0x94300000 0 0x100000>;
273			no-map;
274		};
275	};
276};
277
278&flexspi {
279	pinctrl-names = "default";
280	pinctrl-0 = <&pinctrl_flexspi0>;
281	status = "okay";
282
283	flash@0 {
284		compatible = "jedec,spi-nor";
285		reg = <0>;
286		spi-max-frequency = <80000000>;
287		spi-tx-bus-width = <1>;
288		spi-rx-bus-width = <4>;
289	};
290};
291
292&A53_0 {
293	cpu-supply = <&reg_arm>;
294};
295
296&A53_1 {
297	cpu-supply = <&reg_arm>;
298};
299
300&A53_2 {
301	cpu-supply = <&reg_arm>;
302};
303
304&A53_3 {
305	cpu-supply = <&reg_arm>;
306};
307
308&aud2htx {
309	status = "okay";
310};
311
312&eqos {
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_eqos>;
315	phy-mode = "rgmii-id";
316	phy-handle = <&ethphy0>;
317	snps,force_thresh_dma_mode;
318	snps,mtl-tx-config = <&mtl_tx_setup>;
319	snps,mtl-rx-config = <&mtl_rx_setup>;
320	status = "okay";
321
322	mdio {
323		compatible = "snps,dwmac-mdio";
324		#address-cells = <1>;
325		#size-cells = <0>;
326
327		ethphy0: ethernet-phy@1 {
328			compatible = "ethernet-phy-ieee802.3-c22";
329			reg = <1>;
330			eee-broken-1000t;
331			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
332			reset-assert-us = <10000>;
333			reset-deassert-us = <80000>;
334			realtek,clkout-disable;
335		};
336	};
337
338	mtl_tx_setup: tx-queues-config {
339		snps,tx-queues-to-use = <5>;
340
341		queue0 {
342			snps,dcb-algorithm;
343			snps,priority = <0x1>;
344		};
345
346		queue1 {
347			snps,dcb-algorithm;
348			snps,priority = <0x2>;
349		};
350
351		queue2 {
352			snps,dcb-algorithm;
353			snps,priority = <0x4>;
354		};
355
356		queue3 {
357			snps,dcb-algorithm;
358			snps,priority = <0x8>;
359		};
360
361		queue4 {
362			snps,dcb-algorithm;
363			snps,priority = <0xf0>;
364		};
365	};
366
367	mtl_rx_setup: rx-queues-config {
368		snps,rx-queues-to-use = <5>;
369		snps,rx-sched-sp;
370
371		queue0 {
372			snps,dcb-algorithm;
373			snps,priority = <0x1>;
374			snps,map-to-dma-channel = <0>;
375		};
376
377		queue1 {
378			snps,dcb-algorithm;
379			snps,priority = <0x2>;
380			snps,map-to-dma-channel = <1>;
381		};
382
383		queue2 {
384			snps,dcb-algorithm;
385			snps,priority = <0x4>;
386			snps,map-to-dma-channel = <2>;
387		};
388
389		queue3 {
390			snps,dcb-algorithm;
391			snps,priority = <0x8>;
392			snps,map-to-dma-channel = <3>;
393		};
394
395		queue4 {
396			snps,dcb-algorithm;
397			snps,priority = <0xf0>;
398			snps,map-to-dma-channel = <4>;
399		};
400	};
401};
402
403&fec {
404	pinctrl-names = "default";
405	pinctrl-0 = <&pinctrl_fec>;
406	phy-mode = "rgmii-id";
407	phy-handle = <&ethphy1>;
408	fsl,magic-packet;
409	status = "okay";
410
411	mdio {
412		#address-cells = <1>;
413		#size-cells = <0>;
414
415		ethphy1: ethernet-phy@1 {
416			compatible = "ethernet-phy-ieee802.3-c22";
417			reg = <1>;
418			eee-broken-1000t;
419			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
420			reset-assert-us = <10000>;
421			reset-deassert-us = <80000>;
422			realtek,clkout-disable;
423		};
424	};
425};
426
427&flexcan1 {
428	pinctrl-names = "default";
429	pinctrl-0 = <&pinctrl_flexcan1>;
430	xceiver-supply = <&reg_can1_stby>;
431	status = "okay";
432};
433
434&flexcan2 {
435	pinctrl-names = "default";
436	pinctrl-0 = <&pinctrl_flexcan2>;
437	xceiver-supply = <&reg_can2_stby>;
438	status = "disabled";/* can2 pin conflict with pdm */
439};
440
441&hdmi_pvi {
442	status = "okay";
443};
444
445&hdmi_tx {
446	pinctrl-names = "default";
447	pinctrl-0 = <&pinctrl_hdmi>;
448	status = "okay";
449
450	ports {
451		port@1 {
452			hdmi_tx_out: endpoint {
453				remote-endpoint = <&hdmi_in>;
454			};
455		};
456	};
457};
458
459&hdmi_tx_phy {
460	status = "okay";
461};
462
463&i2c1 {
464	clock-frequency = <400000>;
465	pinctrl-names = "default";
466	pinctrl-0 = <&pinctrl_i2c1>;
467	status = "okay";
468
469	pmic@25 {
470		compatible = "nxp,pca9450c";
471		reg = <0x25>;
472		pinctrl-names = "default";
473		pinctrl-0 = <&pinctrl_pmic>;
474		interrupt-parent = <&gpio1>;
475		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
476
477		regulators {
478			BUCK1 {
479				regulator-name = "BUCK1";
480				regulator-min-microvolt = <720000>;
481				regulator-max-microvolt = <1000000>;
482				regulator-boot-on;
483				regulator-always-on;
484				regulator-ramp-delay = <3125>;
485			};
486
487			reg_arm: BUCK2 {
488				regulator-name = "BUCK2";
489				regulator-min-microvolt = <720000>;
490				regulator-max-microvolt = <1025000>;
491				regulator-boot-on;
492				regulator-always-on;
493				regulator-ramp-delay = <3125>;
494				nxp,dvs-run-voltage = <950000>;
495				nxp,dvs-standby-voltage = <850000>;
496			};
497
498			BUCK4 {
499				regulator-name = "BUCK4";
500				regulator-min-microvolt = <3000000>;
501				regulator-max-microvolt = <3600000>;
502				regulator-boot-on;
503				regulator-always-on;
504			};
505
506			reg_buck5: BUCK5 {
507				regulator-name = "BUCK5";
508				regulator-min-microvolt = <1650000>;
509				regulator-max-microvolt = <1950000>;
510				regulator-boot-on;
511				regulator-always-on;
512			};
513
514			BUCK6 {
515				regulator-name = "BUCK6";
516				regulator-min-microvolt = <1045000>;
517				regulator-max-microvolt = <1155000>;
518				regulator-boot-on;
519				regulator-always-on;
520			};
521
522			LDO1 {
523				regulator-name = "LDO1";
524				regulator-min-microvolt = <1650000>;
525				regulator-max-microvolt = <1950000>;
526				regulator-boot-on;
527				regulator-always-on;
528			};
529
530			LDO3 {
531				regulator-name = "LDO3";
532				regulator-min-microvolt = <1710000>;
533				regulator-max-microvolt = <1890000>;
534				regulator-boot-on;
535				regulator-always-on;
536			};
537
538			LDO5 {
539				regulator-name = "LDO5";
540				regulator-min-microvolt = <1800000>;
541				regulator-max-microvolt = <3300000>;
542				regulator-boot-on;
543				regulator-always-on;
544			};
545		};
546	};
547};
548
549&i2c2 {
550	clock-frequency = <400000>;
551	pinctrl-names = "default";
552	pinctrl-0 = <&pinctrl_i2c2>;
553	status = "okay";
554
555	hdmi@3d {
556		compatible = "adi,adv7535";
557		reg = <0x3d>;
558		interrupt-parent = <&gpio1>;
559		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
560		adi,dsi-lanes = <4>;
561		avdd-supply = <&reg_buck5>;
562		dvdd-supply = <&reg_buck5>;
563		pvdd-supply = <&reg_buck5>;
564		a2vdd-supply = <&reg_buck5>;
565		v3p3-supply = <&reg_vext_3v3>;
566		v1p2-supply = <&reg_buck5>;
567
568		ports {
569			#address-cells = <1>;
570			#size-cells = <0>;
571
572			port@0 {
573				reg = <0>;
574
575				adv7535_in: endpoint {
576					remote-endpoint = <&dsi_out>;
577				};
578			};
579
580			port@1 {
581				reg = <1>;
582
583				adv7535_out: endpoint {
584					remote-endpoint = <&hdmi_connector_in>;
585				};
586			};
587
588		};
589	};
590};
591
592&i2c3 {
593	clock-frequency = <400000>;
594	pinctrl-names = "default";
595	pinctrl-0 = <&pinctrl_i2c3>;
596	status = "okay";
597
598	wm8960: codec@1a {
599		compatible = "wlf,wm8960";
600		reg = <0x1a>;
601		#sound-dai-cells = <0>;
602		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
603		clock-names = "mclk";
604		wlf,shared-lrclk;
605		wlf,hp-cfg = <3 2 3>;
606		wlf,gpio-cfg = <1 3>;
607		AVDD-supply = <&reg_audio_3v3>;
608		DBVDD-supply = <&reg_audio_1v8>;
609		DCVDD-supply = <&reg_audio_1v8>;
610		SPKVDD1-supply = <&reg_audio_pwr>;
611		SPKVDD2-supply = <&reg_audio_pwr>;
612	};
613
614	pca6416: gpio@20 {
615		compatible = "ti,tca6416";
616		reg = <0x20>;
617		gpio-controller;
618		#gpio-cells = <2>;
619		interrupt-controller;
620		#interrupt-cells = <2>;
621		pinctrl-names = "default";
622		pinctrl-0 = <&pinctrl_pca6416_int>;
623		interrupt-parent = <&gpio1>;
624		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
625		gpio-line-names = "EXT_PWREN1",
626			"EXT_PWREN2",
627			"CAN1/I2C5_SEL",
628			"PDM/CAN2_SEL",
629			"FAN_EN",
630			"PWR_MEAS_IO1",
631			"PWR_MEAS_IO2",
632			"EXP_P0_7",
633			"EXP_P1_0",
634			"EXP_P1_1",
635			"EXP_P1_2",
636			"EXP_P1_3",
637			"EXP_P1_4",
638			"EXP_P1_5",
639			"EXP_P1_6",
640			"EXP_P1_7";
641	};
642};
643
644/* I2C on expansion connector J22. */
645&i2c5 {
646	clock-frequency = <100000>; /* Lower clock speed for external bus. */
647	pinctrl-names = "default";
648	pinctrl-0 = <&pinctrl_i2c5>;
649	status = "disabled"; /* can1 pins conflict with i2c5 */
650
651	/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
652	 *     LOW:  CAN1 (default, pull-down)
653	 *     HIGH: I2C5
654	 * You need to set it to high to enable I2C5 (for example, add gpio-hog
655	 * in pca6416 node).
656	 */
657};
658
659&lcdif1 {
660	status = "okay";
661};
662
663&lcdif3 {
664	status = "okay";
665};
666
667&micfil {
668	#sound-dai-cells = <0>;
669	pinctrl-names = "default";
670	pinctrl-0 = <&pinctrl_pdm>;
671	assigned-clocks = <&clk IMX8MP_CLK_PDM>;
672	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
673	assigned-clock-rates = <196608000>;
674	status = "okay";
675};
676
677&mipi_dsi {
678	samsung,esc-clock-frequency = <10000000>;
679	status = "okay";
680
681	ports {
682		port@1 {
683			reg = <1>;
684
685			dsi_out: endpoint {
686				remote-endpoint = <&adv7535_in>;
687				data-lanes = <1 2 3 4>;
688			};
689		};
690	};
691};
692
693&pcie_phy {
694	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
695	clocks = <&pcie0_refclk>;
696	clock-names = "ref";
697	status = "okay";
698};
699
700&pcie {
701	pinctrl-names = "default";
702	pinctrl-0 = <&pinctrl_pcie0>;
703	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
704	vpcie-supply = <&reg_pcie0>;
705	status = "okay";
706};
707
708&pwm1 {
709	pinctrl-names = "default";
710	pinctrl-0 = <&pinctrl_pwm1>;
711	status = "okay";
712};
713
714&pwm2 {
715	pinctrl-names = "default";
716	pinctrl-0 = <&pinctrl_pwm2>;
717	status = "okay";
718};
719
720&pwm4 {
721	pinctrl-names = "default";
722	pinctrl-0 = <&pinctrl_pwm4>;
723	status = "okay";
724};
725
726&sai2 {
727	#sound-dai-cells = <0>;
728	pinctrl-names = "default";
729	pinctrl-0 = <&pinctrl_sai2>;
730	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
731	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
732	assigned-clock-rates = <12288000>;
733	fsl,sai-mclk-direction-output;
734	status = "okay";
735};
736
737&sai3 {
738	pinctrl-names = "default";
739	pinctrl-0 = <&pinctrl_sai3>;
740	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
741	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
742	assigned-clock-rates = <12288000>;
743	fsl,sai-mclk-direction-output;
744	status = "okay";
745};
746
747&snvs_pwrkey {
748	status = "okay";
749};
750
751&uart1 { /* BT */
752	pinctrl-names = "default";
753	pinctrl-0 = <&pinctrl_uart1>;
754	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
755	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
756	uart-has-rtscts;
757	status = "okay";
758};
759
760&uart2 {
761	/* console */
762	pinctrl-names = "default";
763	pinctrl-0 = <&pinctrl_uart2>;
764	status = "okay";
765};
766
767&usb3_phy1 {
768	status = "okay";
769};
770
771&usb3_1 {
772	status = "okay";
773};
774
775&usb_dwc3_1 {
776	pinctrl-names = "default";
777	pinctrl-0 = <&pinctrl_usb1_vbus>;
778	dr_mode = "host";
779	status = "okay";
780};
781
782&uart3 {
783	pinctrl-names = "default";
784	pinctrl-0 = <&pinctrl_uart3>;
785	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
786	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
787	uart-has-rtscts;
788	status = "okay";
789};
790
791&usdhc2 {
792	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
793	assigned-clock-rates = <400000000>;
794	pinctrl-names = "default", "state_100mhz", "state_200mhz";
795	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
796	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
797	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
798	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
799	vmmc-supply = <&reg_usdhc2_vmmc>;
800	bus-width = <4>;
801	status = "okay";
802};
803
804&usdhc3 {
805	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
806	assigned-clock-rates = <400000000>;
807	pinctrl-names = "default", "state_100mhz", "state_200mhz";
808	pinctrl-0 = <&pinctrl_usdhc3>;
809	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
810	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
811	bus-width = <8>;
812	non-removable;
813	status = "okay";
814};
815
816&wdog1 {
817	pinctrl-names = "default";
818	pinctrl-0 = <&pinctrl_wdog>;
819	fsl,ext-reset-output;
820	status = "okay";
821};
822
823&xcvr {
824	#sound-dai-cells = <0>;
825	status = "okay";
826};
827
828&iomuxc {
829	pinctrl-names = "default";
830	pinctrl-0 = <&pinctrl_hog>;
831
832	pinctrl_audio_pwr_reg: audiopwrreggrp {
833		fsl,pins = <
834			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0xd6
835		>;
836	};
837
838	pinctrl_eqos: eqosgrp {
839		fsl,pins = <
840			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
841			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
842			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
843			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
844			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
845			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
846			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
847			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
848			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
849			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
850			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
851			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
852			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
853			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
854			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10
855		>;
856	};
857
858	pinctrl_fec: fecgrp {
859		fsl,pins = <
860			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2
861			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2
862			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
863			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
864			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
865			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
866			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
867			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
868			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
869			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
870			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
871			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
872			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
873			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
874			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10
875		>;
876	};
877
878	pinctrl_flexcan1: flexcan1grp {
879		fsl,pins = <
880			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
881			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
882		>;
883	};
884
885	pinctrl_flexcan2: flexcan2grp {
886		fsl,pins = <
887			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
888			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
889		>;
890	};
891
892	pinctrl_flexcan1_reg: flexcan1reggrp {
893		fsl,pins = <
894			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
895		>;
896	};
897
898	pinctrl_flexcan2_reg: flexcan2reggrp {
899		fsl,pins = <
900			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
901		>;
902	};
903
904	pinctrl_flexspi0: flexspi0grp {
905		fsl,pins = <
906			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
907			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
908			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
909			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
910			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
911			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
912		>;
913	};
914
915	pinctrl_gpio_led: gpioledgrp {
916		fsl,pins = <
917			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140
918		>;
919	};
920
921	pinctrl_hdmi: hdmigrp {
922		fsl,pins = <
923			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c2
924			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c2
925			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x10
926		>;
927	};
928
929	pinctrl_hog: hoggrp {
930		fsl,pins = <
931			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000010
932		>;
933	};
934
935	pinctrl_i2c1: i2c1grp {
936		fsl,pins = <
937			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
938			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
939		>;
940	};
941
942	pinctrl_i2c2: i2c2grp {
943		fsl,pins = <
944			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
945			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
946		>;
947	};
948
949	pinctrl_i2c3: i2c3grp {
950		fsl,pins = <
951			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
952			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
953		>;
954	};
955
956	pinctrl_i2c5: i2c5grp {
957		fsl,pins = <
958			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2
959			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
960		>;
961	};
962
963	pinctrl_lvds_en: lvdsengrp {
964		fsl,pins = <
965			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x1c0
966		>;
967	};
968
969	pinctrl_pcie0: pcie0grp {
970		fsl,pins = <
971			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x60 /* open drain, pull up */
972			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
973		>;
974	};
975
976	pinctrl_pcie0_reg: pcie0reggrp {
977		fsl,pins = <
978			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40
979		>;
980	};
981
982	pinctrl_pdm: pdmgrp {
983		fsl,pins = <
984			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6
985			MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00	0xd6
986			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01	0xd6
987			MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02	0xd6
988			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03	0xd6
989		>;
990	};
991
992	pinctrl_pmic: pmicgrp {
993		fsl,pins = <
994			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0
995		>;
996	};
997
998	pinctrl_pca6416_int: pca6416_int_grp {
999		fsl,pins = <
1000			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x146 /* Input pull-up. */
1001		>;
1002	};
1003
1004	pinctrl_pwm1: pwm1grp {
1005		fsl,pins = <
1006			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116
1007		>;
1008	};
1009
1010	pinctrl_pwm2: pwm2grp {
1011		fsl,pins = <
1012			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116
1013		>;
1014	};
1015
1016	pinctrl_pwm4: pwm4grp {
1017		fsl,pins = <
1018			MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT	0x116
1019		>;
1020	};
1021
1022	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
1023		fsl,pins = <
1024			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
1025		>;
1026	};
1027
1028	pinctrl_uart1: uart1grp {
1029		fsl,pins = <
1030			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
1031			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
1032			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
1033			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
1034		>;
1035	};
1036
1037	pinctrl_sai2: sai2grp {
1038		fsl,pins = <
1039			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6
1040			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6
1041			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6
1042			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00	0xd6
1043		>;
1044	};
1045
1046	pinctrl_sai3: sai3grp {
1047		fsl,pins = <
1048			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
1049			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
1050			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
1051			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
1052			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
1053		>;
1054	};
1055
1056	pinctrl_uart2: uart2grp {
1057		fsl,pins = <
1058			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
1059			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
1060		>;
1061	};
1062
1063	pinctrl_usb1_vbus: usb1grp {
1064		fsl,pins = <
1065			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
1066		>;
1067	};
1068
1069	pinctrl_uart3: uart3grp {
1070		fsl,pins = <
1071			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
1072			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
1073			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
1074			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
1075		>;
1076	};
1077
1078	pinctrl_usdhc2: usdhc2grp {
1079		fsl,pins = <
1080			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
1081			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
1082			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
1083			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
1084			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
1085			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
1086			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
1087		>;
1088	};
1089
1090	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1091		fsl,pins = <
1092			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
1093			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
1094			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
1095			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
1096			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
1097			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
1098			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1099		>;
1100	};
1101
1102	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1103		fsl,pins = <
1104			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
1105			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
1106			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
1107			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
1108			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
1109			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
1110			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1111		>;
1112	};
1113
1114	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
1115		fsl,pins = <
1116			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
1117		>;
1118	};
1119
1120	pinctrl_usdhc3: usdhc3grp {
1121		fsl,pins = <
1122			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
1123			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
1124			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
1125			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
1126			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
1127			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
1128			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
1129			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
1130			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
1131			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
1132			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
1133		>;
1134	};
1135
1136	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1137		fsl,pins = <
1138			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
1139			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
1140			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
1141			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
1142			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
1143			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
1144			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
1145			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
1146			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
1147			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
1148			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
1149		>;
1150	};
1151
1152	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1153		fsl,pins = <
1154			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
1155			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
1156			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
1157			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
1158			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
1159			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
1160			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
1161			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
1162			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
1163			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
1164			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
1165		>;
1166	};
1167
1168	pinctrl_wdog: wdoggrp {
1169		fsl,pins = <
1170			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
1171		>;
1172	};
1173};
1174