1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mm-kontron-sl.dtsi"
9
10/ {
11	model = "Kontron BL i.MX8MM (N801X S)";
12	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
13
14	aliases {
15		ethernet1 = &usbnet;
16		rtc0 = &rx8900;
17		rtc1 = &snvs_rtc;
18	};
19
20	/* fixed crystal dedicated to mcp2515 */
21	osc_can: clock-osc-can {
22		compatible = "fixed-clock";
23		#clock-cells = <0>;
24		clock-frequency = <16000000>;
25		clock-output-names = "osc-can";
26	};
27
28	hdmi-out {
29		compatible = "hdmi-connector";
30		type = "a";
31
32		port {
33			hdmi_in_conn: endpoint {
34				remote-endpoint = <&bridge_out_conn>;
35			};
36		};
37	};
38
39	leds {
40		compatible = "gpio-leds";
41		pinctrl-names = "default";
42		pinctrl-0 = <&pinctrl_gpio_led>;
43
44		led1 {
45			label = "led1";
46			gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
47			linux,default-trigger = "heartbeat";
48		};
49
50		led2 {
51			label = "led2";
52			gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
53		};
54
55		led3 {
56			label = "led3";
57			gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
58		};
59
60		led4 {
61			label = "led4";
62			gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
63		};
64
65		led5 {
66			label = "led5";
67			gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
68		};
69
70		led6 {
71			label = "led6";
72			gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
73		};
74	};
75
76	pwm-beeper {
77		compatible = "pwm-beeper";
78		pwms = <&pwm2 0 5000 0>;
79	};
80
81	reg_rst_eth2: regulator-rst-eth2 {
82		compatible = "regulator-fixed";
83		regulator-name = "rst-usb-eth2";
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_usb_eth2>;
86		gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
87		enable-active-high;
88		regulator-always-on;
89	};
90
91	reg_vdd_5v: regulator-5v {
92		compatible = "regulator-fixed";
93		regulator-name = "vdd-5v";
94		regulator-min-microvolt = <5000000>;
95		regulator-max-microvolt = <5000000>;
96	};
97};
98
99&ecspi2 {
100	pinctrl-names = "default";
101	pinctrl-0 = <&pinctrl_ecspi2>;
102	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
103	status = "okay";
104
105	can0: can@0 {
106		compatible = "microchip,mcp2515";
107		reg = <0>;
108		pinctrl-names = "default";
109		pinctrl-0 = <&pinctrl_can>;
110		clocks = <&osc_can>;
111		interrupt-parent = <&gpio4>;
112		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
113		spi-max-frequency = <10000000>;
114		vdd-supply = <&reg_vdd_3v3>;
115		xceiver-supply = <&reg_vdd_5v>;
116	};
117};
118
119&ecspi3 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_ecspi3>;
122	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
123	status = "okay";
124};
125
126&fec1 {
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_enet>;
129	phy-connection-type = "rgmii-rxid";
130	phy-handle = <&ethphy>;
131	status = "okay";
132
133	mdio {
134		#address-cells = <1>;
135		#size-cells = <0>;
136
137		ethphy: ethernet-phy@0 {
138			reg = <0>;
139			reset-assert-us = <1>;
140			reset-deassert-us = <15000>;
141			reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
142		};
143	};
144};
145
146&gpio4 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_gpio4>;
149
150	dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog {
151		gpio-hog;
152		gpios = <14 GPIO_ACTIVE_HIGH>;
153		output-high;
154		line-name = "dsi-mux-sel";
155	};
156
157	dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog {
158		gpio-hog;
159		gpios = <14 GPIO_ACTIVE_HIGH>;
160		output-low;
161		line-name = "dsi-mux-sel";
162		status = "disabled";
163	};
164
165	dsi-mux-oe-hog {
166		gpio-hog;
167		gpios = <15 GPIO_ACTIVE_LOW>;
168		output-high;
169		line-name = "dsi-mux-oe";
170	};
171};
172
173&i2c3 {
174	clock-frequency = <400000>;
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_i2c3>;
177	status = "okay";
178
179	lvds: bridge@2c {
180		compatible = "ti,sn65dsi84";
181		reg = <0x2c>;
182		enable-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
183		pinctrl-names = "default";
184		pinctrl-0 = <&pinctrl_sn65dsi84>;
185		status = "disabled";
186	};
187
188	hdmi: hdmi@39 {
189		compatible = "adi,adv7535";
190		reg = <0x39>;
191		pinctrl-names = "default";
192		pinctrl-0 = <&pinctrl_adv7535>;
193		adi,dsi-lanes = <4>;
194		interrupt-parent = <&gpio4>;
195		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
196		a2vdd-supply = <&reg_vdd_1v8>;
197		avdd-supply = <&reg_vdd_1v8>;
198		dvdd-supply = <&reg_vdd_1v8>;
199		pvdd-supply = <&reg_vdd_1v8>;
200		v1p2-supply = <&reg_vdd_1v8>;
201		v3p3-supply = <&reg_vdd_3v3>;
202
203		ports {
204			#address-cells = <1>;
205			#size-cells = <0>;
206
207			port@0 {
208				reg = <0>;
209
210				bridge_in_dsi_hdmi: endpoint {
211					remote-endpoint = <&mipi_dsi_out>;
212				};
213			};
214
215			port@1 {
216				reg = <1>;
217
218				bridge_out_conn: endpoint {
219					remote-endpoint = <&hdmi_in_conn>;
220				};
221			};
222		};
223	};
224};
225
226&i2c4 {
227	clock-frequency = <100000>;
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_i2c4>;
230	status = "okay";
231
232	rx8900: rtc@32 {
233		compatible = "epson,rx8900";
234		reg = <0x32>;
235	};
236};
237
238&lcdif {
239	status = "okay";
240};
241
242&mipi_dsi {
243	samsung,esc-clock-frequency = <54000000>;
244	status = "okay";
245};
246
247&mipi_dsi_out {
248	remote-endpoint = <&bridge_in_dsi_hdmi>;
249};
250
251&pwm2 {
252	pinctrl-names = "default";
253	pinctrl-0 = <&pinctrl_pwm2>;
254	status = "okay";
255};
256
257&reg_nvcc_sd {
258	sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
259};
260
261&uart1 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&pinctrl_uart1>;
264	uart-has-rtscts;
265	status = "okay";
266};
267
268&uart2 {
269	pinctrl-names = "default";
270	pinctrl-0 = <&pinctrl_uart2>;
271	linux,rs485-enabled-at-boot-time;
272	uart-has-rtscts;
273	status = "okay";
274};
275
276&usbotg1 {
277	dr_mode = "otg";
278	over-current-active-low;
279	status = "okay";
280};
281
282&usbotg2 {
283	dr_mode = "host";
284	disable-over-current;
285	#address-cells = <1>;
286	#size-cells = <0>;
287	status = "okay";
288
289	usb1@1 {
290		compatible = "usb424,9514";
291		reg = <1>;
292		#address-cells = <1>;
293		#size-cells = <0>;
294
295		usbnet: ethernet@1 {
296			compatible = "usb424,ec00";
297			reg = <1>;
298			local-mac-address = [ 00 00 00 00 00 00 ];
299		};
300	};
301};
302
303&usdhc2 {
304	pinctrl-names = "default", "state_100mhz", "state_200mhz";
305	pinctrl-0 = <&pinctrl_usdhc2>;
306	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
307	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
308	vmmc-supply = <&reg_vdd_3v3>;
309	vqmmc-supply = <&reg_nvcc_sd>;
310	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
311	status = "okay";
312};
313
314&iomuxc {
315	pinctrl-names = "default";
316	pinctrl-0 = <&pinctrl_gpio>;
317
318	pinctrl_adv7535: adv7535grp {
319		fsl,pins = <
320			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19
321		>;
322	};
323
324	pinctrl_can: cangrp {
325		fsl,pins = <
326			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19
327		>;
328	};
329
330	pinctrl_ecspi2: ecspi2grp {
331		fsl,pins = <
332			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
333			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
334			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
335			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
336		>;
337	};
338
339	pinctrl_ecspi3: ecspi3grp {
340		fsl,pins = <
341			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82
342			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82
343			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82
344			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19
345		>;
346	};
347
348	pinctrl_enet: enetgrp {
349		fsl,pins = <
350			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
351			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
352			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
353			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
354			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
355			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
356			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
357			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
358			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
359			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
360			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
361			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
362			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
363			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
364			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19 /* PHY RST */
365			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* ETH IRQ */
366		>;
367	};
368
369	pinctrl_gpio_led: gpioledgrp {
370		fsl,pins = <
371			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
372			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19
373			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19
374			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x19
375			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19
376			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19
377			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19
378		>;
379	};
380
381	pinctrl_gpio: gpiogrp {
382		fsl,pins = <
383			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
384			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
385			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
386			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19
387			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
388			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
389			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
390			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19
391		>;
392	};
393
394	pinctrl_gpio4: gpio4grp {
395		fsl,pins = <
396			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19
397			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19
398		>;
399	};
400
401	pinctrl_i2c3: i2c3grp {
402		fsl,pins = <
403			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000083
404			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000083
405		>;
406	};
407
408	pinctrl_i2c4: i2c4grp {
409		fsl,pins = <
410			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000083
411			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000083
412		>;
413	};
414
415	pinctrl_pwm2: pwm2grp {
416		fsl,pins = <
417			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x19
418		>;
419	};
420
421	pinctrl_sn65dsi84: sn65dsi84grp {
422		fsl,pins = <
423			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26		0x19
424			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x19
425		>;
426	};
427
428	pinctrl_uart1: uart1grp {
429		fsl,pins = <
430			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x0
431			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x0
432			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x0
433			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x0
434		>;
435	};
436
437	pinctrl_uart2: uart2grp {
438		fsl,pins = <
439			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x0
440			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x0
441			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x0
442			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x0
443		>;
444	};
445
446	pinctrl_usb_eth2: usbeth2grp {
447		fsl,pins = <
448			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19
449		>;
450	};
451
452	pinctrl_usdhc2: usdhc2grp {
453		fsl,pins = <
454			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x90
455			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
456			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
457			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
458			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
459			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
460			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
461			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000d0
462		>;
463	};
464
465	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
466		fsl,pins = <
467			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x94
468			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
469			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
470			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
471			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
472			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
473			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
474			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000d0
475		>;
476	};
477
478	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
479		fsl,pins = <
480			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x96
481			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
482			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
483			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
484			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
485			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
486			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
487			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x40000d0
488		>;
489	};
490};
491