1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/pwm/pwm.h>
7
8/ {
9	chosen {
10		stdout-path = &lpuart1;
11	};
12
13	/* Apalis BKL1 */
14	backlight: backlight {
15		compatible = "pwm-backlight";
16		pinctrl-names = "default";
17		pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18		brightness-levels = <0 45 63 88 119 158 203 255>;
19		default-brightness-level = <4>;
20		enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
21		/* TODO: hook-up to Apalis BKL1_PWM */
22		status = "disabled";
23	};
24
25	gpio_fan: gpio-fan {
26		compatible = "gpio-fan";
27		pinctrl-names = "default";
28		pinctrl-0 = <&pinctrl_gpio8>;
29		gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
30		gpio-fan,speed-map = <	 0 0
31				      3000 1>;
32	};
33
34	/* TODO: LVDS Panel */
35
36	/* TODO: Shared PCIe/SATA Reference Clock */
37
38	/* TODO: PCIe Wi-Fi Reference Clock */
39
40	/*
41	 * Power management bus used to control LDO1OUT of the
42	 * second PMIC PF8100. This is used for controlling voltage levels of
43	 * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
44	 *
45	 * IMX_SC_R_BOARD_R1 for 3.3V
46	 * IMX_SC_R_BOARD_R2 for 1.8V
47	 * IMX_SC_R_BOARD_R3 for 2.5V
48	 * Note that for 2.5V operation the pad muxing needs to be changed,
49	 * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
50	 *
51	 * those power domains are mutually exclusive.
52	 */
53	reg_ext_rgmii: regulator-ext-rgmii {
54		compatible = "regulator-fixed";
55		power-domains = <&pd IMX_SC_R_BOARD_R1>;
56		regulator-max-microvolt = <3300000>;
57		regulator-min-microvolt = <3300000>;
58		regulator-name = "VDD_EXT_RGMII (LDO1)";
59
60		regulator-state-mem {
61			regulator-off-in-suspend;
62		};
63	};
64
65	reg_module_3v3: regulator-module-3v3 {
66		compatible = "regulator-fixed";
67		regulator-max-microvolt = <3300000>;
68		regulator-min-microvolt = <3300000>;
69		regulator-name = "+V3.3";
70	};
71
72	reg_module_3v3_avdd: regulator-module-3v3-avdd {
73		compatible = "regulator-fixed";
74		regulator-max-microvolt = <3300000>;
75		regulator-min-microvolt = <3300000>;
76		regulator-name = "+V3.3_AUDIO";
77	};
78
79	reg_module_wifi: regulator-module-wifi {
80		compatible = "regulator-fixed";
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_wifi_pdn>;
83		gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
84		enable-active-high;
85		regulator-always-on;
86		regulator-name = "wifi_pwrdn_fake_regulator";
87		regulator-settling-time-us = <100>;
88	};
89
90	reg_pcie_switch: regulator-pcie-switch {
91		compatible = "regulator-fixed";
92		pinctrl-names = "default";
93		pinctrl-0 = <&pinctrl_gpio7>;
94		gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
95		enable-active-high;
96		regulator-max-microvolt = <1800000>;
97		regulator-min-microvolt = <1800000>;
98		regulator-name = "pcie_switch";
99		startup-delay-us = <100000>;
100	};
101
102	reg_usb_host_vbus: regulator-usb-host-vbus {
103		compatible = "regulator-fixed";
104		pinctrl-names = "default";
105		pinctrl-0 = <&pinctrl_usbh_en>;
106		/* Apalis USBH_EN */
107		gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
108		enable-active-high;
109		regulator-always-on;
110		regulator-max-microvolt = <5000000>;
111		regulator-min-microvolt = <5000000>;
112		regulator-name = "usb-host-vbus";
113	};
114
115	reg_usb_hsic: regulator-usb-hsic {
116		compatible = "regulator-fixed";
117		regulator-max-microvolt = <3000000>;
118		regulator-min-microvolt = <3000000>;
119		regulator-name = "usb-hsic-dummy";
120	};
121
122	reg_usb_phy: regulator-usb-hsic1 {
123		compatible = "regulator-fixed";
124		regulator-max-microvolt = <3000000>;
125		regulator-min-microvolt = <3000000>;
126		regulator-name = "usb-phy-dummy";
127	};
128
129	reg_vref_1v8: regulator-vref-1v8 {
130		compatible = "regulator-fixed";
131		regulator-name = "+V1.8";
132		regulator-min-microvolt = <1800000>;
133		regulator-max-microvolt = <1800000>;
134	};
135
136	reserved-memory {
137		#address-cells = <2>;
138		#size-cells = <2>;
139		ranges;
140
141		decoder_boot: decoder-boot@84000000 {
142			reg = <0 0x84000000 0 0x2000000>;
143			no-map;
144		};
145
146		encoder1_boot: encoder1-boot@86000000 {
147			reg = <0 0x86000000 0 0x200000>;
148			no-map;
149		};
150
151		encoder2_boot: encoder2-boot@86200000 {
152			reg = <0 0x86200000 0 0x200000>;
153			no-map;
154		};
155
156		/*
157		 * reserved-memory layout
158		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
159		 * Shouldn't be used at A core and Linux side.
160		 *
161		 */
162		m4_reserved: m4@88000000 {
163			reg = <0 0x88000000 0 0x8000000>;
164			no-map;
165		};
166
167		rpmsg_reserved: rpmsg@90200000 {
168			reg = <0 0x90200000 0 0x200000>;
169			no-map;
170		};
171
172		vdevbuffer: vdevbuffer@90400000 {
173			compatible = "shared-dma-pool";
174			reg = <0 0x90400000 0 0x100000>;
175			no-map;
176		};
177
178		decoder_rpc: decoder-rpc@92000000 {
179			reg = <0 0x92000000 0 0x200000>;
180			no-map;
181		};
182
183		dsp_reserved: dsp@92400000 {
184			reg = <0 0x92400000 0 0x2000000>;
185			no-map;
186		};
187
188		encoder1_rpc: encoder1-rpc@94400000 {
189			reg = <0 0x94400000 0 0x700000>;
190			no-map;
191		};
192
193		encoder2_rpc: encoder2-rpc@94b00000 {
194			reg = <0 0x94b00000 0 0x700000>;
195			no-map;
196		};
197
198		/* global autoconfigured region for contiguous allocations */
199		linux,cma {
200			compatible = "shared-dma-pool";
201			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
202			linux,cma-default;
203			reusable;
204			size = <0 0x3c000000>;
205		};
206	};
207
208	sound {
209		compatible = "simple-audio-card";
210		simple-audio-card,bitclock-master = <&dailink_master>;
211		simple-audio-card,format = "i2s";
212		simple-audio-card,frame-master = <&dailink_master>;
213		simple-audio-card,name = "apalis-imx8qm";
214
215		simple-audio-card,cpu {
216			sound-dai = <&sai1>;
217		};
218
219		dailink_master: simple-audio-card,codec {
220			sound-dai = <&sgtl5000>;
221		};
222	};
223
224	/* TODO: HDMI Audio */
225
226	/* Apalis SPDIF1 */
227	sound-spdif {
228		compatible = "fsl,imx-audio-spdif";
229		model = "imx-spdif";
230		spdif-controller = <&spdif0>;
231		spdif-in;
232		spdif-out;
233	};
234
235	touchscreen: touchscreen {
236		compatible = "toradex,vf50-touchscreen";
237		interrupt-parent = <&lsio_gpio3>;
238		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
239		pinctrl-names = "idle", "default";
240		pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>;
241		pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>;
242		io-channels = <&adc1 2>, <&adc1 1>,
243			      <&adc1 0>, <&adc1 3>;
244		vf50-ts-min-pressure = <200>;
245		xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
246		xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>;
247		yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>;
248		ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>;
249		/*
250		 * NOTE: you must remove the pinctrl-adc1 from the adc1
251		 * node below to use the touchscreen
252		 */
253		status = "disabled";
254	};
255
256};
257
258&asrc0 {
259	fsl,asrc-rate  = <48000>;
260};
261
262&adc0 {
263	pinctrl-names = "default";
264	pinctrl-0 = <&pinctrl_adc0>;
265};
266
267&adc1 {
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_adc1>;
270};
271
272/* TODO: Asynchronous Sample Rate Converter (ASRC) */
273
274&cpu_alert0 {
275	temperature = <95000>;
276};
277
278&cpu_alert1 {
279	temperature = <95000>;
280};
281
282&cpu_crit0 {
283	temperature = <105000>;
284};
285
286&cpu_crit1 {
287	temperature = <105000>;
288};
289
290&drc_alert0 {
291	temperature = <95000>;
292};
293
294&drc_crit0 {
295	temperature = <105000>;
296};
297
298/* Apalis ETH1 */
299&fec1 {
300	pinctrl-names = "default", "sleep";
301	pinctrl-0 = <&pinctrl_fec1>;
302	pinctrl-1 = <&pinctrl_fec1_sleep>;
303	fsl,magic-packet;
304	phy-handle = <&ethphy0>;
305	phy-mode = "rgmii-id";
306
307	mdio {
308		#address-cells = <1>;
309		#size-cells = <0>;
310
311		ethphy0: ethernet-phy@7 {
312			compatible = "ethernet-phy-ieee802.3-c22";
313			reg = <7>;
314			interrupt-parent = <&lsio_gpio1>;
315			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
316			micrel,led-mode = <0>;
317			reset-assert-us = <2>;
318			reset-deassert-us = <2>;
319			reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
320		};
321	};
322};
323
324/* Apalis CAN1 */
325&flexcan1 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&pinctrl_flexcan1>;
328};
329
330/* Apalis CAN2 */
331&flexcan2 {
332	pinctrl-names = "default";
333	pinctrl-0 = <&pinctrl_flexcan2>;
334};
335
336/* Apalis CAN3 (optional) */
337&flexcan3 {
338	pinctrl-names = "default";
339	pinctrl-0 = <&pinctrl_flexcan3>;
340};
341
342/* TODO: Apalis HDMI1 */
343
344&gpu_alert0 {
345	temperature = <95000>;
346};
347
348&gpu_alert1 {
349	temperature = <95000>;
350};
351
352&gpu_crit0 {
353	temperature = <105000>;
354};
355
356&gpu_crit1 {
357	temperature = <105000>;
358};
359
360/* On-module I2C */
361&i2c1 {
362	pinctrl-names = "default";
363	pinctrl-0 = <&pinctrl_lpi2c1>;
364	#address-cells = <1>;
365	#size-cells = <0>;
366	clock-frequency = <100000>;
367	status = "okay";
368
369	/* USB3503A */
370	usb-hub@8 {
371		compatible = "smsc,usb3503a";
372		reg = <0x08>;
373		pinctrl-names = "default";
374		pinctrl-0 = <&pinctrl_usb3503a>;
375		connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>;
376		initial-mode = <1>;
377		intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
378		refclk-frequency = <25000000>;
379		reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
380	};
381
382	/* On Module Audio Codec */
383	sgtl5000: audio-codec@a {
384		compatible = "fsl,sgtl5000";
385		reg = <0x0a>;
386		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
387				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
388				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
389				  <&mclkout0_lpcg IMX_LPCG_CLK_0>;
390		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
391		clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
392		pinctrl-names = "default";
393		pinctrl-0 = <&pinctrl_sgtl5000>;
394		#sound-dai-cells = <0>;
395		VDDA-supply = <&reg_module_3v3_avdd>;
396		VDDD-supply = <&reg_vref_1v8>;
397		VDDIO-supply = <&reg_module_3v3>;
398	};
399};
400
401/* Apalis I2C1 */
402&i2c2 {
403	pinctrl-names = "default";
404	pinctrl-0 = <&pinctrl_lpi2c2>;
405	#address-cells = <1>;
406	#size-cells = <0>;
407	clock-frequency = <100000>;
408
409	atmel_mxt_ts: touch@4a {
410		compatible = "atmel,maxtouch";
411		reg = <0x4a>;
412		interrupt-parent = <&lsio_gpio4>;
413		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;		/* Apalis GPIO5 */
414		pinctrl-names = "default";
415		pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>;
416		reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>;	/* Apalis GPIO6 */
417		status = "disabled";
418	};
419
420	/* M41T0M6 real time clock on carrier board */
421	rtc_i2c: rtc@68 {
422		compatible = "st,m41t0";
423		reg = <0x68>;
424		status = "disabled";
425	};
426};
427
428/* Apalis I2C3 (CAM) */
429&i2c3 {
430	pinctrl-names = "default";
431	pinctrl-0 = <&pinctrl_lpi2c3>;
432	#address-cells = <1>;
433	#size-cells = <0>;
434	clock-frequency = <100000>;
435};
436
437&jpegdec {
438	status = "okay";
439};
440
441&jpegenc {
442	status = "okay";
443};
444
445/* TODO: Apalis LVDS1 */
446
447/* Apalis SPI1 */
448&lpspi0 {
449	pinctrl-names = "default";
450	pinctrl-0 = <&pinctrl_lpspi0>;
451	#address-cells = <1>;
452	#size-cells = <0>;
453	cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
454};
455
456/* Apalis SPI2 */
457&lpspi2 {
458	pinctrl-names = "default";
459	pinctrl-0 = <&pinctrl_lpspi2>;
460	#address-cells = <1>;
461	#size-cells = <0>;
462	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
463};
464
465/* Apalis UART3 */
466&lpuart0 {
467	pinctrl-names = "default";
468	pinctrl-0 = <&pinctrl_lpuart0>;
469};
470
471/* Apalis UART1 */
472&lpuart1 {
473	pinctrl-names = "default";
474	pinctrl-0 = <&pinctrl_lpuart1>;
475};
476
477/* Apalis UART4 */
478&lpuart2 {
479	pinctrl-names = "default";
480	pinctrl-0 = <&pinctrl_lpuart2>;
481};
482
483/* Apalis UART2 */
484&lpuart3 {
485	pinctrl-names = "default";
486	pinctrl-0 = <&pinctrl_lpuart3>;
487};
488
489&lsio_gpio0 {
490	gpio-line-names = "MXM3_279",
491			  "MXM3_277",
492			  "MXM3_135",
493			  "MXM3_203",
494			  "MXM3_201",
495			  "MXM3_275",
496			  "MXM3_110",
497			  "MXM3_120",
498			  "MXM3_1/GPIO1",
499			  "MXM3_3/GPIO2",
500			  "MXM3_124",
501			  "MXM3_122",
502			  "MXM3_5/GPIO3",
503			  "MXM3_7/GPIO4",
504			  "",
505			  "",
506			  "MXM3_4",
507			  "MXM3_211",
508			  "MXM3_209",
509			  "MXM3_2",
510			  "MXM3_136",
511			  "MXM3_134",
512			  "MXM3_6",
513			  "MXM3_8",
514			  "MXM3_112",
515			  "MXM3_118",
516			  "MXM3_114",
517			  "MXM3_116";
518};
519
520&lsio_gpio1 {
521	gpio-line-names = "",
522			  "",
523			  "",
524			  "",
525			  "MXM3_286",
526			  "",
527			  "MXM3_87",
528			  "MXM3_99",
529			  "MXM3_138",
530			  "MXM3_140",
531			  "MXM3_239",
532			  "",
533			  "MXM3_281",
534			  "MXM3_283",
535			  "MXM3_126",
536			  "MXM3_132",
537			  "",
538			  "",
539			  "",
540			  "",
541			  "MXM3_173",
542			  "MXM3_175",
543			  "MXM3_123";
544
545	hdmi-ctrl-hog {
546		pinctrl-names = "default";
547		pinctrl-0 = <&pinctrl_hdmi_ctrl>;
548		gpio-hog;
549		gpios = <30 GPIO_ACTIVE_HIGH>;
550		line-name = "CONNECTOR_IS_HDMI";
551		/* Set signals depending on HDP device type, 0 DP, 1 HDMI */
552		output-high;
553	};
554};
555
556&lsio_gpio2 {
557	gpio-line-names = "",
558			  "",
559			  "",
560			  "",
561			  "",
562			  "",
563			  "",
564			  "MXM3_198",
565			  "MXM3_35",
566			  "MXM3_164",
567			  "",
568			  "",
569			  "",
570			  "",
571			  "MXM3_217",
572			  "MXM3_215",
573			  "",
574			  "",
575			  "MXM3_193",
576			  "MXM3_194",
577			  "MXM3_37",
578			  "",
579			  "MXM3_271",
580			  "MXM3_273",
581			  "MXM3_195",
582			  "MXM3_197",
583			  "MXM3_177",
584			  "MXM3_179",
585			  "MXM3_181",
586			  "MXM3_183",
587			  "MXM3_185",
588			  "MXM3_187";
589
590	pcie-wifi-hog {
591		pinctrl-names = "default";
592		pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
593		gpio-hog;
594		gpios = <11 GPIO_ACTIVE_HIGH>;
595		line-name = "PCIE_WIFI_CLK";
596		output-high;
597	};
598};
599
600&lsio_gpio3 {
601	gpio-line-names = "MXM3_191",
602			  "",
603			  "MXM3_221",
604			  "MXM3_225",
605			  "MXM3_223",
606			  "MXM3_227",
607			  "MXM3_200",
608			  "MXM3_235",
609			  "MXM3_231",
610			  "MXM3_229",
611			  "MXM3_233",
612			  "MXM3_204",
613			  "MXM3_196",
614			  "",
615			  "MXM3_202",
616			  "",
617			  "",
618			  "",
619			  "MXM3_305",
620			  "MXM3_307",
621			  "MXM3_309",
622			  "MXM3_311",
623			  "MXM3_315",
624			  "MXM3_317",
625			  "MXM3_319",
626			  "MXM3_321",
627			  "MXM3_15/GPIO7",
628			  "MXM3_63",
629			  "MXM3_17/GPIO8",
630			  "MXM3_12",
631			  "MXM3_14",
632			  "MXM3_16";
633};
634
635&lsio_gpio4 {
636	gpio-line-names = "MXM3_18",
637			  "MXM3_11/GPIO5",
638			  "MXM3_13/GPIO6",
639			  "MXM3_274",
640			  "MXM3_84",
641			  "MXM3_262",
642			  "MXM3_96",
643			  "",
644			  "",
645			  "",
646			  "",
647			  "",
648			  "MXM3_190",
649			  "",
650			  "",
651			  "",
652			  "MXM3_269",
653			  "MXM3_251",
654			  "MXM3_253",
655			  "MXM3_295",
656			  "MXM3_299",
657			  "MXM3_301",
658			  "MXM3_297",
659			  "MXM3_293",
660			  "MXM3_291",
661			  "MXM3_289",
662			  "MXM3_287";
663
664	/* Enable pcie root / sata ref clock unconditionally */
665	pcie-sata-hog {
666		pinctrl-names = "default";
667		pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
668		gpio-hog;
669		gpios = <11 GPIO_ACTIVE_HIGH>;
670		line-name = "PCIE_SATA_CLK";
671		output-high;
672	};
673};
674
675&lsio_gpio5 {
676	gpio-line-names = "",
677			  "",
678			  "",
679			  "",
680			  "",
681			  "",
682			  "",
683			  "",
684			  "",
685			  "",
686			  "",
687			  "",
688			  "",
689			  "",
690			  "MXM3_150",
691			  "MXM3_160",
692			  "MXM3_162",
693			  "MXM3_144",
694			  "MXM3_146",
695			  "MXM3_148",
696			  "MXM3_152",
697			  "MXM3_156",
698			  "MXM3_158",
699			  "MXM3_159",
700			  "MXM3_184",
701			  "MXM3_180",
702			  "MXM3_186",
703			  "MXM3_188",
704			  "MXM3_176",
705			  "MXM3_178";
706};
707
708&lsio_gpio6 {
709	gpio-line-names = "",
710			  "",
711			  "",
712			  "",
713			  "",
714			  "",
715			  "",
716			  "",
717			  "",
718			  "",
719			  "MXM3_261",
720			  "MXM3_263",
721			  "MXM3_259",
722			  "MXM3_257",
723			  "MXM3_255",
724			  "MXM3_128",
725			  "MXM3_130",
726			  "MXM3_265",
727			  "MXM3_249",
728			  "MXM3_247",
729			  "MXM3_245",
730			  "MXM3_243";
731};
732
733/* Apalis PWM3, MXM3 pin 6 */
734&lsio_pwm0 {
735	pinctrl-names = "default";
736	pinctrl-0 = <&pinctrl_pwm0>;
737	#pwm-cells = <3>;
738};
739
740/* Apalis PWM4, MXM3 pin 8 */
741&lsio_pwm1 {
742	pinctrl-names = "default";
743	pinctrl-0 = <&pinctrl_pwm1>;
744	#pwm-cells = <3>;
745};
746
747/* Apalis PWM1, MXM3 pin 2 */
748&lsio_pwm2 {
749	pinctrl-names = "default";
750	pinctrl-0 = <&pinctrl_pwm2>;
751	#pwm-cells = <3>;
752};
753
754/* Apalis PWM2, MXM3 pin 4 */
755&lsio_pwm3 {
756	pinctrl-names = "default";
757	pinctrl-0 = <&pinctrl_pwm3>;
758	#pwm-cells = <3>;
759};
760
761/* Messaging Units */
762&mu_m0 {
763	status = "okay";
764};
765
766&mu1_m0 {
767	status = "okay";
768};
769
770&mu2_m0 {
771	status = "okay";
772};
773
774/* TODO: Apalis PCIE1 */
775
776/* TODO: On-module Wi-Fi */
777
778/* TODO: Apalis BKL1_PWM */
779
780/* Apalis DAP1 */
781&sai1 {
782	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
783			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
784			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
785			  <&sai1_lpcg IMX_LPCG_CLK_0>;
786	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
787	pinctrl-names = "default";
788	pinctrl-0 = <&pinctrl_sai1>;
789	#sound-dai-cells = <0>;
790	status = "okay";
791};
792
793/* Apalis HDMI Audio */
794&sai5 {
795	assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
796			  <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
797			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
798			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
799			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
800			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
801			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
802			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
803			  <&sai5_lpcg 0>;
804	assigned-clock-parents = <&aud_pll_div0_lpcg 0>, <&aud_rec1_lpcg 0>;
805	assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>,
806			       <722534400>, <45158400>, <11289600>, <49152000>;
807};
808
809/* TODO: Apalis SATA1 */
810
811/* Apalis SPDIF1 */
812&spdif0 {
813	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
814			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
815			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
816	assigned-clock-rates = <786432000>, <49152000>, <12288000>;
817	pinctrl-names = "default";
818	pinctrl-0 = <&pinctrl_spdif0>;
819	status = "okay";
820};
821
822/* TODO: Thermal Zones */
823
824/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
825
826/* Apalis USBH4 */
827&usb3_phy {
828	status = "okay";
829};
830
831&usbotg3 {
832	status = "okay";
833};
834
835&usbotg3_cdns3 {
836	dr_mode = "host";
837};
838
839/* Apalis USBO1 */
840&usbphy1 {
841	phy-3p0-supply = <&reg_usb_phy>;
842	status = "okay";
843};
844
845&usbotg1 {
846	pinctrl-names = "default";
847	pinctrl-0 = <&pinctrl_usbotg1>;
848	adp-disable;
849	hnp-disable;
850	over-current-active-low;
851	power-active-high;
852	srp-disable;
853};
854
855/* On-module eMMC */
856&usdhc1 {
857	pinctrl-names = "default", "state_100mhz", "state_200mhz";
858	pinctrl-0 = <&pinctrl_usdhc1>;
859	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
860	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
861	bus-width = <8>;
862	non-removable;
863	status = "okay";
864};
865
866/* Apalis MMC1 */
867&usdhc2 {
868	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
869	pinctrl-0 = <&pinctrl_usdhc2_4bit>,
870		    <&pinctrl_usdhc2_8bit>,
871		    <&pinctrl_mmc1_cd>;
872	pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
873		    <&pinctrl_usdhc2_8bit_100mhz>,
874		    <&pinctrl_mmc1_cd>;
875	pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
876		    <&pinctrl_usdhc2_8bit_200mhz>,
877		    <&pinctrl_mmc1_cd>;
878	pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
879		    <&pinctrl_usdhc2_8bit_sleep>,
880		    <&pinctrl_mmc1_cd_sleep>;
881	bus-width = <8>;
882	cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
883	no-1-8-v;
884};
885
886/* Apalis SD1 */
887&usdhc3 {
888	pinctrl-names = "default", "state_100mhz", "state_200mhz";
889	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
890	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
891	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
892	bus-width = <4>;
893	cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
894	no-1-8-v;
895};
896
897/* Video Processing Unit */
898&vpu {
899	compatible = "nxp,imx8qm-vpu";
900	status = "okay";
901};
902
903&vpu_core0 {
904	reg = <0x2d080000 0x10000>;
905	memory-region = <&decoder_boot>, <&decoder_rpc>;
906	status = "okay";
907};
908
909&vpu_core1 {
910	reg = <0x2d090000 0x10000>;
911	memory-region = <&encoder1_boot>, <&encoder1_rpc>;
912	status = "okay";
913};
914
915&vpu_core2 {
916	reg = <0x2d0a0000 0x10000>;
917	memory-region = <&encoder2_boot>, <&encoder2_rpc>;
918	status = "okay";
919};
920
921&iomuxc {
922	pinctrl-names = "default";
923	pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
924		    <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
925		    <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
926		    <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
927		    <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
928		    <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
929		    <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
930		    <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
931		    <&pinctrl_usdhc1_gpios>;
932
933	/* Apalis AN1_ADC */
934	pinctrl_adc0: adc0grp {
935		fsl,pins = /* Apalis AN1_ADC0 */
936			   <IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060>,
937			   /* Apalis AN1_ADC1 */
938			   <IMX8QM_ADC_IN1_DMA_ADC0_IN1				0xc0000060>,
939			   /* Apalis AN1_ADC2 */
940			   <IMX8QM_ADC_IN2_DMA_ADC0_IN2				0xc0000060>,
941			   /* Apalis AN1_TSWIP_ADC3 */
942			   <IMX8QM_ADC_IN3_DMA_ADC0_IN3				0xc0000060>;
943	};
944
945	/* Apalis AN1_TS */
946	pinctrl_adc1: adc1grp {
947		fsl,pins = /* Apalis AN1_TSPX */
948			   <IMX8QM_ADC_IN4_DMA_ADC1_IN0				0xc0000060>,
949			   /* Apalis AN1_TSMX */
950			   <IMX8QM_ADC_IN5_DMA_ADC1_IN1				0xc0000060>,
951			   /* Apalis AN1_TSPY */
952			   <IMX8QM_ADC_IN6_DMA_ADC1_IN2				0xc0000060>,
953			   /* Apalis AN1_TSMY */
954			   <IMX8QM_ADC_IN7_DMA_ADC1_IN3				0xc0000060>;
955	};
956
957	/* Apalis CAM1 */
958	pinctrl_cam1_gpios: cam1gpiosgrp {
959		fsl,pins = /* Apalis CAM1_D7 */
960			   <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20		0x00000021>,
961			   /* Apalis CAM1_D6 */
962			   <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21		0x00000021>,
963			   /* Apalis CAM1_D5 */
964			   <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26			0x00000021>,
965			   /* Apalis CAM1_D4 */
966			   <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27			0x00000021>,
967			   /* Apalis CAM1_D3 */
968			   <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28		0x00000021>,
969			   /* Apalis CAM1_D2 */
970			   <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29		0x00000021>,
971			   /* Apalis CAM1_D1 */
972			   <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30		0x00000021>,
973			   /* Apalis CAM1_D0 */
974			   <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31		0x00000021>,
975			   /* Apalis CAM1_PCLK */
976			   <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00			0x00000021>,
977			   /* Apalis CAM1_MCLK */
978			   <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18			0x00000021>,
979			   /* Apalis CAM1_VSYNC */
980			   <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24			0x00000021>,
981			   /* Apalis CAM1_HSYNC */
982			   <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25			0x00000021>;
983	};
984
985	/* Apalis DAP1 */
986	pinctrl_dap1_gpios: dap1gpiosgrp {
987		fsl,pins = /* Apalis DAP1_MCLK */
988			   <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19			0x00000021>,
989			   /* Apalis DAP1_D_OUT */
990			   <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12			0x00000021>,
991			   /* Apalis DAP1_RESET */
992			   <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021>,
993			   /* Apalis DAP1_BIT_CLK */
994			   <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021>,
995			   /* Apalis DAP1_D_IN */
996			   <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14			0x00000021>,
997			   /* Apalis DAP1_SYNC */
998			   <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11			0x00000021>,
999			   /* On-module Wi-Fi_I2S_EN# */
1000			   <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13		0x00000021>;
1001	};
1002
1003	/* Apalis LCD1_G1+2 */
1004	pinctrl_esai0_gpios: esai0gpiosgrp {
1005		fsl,pins = /* Apalis LCD1_G1 */
1006			   <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22			0x00000021>,
1007			   /* Apalis LCD1_G2 */
1008			   <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23			0x00000021>;
1009	};
1010
1011	/* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */
1012	pinctrl_fec1: fec1grp {
1013		fsl,pins = /* Use pads in 3.3V mode */
1014			   <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD			0x000014a0>,
1015			   <IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020>,
1016			   <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO				0x06000020>,
1017			   <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL		0x06000020>,
1018			   <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC			0x06000020>,
1019			   <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020>,
1020			   <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020>,
1021			   <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020>,
1022			   <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020>,
1023			   <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC			0x06000020>,
1024			   <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL		0x06000020>,
1025			   <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020>,
1026			   <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020>,
1027			   <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020>,
1028			   <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020>,
1029			   <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M	0x06000020>,
1030			   /* On-module ETH_RESET# */
1031			   <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11				0x06000020>,
1032			   /* On-module ETH_INT# */
1033			   <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29			0x04000060>;
1034	};
1035
1036	pinctrl_fec1_sleep: fec1-sleepgrp {
1037		fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD		0x000014a0>,
1038			   <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14			0x04000040>,
1039			   <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13			0x04000040>,
1040			   <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31		0x04000040>,
1041			   <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30		0x04000040>,
1042			   <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00		0x04000040>,
1043			   <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01		0x04000040>,
1044			   <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02		0x04000040>,
1045			   <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03		0x04000040>,
1046			   <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04		0x04000040>,
1047			   <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05		0x04000040>,
1048			   <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06		0x04000040>,
1049			   <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07		0x04000040>,
1050			   <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08		0x04000040>,
1051			   <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09		0x04000040>,
1052			   <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15	0x04000040>,
1053			   <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11			0x06000020>,
1054			   <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29		0x04000040>;
1055	};
1056
1057	/* Apalis LCD1_ */
1058	pinctrl_fec2_gpios: fec2gpiosgrp {
1059		fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0>,
1060			   /* Apalis LCD1_R1 */
1061			   <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18			0x00000021>,
1062			   /* Apalis LCD1_R0 */
1063			   <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17			0x00000021>,
1064			   /* Apalis LCD1_G0 */
1065			   <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16	0x00000021>,
1066			   /* Apalis LCD1_R7 */
1067			   <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17		0x00000021>,
1068			   /* Apalis LCD1_DE */
1069			   <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18		0x00000021>,
1070			   /* Apalis LCD1_HSYNC */
1071			   <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19		0x00000021>,
1072			   /* Apalis LCD1_VSYNC */
1073			   <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20		0x00000021>,
1074			   /* Apalis LCD1_PCLK */
1075			   <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21		0x00000021>,
1076			   /* Apalis LCD1_R6 */
1077			   <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11		0x00000021>,
1078			   /* Apalis LCD1_R5 */
1079			   <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10		0x00000021>,
1080			   /* Apalis LCD1_R4 */
1081			   <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12		0x00000021>,
1082			   /* Apalis LCD1_R3 */
1083			   <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13		0x00000021>,
1084			   /* Apalis LCD1_R2 */
1085			   <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14		0x00000021>;
1086	};
1087
1088	/* Apalis CAN1 */
1089	pinctrl_flexcan1: flexcan0grp {
1090		fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x00000021>,
1091			   <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x00000021>;
1092	};
1093
1094	/* Apalis CAN2 */
1095	pinctrl_flexcan2: flexcan1grp {
1096		fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x00000021>,
1097			   <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x00000021>;
1098	};
1099
1100	/* Apalis CAN3 (optional) */
1101	pinctrl_flexcan3: flexcan2grp {
1102		fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x00000021>,
1103			   <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x00000021>;
1104	};
1105
1106	/* Apalis GPIO1 */
1107	pinctrl_gpio1: gpio1grp {
1108		fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08			0x06000021>;
1109	};
1110
1111	/* Apalis GPIO2 */
1112	pinctrl_gpio2: gpio2grp {
1113		fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09			0x06000021>;
1114	};
1115
1116	/* Apalis GPIO3 */
1117	pinctrl_gpio3: gpio3grp {
1118		fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12			0x06000021>;
1119	};
1120
1121	/* Apalis GPIO4 */
1122	pinctrl_gpio4: gpio4grp {
1123		fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13			0x06000021>;
1124	};
1125
1126	/* Apalis GPIO5 */
1127	pinctrl_gpio5: gpio5grp {
1128		fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01			0x06000021>;
1129	};
1130
1131	/* Apalis GPIO6 */
1132	pinctrl_gpio6: gpio6grp {
1133		fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02			0x00000021>;
1134	};
1135
1136	/* Apalis GPIO7 */
1137	pinctrl_gpio7: gpio7grp {
1138		fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26			0x00000021>;
1139	};
1140
1141	/* Apalis GPIO8 */
1142	pinctrl_gpio8: gpio8grp {
1143		fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28			0x00000021>;
1144	};
1145
1146	/* Apalis BKL1_ON */
1147	pinctrl_gpio_bkl_on: gpiobklongrp {
1148		fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04			0x00000021>;
1149	};
1150
1151	/* Apalis WAKE1_MICO */
1152	pinctrl_gpio_keys: gpiokeysgrp {
1153		fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20			0x06700021>;
1154	};
1155
1156	/* Apalis USBH_OC# */
1157	pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {
1158		fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06			0x04000021>;
1159	};
1160
1161	/* On-module HDMI_CTRL */
1162	pinctrl_hdmi_ctrl: hdmictrlgrp {
1163		fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0x00000061>;
1164	};
1165
1166	/* On-module I2C */
1167	pinctrl_lpi2c1: lpi2c1grp {
1168		fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL			0x04000020>,
1169			   <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA			0x04000020>;
1170	};
1171
1172	/* Apalis I2C1 */
1173	pinctrl_lpi2c2: lpi2c2grp {
1174		fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL			0x04000020>,
1175			   <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA			0x04000020>;
1176	};
1177
1178	/* Apalis I2C3 (CAM) */
1179	pinctrl_lpi2c3: lpi2c3grp {
1180		fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL				0x04000020>,
1181			   <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA			0x04000020>;
1182	};
1183
1184	/* Apalis SPI1 */
1185	pinctrl_lpspi0: lpspi0grp {
1186		fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK			0x0600004c>,
1187			   <IMX8QM_SPI0_SDO_DMA_SPI0_SDO			0x0600004c>,
1188			   <IMX8QM_SPI0_SDI_DMA_SPI0_SDI			0x0600004c>,
1189			   <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05			0x0600004c>;
1190	};
1191
1192	/* Apalis SPI2 */
1193	pinctrl_lpspi2: lpspi2grp {
1194		fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK			0x0600004c>,
1195			   <IMX8QM_SPI2_SDO_DMA_SPI2_SDO			0x0600004c>,
1196			   <IMX8QM_SPI2_SDI_DMA_SPI2_SDI			0x0600004c>,
1197			   <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10			0x0600004c>;
1198	};
1199
1200	/* Apalis UART3 */
1201	pinctrl_lpuart0: lpuart0grp {
1202		fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX			0x06000020>,
1203			   <IMX8QM_UART0_TX_DMA_UART0_TX			0x06000020>;
1204	};
1205
1206	/* Apalis UART1 */
1207	pinctrl_lpuart1: lpuart1grp {
1208		fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX			0x06000020>,
1209			   <IMX8QM_UART1_TX_DMA_UART1_TX			0x06000020>,
1210			   <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B			0x06000020>,
1211			   <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B			0x06000020>;
1212	};
1213
1214	/* Apalis UART1 */
1215	pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
1216		fsl,pins = /* Apalis UART1_DTR */
1217			   <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06			0x00000021>,
1218			   /* Apalis UART1_DSR */
1219			   <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07			0x00000021>,
1220			   /* Apalis UART1_DCD */
1221			   <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10			0x00000021>,
1222			   /* Apalis UART1_RI */
1223			   <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11			0x00000021>;
1224	};
1225
1226	/* Apalis UART4 */
1227	pinctrl_lpuart2: lpuart2grp {
1228		fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX			0x06000020>,
1229			   <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX			0x06000020>;
1230	};
1231
1232	/* Apalis UART2 */
1233	pinctrl_lpuart3: lpuart3grp {
1234		fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX			0x06000020>,
1235			   <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX			0x06000020>,
1236			   <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B		0x06000020>,
1237			   <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B		0x06000020>;
1238	};
1239
1240	/* Apalis TS_2 */
1241	pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {
1242		fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06		0x00000021>;
1243	};
1244
1245	/* Apalis LCD1_G6+7 */
1246	pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
1247		fsl,pins = /* Apalis LCD1_G6 */
1248			   <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12		0x00000021>,
1249			   /* Apalis LCD1_G7 */
1250			   <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x00000021>;
1251	};
1252
1253	/* Apalis TS_3 */
1254	pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {
1255		fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021>;
1256	};
1257
1258	/* Apalis TS_4 */
1259	pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
1260		fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22		0x00000021>;
1261	};
1262
1263	/* Apalis TS_1 */
1264	pinctrl_mlb_gpios: mlbgpiosgrp {
1265		fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27			0x00000021>;
1266	};
1267
1268	/* Apalis MMC1_CD# */
1269	pinctrl_mmc1_cd: mmc1cdgrp {
1270		fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000021>;
1271	};
1272
1273	pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {
1274		fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x04000021>;
1275	};
1276
1277	/* On-module PCIe_Wi-Fi */
1278	pinctrl_pcieb: pciebgrp {
1279		fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30		0x00000021>,
1280			   <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x00000021>,
1281			   <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x00000021>;
1282	};
1283
1284	/* On-module PCIe_CLK_EN1 */
1285	pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
1286		fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11			0x00000021>;
1287	};
1288
1289	/* On-module PCIe_CLK_EN2 */
1290	pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {
1291		fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11		0x00000021>;
1292	};
1293
1294	/* Apalis PWM3 */
1295	pinctrl_pwm0: pwm0grp {
1296		fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT			0x00000020>;
1297	};
1298
1299	/* Apalis PWM4 */
1300	pinctrl_pwm1: pwm1grp {
1301		fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT			0x00000020>;
1302	};
1303
1304	/* Apalis PWM1 */
1305	pinctrl_pwm2: pwm2grp {
1306		fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT			0x00000020>;
1307	};
1308
1309	/* Apalis PWM2 */
1310	pinctrl_pwm3: pwm3grp {
1311		fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT			0x00000020>;
1312	};
1313
1314	/* Apalis BKL1_PWM */
1315	pinctrl_pwm_bkl: pwmbklgrp {
1316		fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT			0x00000020>;
1317	};
1318
1319	/* Apalis LCD1_ */
1320	pinctrl_qspi1a_gpios: qspi1agpiosgrp {
1321		fsl,pins = /* Apalis LCD1_B0 */
1322			   <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26			0x00000021>,
1323			   /* Apalis LCD1_B1 */
1324			   <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25			0x00000021>,
1325			   /* Apalis LCD1_B2 */
1326			   <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24			0x00000021>,
1327			   /* Apalis LCD1_B3 */
1328			   <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23			0x00000021>,
1329			   /* Apalis LCD1_B5 */
1330			   <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22			0x00000021>,
1331			   /* Apalis LCD1_B7 */
1332			   <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21			0x00000021>,
1333			   /* Apalis LCD1_B4 */
1334			   <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19			0x00000021>,
1335			   /* Apalis LCD1_B6 */
1336			   <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20			0x00000021>;
1337	};
1338
1339	/* On-module RESET_MOCI#_DRV */
1340	pinctrl_reset_moci: resetmocigrp {
1341		fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30			0x00000021>;
1342	};
1343
1344	/* On-module I2S SGTL5000 for Apalis Analogue Audio */
1345	pinctrl_sai1: sai1grp {
1346		fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD			0xc600006c>,
1347			   <IMX8QM_SAI1_RXD_AUD_SAI1_RXD			0xc600004c>,
1348			   <IMX8QM_SAI1_TXC_AUD_SAI1_TXC			0xc600004c>,
1349			   <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS			0xc600004c>;
1350	};
1351
1352	/* Apalis SATA1_ACT# */
1353	pinctrl_sata1_act: sata1actgrp {
1354		fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000021>;
1355	};
1356
1357	/* Apalis SD1_CD# */
1358	pinctrl_sd1_cd: sd1cdgrp {
1359		fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12			0x00000021>;
1360	};
1361
1362	/* On-module I2S SGTL5000 SYS_MCLK */
1363	pinctrl_sgtl5000: sgtl5000grp {
1364		fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0xc600004c>;
1365	};
1366
1367	/* Apalis LCD1_ */
1368	pinctrl_sim0_gpios: sim0gpiosgrp {
1369		fsl,pins = /* Apalis LCD1_G5 */
1370			   <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00			0x00000021>,
1371			   /* Apalis LCD1_G3 */
1372			   <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05		0x00000021>,
1373			   /* Apalis TS_5 */
1374			   <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02			0x00000021>,
1375			   /* Apalis LCD1_G4 */
1376			   <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01			0x00000021>;
1377	};
1378
1379	/* Apalis SPDIF */
1380	pinctrl_spdif0: spdif0grp {
1381		fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX			0xc6000040>,
1382			   <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX			0xc6000040>;
1383	};
1384
1385	pinctrl_touchctrl_gpios: touchctrlgpiosgrp {
1386		fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04			0x00000021>,
1387			   <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05			0x00000041>,
1388			   <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17			0x00000021>,
1389			   <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21			0x00000041>;
1390	};
1391
1392	pinctrl_touchctrl_idle: touchctrlidlegrp {
1393		fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22			0x00000021>,
1394			   <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23			0x00000021>,
1395			   <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24			0x00000021>,
1396			   <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25			0x00000021>;
1397	};
1398
1399	/* On-module USB HSIC HUB (active) */
1400	pinctrl_usb_hsic_active: usbh1activegrp {
1401		fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0x000000cf>,
1402			   <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0x000000ff>;
1403	};
1404
1405	/* On-module USB HSIC HUB (idle) */
1406	pinctrl_usb_hsic_idle: usbh1idlegrp {
1407		fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0x000000cf>,
1408			   <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0x000000cf>;
1409	};
1410
1411	/* On-module USB HSIC HUB */
1412	pinctrl_usb3503a: usb3503agrp {
1413		fsl,pins = /* On-module HSIC_HUB_CONNECT */
1414			   <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x00000041>,
1415			   /* On-module HSIC_INT_N */
1416			   <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01			0x00000021>,
1417			   /* On-module HSIC_RESET_N */
1418			   <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02			0x00000041>;
1419	};
1420
1421	/* Apalis USBH_EN */
1422	pinctrl_usbh_en: usbhengrp {
1423		fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04			0x00000021>;
1424	};
1425
1426	/* Apalis USBO1 */
1427	pinctrl_usbotg1: usbotg1grp {
1428		fsl,pins = /* Apalis USBO1_EN */
1429			   <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021>,
1430			   /* Apalis USBO1_OC# */
1431			   <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC			0x04000021>;
1432	};
1433
1434	/* On-module eMMC */
1435	pinctrl_usdhc1: usdhc1grp {
1436		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
1437			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021>,
1438			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021>,
1439			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021>,
1440			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021>,
1441			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021>,
1442			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021>,
1443			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021>,
1444			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021>,
1445			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021>,
1446			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000041>,
1447			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000021>;
1448	};
1449
1450	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1451		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040>,
1452			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020>,
1453			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000020>,
1454			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000020>,
1455			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000020>,
1456			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000020>,
1457			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000020>,
1458			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000020>,
1459			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000020>,
1460			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000020>,
1461			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040>,
1462			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020>;
1463	};
1464
1465	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1466		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040>,
1467			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020>,
1468			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000020>,
1469			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000020>,
1470			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000020>,
1471			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000020>,
1472			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000020>,
1473			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000020>,
1474			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000020>,
1475			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000020>,
1476			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040>,
1477			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020>;
1478	};
1479
1480	/* Apalis TS_6 */
1481	pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
1482		fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23		0x00000021>;
1483	};
1484
1485	/* Apalis MMC1 */
1486	pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {
1487		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,
1488			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021>,
1489			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000021>,
1490			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000021>,
1491			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000021>,
1492			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000021>,
1493			   /* On-module PMIC use */
1494			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1495	};
1496
1497	pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {
1498		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000040>,
1499			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000020>,
1500			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020>,
1501			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020>,
1502			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020>,
1503			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020>,
1504			   /* On-module PMIC use */
1505			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1506	};
1507
1508	pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {
1509		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000040>,
1510			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000020>,
1511			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020>,
1512			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020>,
1513			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020>,
1514			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020>,
1515			   /* On-module PMIC use */
1516			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1517	};
1518
1519	pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {
1520		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000021>,
1521			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000021>,
1522			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000021>,
1523			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000021>;
1524	};
1525
1526	pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {
1527		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000020>,
1528			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000020>,
1529			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000020>,
1530			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000020>;
1531	};
1532
1533	pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {
1534		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000020>,
1535			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000020>,
1536			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000020>,
1537			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000020>;
1538	};
1539
1540	pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {
1541		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x04000061>,
1542			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x04000061>,
1543			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x04000061>,
1544			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x04000061>,
1545			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x04000061>,
1546			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x04000061>,
1547			   /* On-module PMIC use */
1548			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1549	};
1550
1551	pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {
1552		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x04000061>,
1553			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x04000061>,
1554			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x04000061>,
1555			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x04000061>;
1556	};
1557
1558	/* Apalis SD1 */
1559	pinctrl_usdhc3: usdhc3grp {
1560		fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041>,
1561			   <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021>,
1562			   <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021>,
1563			   <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021>,
1564			   <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021>,
1565			   <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021>,
1566			   /* On-module PMIC use */
1567			   <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021>;
1568	};
1569
1570	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1571		fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041>,
1572			   <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021>,
1573			   <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021>,
1574			   <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021>,
1575			   <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021>,
1576			   <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021>,
1577			   /* On-module PMIC use */
1578			   <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021>;
1579	};
1580
1581	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1582		fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041>,
1583			   <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021>,
1584			   <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021>,
1585			   <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021>,
1586			   <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021>,
1587			   <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021>,
1588			   /* On-module PMIC use */
1589			   <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021>;
1590	};
1591
1592	/* On-module Wi-Fi */
1593	pinctrl_wifi: wifigrp {
1594		fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */
1595			   <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x06000021>,
1596			   /* On-module Wi-Fi_PCIE_W_DISABLE */
1597			   <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24		0x06000021>;
1598	};
1599
1600	pinctrl_wifi_pdn: wifipdngrp {
1601		fsl,pins = /* On-module Wi-Fi_POWER_DOWN */
1602			   <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0x06000021>;
1603	};
1604};
1605