1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "google,gs101"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_gpio_alive; 23 pinctrl1 = &pinctrl_far_alive; 24 pinctrl2 = &pinctrl_gsacore; 25 pinctrl3 = &pinctrl_gsactrl; 26 pinctrl4 = &pinctrl_peric0; 27 pinctrl5 = &pinctrl_peric1; 28 pinctrl6 = &pinctrl_hsi1; 29 pinctrl7 = &pinctrl_hsi2; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&cpu0>; 40 }; 41 core1 { 42 cpu = <&cpu1>; 43 }; 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 core3 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu4>; 55 }; 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 core1 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0000>; 75 enable-method = "psci"; 76 cpu-idle-states = <&ananke_cpu_sleep>; 77 capacity-dmips-mhz = <250>; 78 dynamic-power-coefficient = <70>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x0100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&ananke_cpu_sleep>; 87 capacity-dmips-mhz = <250>; 88 dynamic-power-coefficient = <70>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0200>; 95 enable-method = "psci"; 96 cpu-idle-states = <&ananke_cpu_sleep>; 97 capacity-dmips-mhz = <250>; 98 dynamic-power-coefficient = <70>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0300>; 105 enable-method = "psci"; 106 cpu-idle-states = <&ananke_cpu_sleep>; 107 capacity-dmips-mhz = <250>; 108 dynamic-power-coefficient = <70>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a76"; 114 reg = <0x0400>; 115 enable-method = "psci"; 116 cpu-idle-states = <&enyo_cpu_sleep>; 117 capacity-dmips-mhz = <620>; 118 dynamic-power-coefficient = <284>; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a76"; 124 reg = <0x0500>; 125 enable-method = "psci"; 126 cpu-idle-states = <&enyo_cpu_sleep>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 }; 130 131 cpu6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-x1"; 134 reg = <0x0600>; 135 enable-method = "psci"; 136 cpu-idle-states = <&hera_cpu_sleep>; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <650>; 139 }; 140 141 cpu7: cpu@700 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-x1"; 144 reg = <0x0700>; 145 enable-method = "psci"; 146 cpu-idle-states = <&hera_cpu_sleep>; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <650>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 ananke_cpu_sleep: cpu-ananke-sleep { 155 idle-state-name = "c2"; 156 compatible = "arm,idle-state"; 157 arm,psci-suspend-param = <0x0010000>; 158 entry-latency-us = <70>; 159 exit-latency-us = <160>; 160 min-residency-us = <2000>; 161 }; 162 163 enyo_cpu_sleep: cpu-enyo-sleep { 164 idle-state-name = "c2"; 165 compatible = "arm,idle-state"; 166 arm,psci-suspend-param = <0x0010000>; 167 entry-latency-us = <150>; 168 exit-latency-us = <190>; 169 min-residency-us = <2500>; 170 }; 171 172 hera_cpu_sleep: cpu-hera-sleep { 173 idle-state-name = "c2"; 174 compatible = "arm,idle-state"; 175 arm,psci-suspend-param = <0x0010000>; 176 entry-latency-us = <235>; 177 exit-latency-us = <220>; 178 min-residency-us = <3500>; 179 }; 180 }; 181 }; 182 183 /* ect node is required to be present by bootloader */ 184 ect { 185 }; 186 187 ext_24_5m: clock-1 { 188 compatible = "fixed-clock"; 189 #clock-cells = <0>; 190 clock-output-names = "oscclk"; 191 }; 192 193 ext_200m: clock-2 { 194 compatible = "fixed-clock"; 195 #clock-cells = <0>; 196 clock-output-names = "ext-200m"; 197 }; 198 199 firmware { 200 acpm_ipc: power-management { 201 compatible = "google,gs101-acpm-ipc"; 202 mboxes = <&ap2apm_mailbox>; 203 shmem = <&apm_sram>; 204 }; 205 }; 206 207 pmu-0 { 208 compatible = "arm,cortex-a55-pmu"; 209 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 210 }; 211 212 pmu-1 { 213 compatible = "arm,cortex-a76-pmu"; 214 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 215 }; 216 217 pmu-2 { 218 compatible = "arm,cortex-x1-pmu"; 219 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 220 }; 221 222 pmu-3 { 223 compatible = "arm,dsu-pmu"; 224 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 225 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 226 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 227 }; 228 229 psci { 230 compatible = "arm,psci-1.0"; 231 method = "smc"; 232 }; 233 234 reserved_memory: reserved-memory { 235 #address-cells = <2>; 236 #size-cells = <1>; 237 ranges; 238 239 gsa_reserved_protected: gsa@90200000 { 240 reg = <0x0 0x90200000 0x400000>; 241 no-map; 242 }; 243 244 tpu_fw_reserved: tpu-fw@93000000 { 245 reg = <0x0 0x93000000 0x1000000>; 246 no-map; 247 }; 248 249 aoc_reserve: aoc@94000000 { 250 reg = <0x0 0x94000000 0x03000000>; 251 no-map; 252 }; 253 254 abl_reserved: abl@f8800000 { 255 reg = <0x0 0xf8800000 0x02000000>; 256 no-map; 257 }; 258 259 dss_log_reserved: dss-log-reserved@fd3f0000 { 260 reg = <0x0 0xfd3f0000 0x0000e000>; 261 no-map; 262 }; 263 264 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 265 reg = <0x0 0xfd3fe000 0x00001000>; 266 no-map; 267 }; 268 269 bldr_log_reserved: bldr-log-reserved@fd800000 { 270 reg = <0x0 0xfd800000 0x00100000>; 271 no-map; 272 }; 273 274 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 275 reg = <0x0 0xfd900000 0x00002000>; 276 no-map; 277 }; 278 }; 279 280 soc: soc@0 { 281 compatible = "simple-bus"; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 ranges = <0x0 0x0 0x0 0x40000000>; 285 286 cmu_misc: clock-controller@10010000 { 287 compatible = "google,gs101-cmu-misc"; 288 reg = <0x10010000 0x8000>; 289 #clock-cells = <1>; 290 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 291 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 292 clock-names = "bus", "sss"; 293 }; 294 295 timer@10050000 { 296 compatible = "google,gs101-mct", 297 "samsung,exynos4210-mct"; 298 reg = <0x10050000 0x800>; 299 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 300 clock-names = "fin_pll", "mct"; 301 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 302 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 303 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 304 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 305 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 306 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 307 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 308 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 309 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 310 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 311 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 312 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 313 }; 314 315 watchdog_cl0: watchdog@10060000 { 316 compatible = "google,gs101-wdt"; 317 reg = <0x10060000 0x100>; 318 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 319 <&ext_24_5m>; 320 clock-names = "watchdog", "watchdog_src"; 321 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 322 samsung,syscon-phandle = <&pmu_system_controller>; 323 samsung,cluster-index = <0>; 324 status = "disabled"; 325 }; 326 327 watchdog_cl1: watchdog@10070000 { 328 compatible = "google,gs101-wdt"; 329 reg = <0x10070000 0x100>; 330 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 331 <&ext_24_5m>; 332 clock-names = "watchdog", "watchdog_src"; 333 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 334 samsung,syscon-phandle = <&pmu_system_controller>; 335 samsung,cluster-index = <1>; 336 status = "disabled"; 337 }; 338 339 gic: interrupt-controller@10400000 { 340 compatible = "arm,gic-v3"; 341 #interrupt-cells = <4>; 342 interrupt-controller; 343 reg = <0x10400000 0x10000>, /* GICD */ 344 <0x10440000 0x100000>;/* GICR * 8 */ 345 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 346 347 ppi-partitions { 348 ppi_cluster0: interrupt-partition-0 { 349 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 350 }; 351 352 ppi_cluster1: interrupt-partition-1 { 353 affinity = <&cpu4 &cpu5>; 354 }; 355 356 ppi_cluster2: interrupt-partition-2 { 357 affinity = <&cpu6 &cpu7>; 358 }; 359 }; 360 }; 361 362 cmu_peric0: clock-controller@10800000 { 363 compatible = "google,gs101-cmu-peric0"; 364 reg = <0x10800000 0x4000>; 365 #clock-cells = <1>; 366 clocks = <&ext_24_5m>, 367 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 368 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 369 clock-names = "oscclk", "bus", "ip"; 370 }; 371 372 sysreg_peric0: syscon@10820000 { 373 compatible = "google,gs101-peric0-sysreg", "syscon"; 374 reg = <0x10820000 0x10000>; 375 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 376 }; 377 378 pinctrl_peric0: pinctrl@10840000 { 379 compatible = "google,gs101-pinctrl"; 380 reg = <0x10840000 0x00001000>; 381 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; 382 clock-names = "pclk"; 383 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 384 }; 385 386 usi1: usi@109000c0 { 387 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 388 reg = <0x109000c0 0x20>; 389 ranges; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 393 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 394 clock-names = "pclk", "ipclk"; 395 samsung,sysreg = <&sysreg_peric0 0x1000>; 396 status = "disabled"; 397 398 hsi2c_1: i2c@10900000 { 399 compatible = "google,gs101-hsi2c", 400 "samsung,exynosautov9-hsi2c"; 401 reg = <0x10900000 0xc0>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, 405 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; 406 clock-names = "hsi2c", "hsi2c_pclk"; 407 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 408 pinctrl-0 = <&hsi2c1_bus>; 409 pinctrl-names = "default"; 410 status = "disabled"; 411 }; 412 413 serial_1: serial@10900000 { 414 compatible = "google,gs101-uart"; 415 reg = <0x10900000 0xc0>; 416 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 417 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 418 clock-names = "uart", "clk_uart_baud0"; 419 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 420 pinctrl-0 = <&uart1_bus_single>; 421 pinctrl-names = "default"; 422 samsung,uart-fifosize = <64>; 423 status = "disabled"; 424 }; 425 426 spi_1: spi@10900000 { 427 compatible = "google,gs101-spi"; 428 reg = <0x10900000 0x30>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 432 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 433 clock-names = "spi", "spi_busclk0"; 434 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 435 pinctrl-0 = <&spi1_bus>; 436 pinctrl-names = "default"; 437 status = "disabled"; 438 }; 439 }; 440 441 usi2: usi@109100c0 { 442 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 443 reg = <0x109100c0 0x20>; 444 ranges; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 448 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 449 clock-names = "pclk", "ipclk"; 450 samsung,sysreg = <&sysreg_peric0 0x1004>; 451 status = "disabled"; 452 453 hsi2c_2: i2c@10910000 { 454 compatible = "google,gs101-hsi2c", 455 "samsung,exynosautov9-hsi2c"; 456 reg = <0x10910000 0xc0>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, 460 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; 461 clock-names = "hsi2c", "hsi2c_pclk"; 462 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 463 pinctrl-0 = <&hsi2c2_bus>; 464 pinctrl-names = "default"; 465 status = "disabled"; 466 }; 467 468 serial_2: serial@10910000 { 469 compatible = "google,gs101-uart"; 470 reg = <0x10910000 0xc0>; 471 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 472 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 473 clock-names = "uart", "clk_uart_baud0"; 474 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 475 pinctrl-0 = <&uart2_bus_single>; 476 pinctrl-names = "default"; 477 samsung,uart-fifosize = <64>; 478 status = "disabled"; 479 }; 480 481 spi_2: spi@10910000 { 482 compatible = "google,gs101-spi"; 483 reg = <0x10910000 0x30>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 487 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 488 clock-names = "spi", "spi_busclk0"; 489 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 490 pinctrl-0 = <&spi2_bus>; 491 pinctrl-names = "default"; 492 status = "disabled"; 493 }; 494 }; 495 496 usi3: usi@109200c0 { 497 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 498 reg = <0x109200c0 0x20>; 499 ranges; 500 #address-cells = <1>; 501 #size-cells = <1>; 502 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 503 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 504 clock-names = "pclk", "ipclk"; 505 samsung,sysreg = <&sysreg_peric0 0x1008>; 506 status = "disabled"; 507 508 hsi2c_3: i2c@10920000 { 509 compatible = "google,gs101-hsi2c", 510 "samsung,exynosautov9-hsi2c"; 511 reg = <0x10920000 0xc0>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, 515 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; 516 clock-names = "hsi2c", "hsi2c_pclk"; 517 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 518 pinctrl-0 = <&hsi2c3_bus>; 519 pinctrl-names = "default"; 520 status = "disabled"; 521 }; 522 523 serial_3: serial@10920000 { 524 compatible = "google,gs101-uart"; 525 reg = <0x10920000 0xc0>; 526 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 527 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 528 clock-names = "uart", "clk_uart_baud0"; 529 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 530 pinctrl-0 = <&uart3_bus_single>; 531 pinctrl-names = "default"; 532 samsung,uart-fifosize = <64>; 533 status = "disabled"; 534 }; 535 536 spi_3: spi@10920000 { 537 compatible = "google,gs101-spi"; 538 reg = <0x10920000 0x30>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 542 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 543 clock-names = "spi", "spi_busclk0"; 544 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 545 pinctrl-0 = <&spi3_bus>; 546 pinctrl-names = "default"; 547 status = "disabled"; 548 }; 549 }; 550 551 usi4: usi@109300c0 { 552 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 553 reg = <0x109300c0 0x20>; 554 ranges; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 558 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 559 clock-names = "pclk", "ipclk"; 560 samsung,sysreg = <&sysreg_peric0 0x100c>; 561 status = "disabled"; 562 563 hsi2c_4: i2c@10930000 { 564 compatible = "google,gs101-hsi2c", 565 "samsung,exynosautov9-hsi2c"; 566 reg = <0x10930000 0xc0>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, 570 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; 571 clock-names = "hsi2c", "hsi2c_pclk"; 572 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 573 pinctrl-0 = <&hsi2c4_bus>; 574 pinctrl-names = "default"; 575 status = "disabled"; 576 }; 577 578 serial_4: serial@10930000 { 579 compatible = "google,gs101-uart"; 580 reg = <0x10930000 0xc0>; 581 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 582 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 583 clock-names = "uart", "clk_uart_baud0"; 584 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 585 pinctrl-0 = <&uart4_bus_single>; 586 pinctrl-names = "default"; 587 samsung,uart-fifosize = <64>; 588 status = "disabled"; 589 }; 590 591 spi_4: spi@10930000 { 592 compatible = "google,gs101-spi"; 593 reg = <0x10930000 0x30>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 597 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 598 clock-names = "spi", "spi_busclk0"; 599 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 600 pinctrl-0 = <&spi4_bus>; 601 pinctrl-names = "default"; 602 status = "disabled"; 603 }; 604 }; 605 606 usi5: usi@109400c0 { 607 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 608 reg = <0x109400c0 0x20>; 609 ranges; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 613 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 614 clock-names = "pclk", "ipclk"; 615 samsung,sysreg = <&sysreg_peric0 0x1010>; 616 status = "disabled"; 617 618 hsi2c_5: i2c@10940000 { 619 compatible = "google,gs101-hsi2c", 620 "samsung,exynosautov9-hsi2c"; 621 reg = <0x10940000 0xc0>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, 625 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; 626 clock-names = "hsi2c", "hsi2c_pclk"; 627 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 628 pinctrl-0 = <&hsi2c5_bus>; 629 pinctrl-names = "default"; 630 status = "disabled"; 631 }; 632 633 serial_5: serial@10940000 { 634 compatible = "google,gs101-uart"; 635 reg = <0x10940000 0xc0>; 636 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 637 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 638 clock-names = "uart", "clk_uart_baud0"; 639 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 640 pinctrl-0 = <&uart5_bus_single>; 641 pinctrl-names = "default"; 642 samsung,uart-fifosize = <64>; 643 status = "disabled"; 644 }; 645 646 spi_5: spi@10940000 { 647 compatible = "google,gs101-spi"; 648 reg = <0x10940000 0x30>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 652 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 653 clock-names = "spi", "spi_busclk0"; 654 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 655 pinctrl-0 = <&spi5_bus>; 656 pinctrl-names = "default"; 657 status = "disabled"; 658 }; 659 }; 660 661 usi6: usi@109500c0 { 662 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 663 reg = <0x109500c0 0x20>; 664 ranges; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 668 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 669 clock-names = "pclk", "ipclk"; 670 samsung,sysreg = <&sysreg_peric0 0x1014>; 671 status = "disabled"; 672 673 hsi2c_6: i2c@10950000 { 674 compatible = "google,gs101-hsi2c", 675 "samsung,exynosautov9-hsi2c"; 676 reg = <0x10950000 0xc0>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, 680 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; 681 clock-names = "hsi2c", "hsi2c_pclk"; 682 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 683 pinctrl-0 = <&hsi2c6_bus>; 684 pinctrl-names = "default"; 685 status = "disabled"; 686 }; 687 688 serial_6: serial@10950000 { 689 compatible = "google,gs101-uart"; 690 reg = <0x10950000 0xc0>; 691 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 692 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 693 clock-names = "uart", "clk_uart_baud0"; 694 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 695 pinctrl-0 = <&uart6_bus_single>; 696 pinctrl-names = "default"; 697 samsung,uart-fifosize = <64>; 698 status = "disabled"; 699 }; 700 701 spi_6: spi@10950000 { 702 compatible = "google,gs101-spi"; 703 reg = <0x10950000 0x30>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 707 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 708 clock-names = "spi", "spi_busclk0"; 709 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 710 pinctrl-0 = <&spi6_bus>; 711 pinctrl-names = "default"; 712 status = "disabled"; 713 }; 714 }; 715 716 usi7: usi@109600c0 { 717 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 718 reg = <0x109600c0 0x20>; 719 ranges; 720 #address-cells = <1>; 721 #size-cells = <1>; 722 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 723 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 724 clock-names = "pclk", "ipclk"; 725 samsung,sysreg = <&sysreg_peric0 0x1018>; 726 status = "disabled"; 727 728 hsi2c_7: i2c@10960000 { 729 compatible = "google,gs101-hsi2c", 730 "samsung,exynosautov9-hsi2c"; 731 reg = <0x10960000 0xc0>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, 735 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; 736 clock-names = "hsi2c", "hsi2c_pclk"; 737 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 738 pinctrl-0 = <&hsi2c7_bus>; 739 pinctrl-names = "default"; 740 status = "disabled"; 741 }; 742 743 serial_7: serial@10960000 { 744 compatible = "google,gs101-uart"; 745 reg = <0x10960000 0xc0>; 746 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 747 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 748 clock-names = "uart", "clk_uart_baud0"; 749 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 750 pinctrl-0 = <&uart7_bus_single>; 751 pinctrl-names = "default"; 752 samsung,uart-fifosize = <64>; 753 status = "disabled"; 754 }; 755 756 spi_7: spi@10960000 { 757 compatible = "google,gs101-spi"; 758 reg = <0x10960000 0x30>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 762 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 763 clock-names = "spi", "spi_busclk0"; 764 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 765 pinctrl-0 = <&spi7_bus>; 766 pinctrl-names = "default"; 767 status = "disabled"; 768 }; 769 }; 770 771 usi8: usi@109700c0 { 772 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 773 reg = <0x109700c0 0x20>; 774 ranges; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 778 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 779 clock-names = "pclk", "ipclk"; 780 samsung,sysreg = <&sysreg_peric0 0x101c>; 781 status = "disabled"; 782 783 hsi2c_8: i2c@10970000 { 784 compatible = "google,gs101-hsi2c", 785 "samsung,exynosautov9-hsi2c"; 786 reg = <0x10970000 0xc0>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 790 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 791 clock-names = "hsi2c", "hsi2c_pclk"; 792 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 793 pinctrl-0 = <&hsi2c8_bus>; 794 pinctrl-names = "default"; 795 status = "disabled"; 796 }; 797 798 serial_8: serial@10970000 { 799 compatible = "google,gs101-uart"; 800 reg = <0x10970000 0xc0>; 801 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 802 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 803 clock-names = "uart", "clk_uart_baud0"; 804 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 805 pinctrl-0 = <&uart8_bus_single>; 806 pinctrl-names = "default"; 807 samsung,uart-fifosize = <64>; 808 status = "disabled"; 809 }; 810 811 spi_8: spi@10970000 { 812 compatible = "google,gs101-spi"; 813 reg = <0x10970000 0x30>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 817 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 818 clock-names = "spi", "spi_busclk0"; 819 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 820 pinctrl-0 = <&spi8_bus>; 821 pinctrl-names = "default"; 822 status = "disabled"; 823 }; 824 }; 825 826 usi_uart: usi@10a000c0 { 827 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 828 reg = <0x10a000c0 0x20>; 829 ranges; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 833 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 834 clock-names = "pclk", "ipclk"; 835 samsung,sysreg = <&sysreg_peric0 0x1020>; 836 samsung,mode = <USI_V2_UART>; 837 status = "disabled"; 838 839 serial_0: serial@10a00000 { 840 compatible = "google,gs101-uart"; 841 reg = <0x10a00000 0xc0>; 842 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 843 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 844 clock-names = "uart", "clk_uart_baud0"; 845 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 846 pinctrl-0 = <&uart0_bus>; 847 pinctrl-names = "default"; 848 samsung,uart-fifosize = <256>; 849 status = "disabled"; 850 }; 851 }; 852 853 usi14: usi@10a200c0 { 854 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 855 reg = <0x10a200c0 0x20>; 856 ranges; 857 #address-cells = <1>; 858 #size-cells = <1>; 859 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 860 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 861 clock-names = "pclk", "ipclk"; 862 samsung,sysreg = <&sysreg_peric0 0x1028>; 863 status = "disabled"; 864 865 hsi2c_14: i2c@10a20000 { 866 compatible = "google,gs101-hsi2c", 867 "samsung,exynosautov9-hsi2c"; 868 reg = <0x10a20000 0xc0>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, 872 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; 873 clock-names = "hsi2c", "hsi2c_pclk"; 874 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 875 pinctrl-0 = <&hsi2c14_bus>; 876 pinctrl-names = "default"; 877 status = "disabled"; 878 }; 879 880 serial_14: serial@10a20000 { 881 compatible = "google,gs101-uart"; 882 reg = <0x10a20000 0xc0>; 883 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 884 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 885 clock-names = "uart", "clk_uart_baud0"; 886 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 887 pinctrl-0 = <&uart14_bus_single>; 888 pinctrl-names = "default"; 889 samsung,uart-fifosize = <64>; 890 status = "disabled"; 891 }; 892 893 spi_14: spi@10a20000 { 894 compatible = "google,gs101-spi"; 895 reg = <0x10a20000 0x30>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 899 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 900 clock-names = "spi", "spi_busclk0"; 901 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 902 pinctrl-0 = <&spi14_bus>; 903 pinctrl-names = "default"; 904 status = "disabled"; 905 }; 906 }; 907 908 cmu_peric1: clock-controller@10c00000 { 909 compatible = "google,gs101-cmu-peric1"; 910 reg = <0x10c00000 0x4000>; 911 #clock-cells = <1>; 912 clocks = <&ext_24_5m>, 913 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 914 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 915 clock-names = "oscclk", "bus", "ip"; 916 }; 917 918 sysreg_peric1: syscon@10c20000 { 919 compatible = "google,gs101-peric1-sysreg", "syscon"; 920 reg = <0x10c20000 0x10000>; 921 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 922 }; 923 924 pinctrl_peric1: pinctrl@10c40000 { 925 compatible = "google,gs101-pinctrl"; 926 reg = <0x10c40000 0x00001000>; 927 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; 928 clock-names = "pclk"; 929 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 930 }; 931 932 usi0: usi@10d100c0 { 933 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 934 reg = <0x10d100c0 0x20>; 935 ranges; 936 #address-cells = <1>; 937 #size-cells = <1>; 938 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 939 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 940 clock-names = "pclk", "ipclk"; 941 samsung,sysreg = <&sysreg_peric1 0x1000>; 942 status = "disabled"; 943 944 hsi2c_0: i2c@10d10000 { 945 compatible = "google,gs101-hsi2c", 946 "samsung,exynosautov9-hsi2c"; 947 reg = <0x10d10000 0xc0>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, 951 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; 952 clock-names = "hsi2c", "hsi2c_pclk"; 953 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 954 pinctrl-0 = <&hsi2c0_bus>; 955 pinctrl-names = "default"; 956 status = "disabled"; 957 }; 958 959 serial_usi0: serial@10d10000 { 960 compatible = "google,gs101-uart"; 961 reg = <0x10d10000 0xc0>; 962 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 963 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 964 clock-names = "uart", "clk_uart_baud0"; 965 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 966 pinctrl-0 = <&uart0_bus_single>; 967 pinctrl-names = "default"; 968 samsung,uart-fifosize = <64>; 969 status = "disabled"; 970 }; 971 972 spi_0: spi@10d10000 { 973 compatible = "google,gs101-spi"; 974 reg = <0x10d10000 0x30>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 978 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 979 clock-names = "spi", "spi_busclk0"; 980 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 981 pinctrl-0 = <&spi0_bus>; 982 pinctrl-names = "default"; 983 status = "disabled"; 984 }; 985 }; 986 987 usi9: usi@10d200c0 { 988 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 989 reg = <0x10d200c0 0x20>; 990 ranges; 991 #address-cells = <1>; 992 #size-cells = <1>; 993 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 994 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 995 clock-names = "pclk", "ipclk"; 996 samsung,sysreg = <&sysreg_peric1 0x1004>; 997 status = "disabled"; 998 999 hsi2c_9: i2c@10d20000 { 1000 compatible = "google,gs101-hsi2c", 1001 "samsung,exynosautov9-hsi2c"; 1002 reg = <0x10d20000 0xc0>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, 1006 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; 1007 clock-names = "hsi2c", "hsi2c_pclk"; 1008 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1009 pinctrl-0 = <&hsi2c9_bus>; 1010 pinctrl-names = "default"; 1011 status = "disabled"; 1012 }; 1013 1014 serial_9: serial@10d20000 { 1015 compatible = "google,gs101-uart"; 1016 reg = <0x10d20000 0xc0>; 1017 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1018 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1019 clock-names = "uart", "clk_uart_baud0"; 1020 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1021 pinctrl-0 = <&uart9_bus_single>; 1022 pinctrl-names = "default"; 1023 samsung,uart-fifosize = <64>; 1024 status = "disabled"; 1025 }; 1026 1027 spi_9: spi@10d20000 { 1028 compatible = "google,gs101-spi"; 1029 reg = <0x10d20000 0x30>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1033 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1034 clock-names = "spi", "spi_busclk0"; 1035 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1036 pinctrl-0 = <&spi9_bus>; 1037 pinctrl-names = "default"; 1038 status = "disabled"; 1039 }; 1040 }; 1041 1042 usi10: usi@10d300c0 { 1043 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1044 reg = <0x10d300c0 0x20>; 1045 ranges; 1046 #address-cells = <1>; 1047 #size-cells = <1>; 1048 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1049 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1050 clock-names = "pclk", "ipclk"; 1051 samsung,sysreg = <&sysreg_peric1 0x1008>; 1052 status = "disabled"; 1053 1054 hsi2c_10: i2c@10d30000 { 1055 compatible = "google,gs101-hsi2c", 1056 "samsung,exynosautov9-hsi2c"; 1057 reg = <0x10d30000 0xc0>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, 1061 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; 1062 clock-names = "hsi2c", "hsi2c_pclk"; 1063 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1064 pinctrl-0 = <&hsi2c10_bus>; 1065 pinctrl-names = "default"; 1066 status = "disabled"; 1067 }; 1068 1069 serial_10: serial@10d30000 { 1070 compatible = "google,gs101-uart"; 1071 reg = <0x10d30000 0xc0>; 1072 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1073 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1074 clock-names = "uart", "clk_uart_baud0"; 1075 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1076 pinctrl-0 = <&uart10_bus_single>; 1077 pinctrl-names = "default"; 1078 samsung,uart-fifosize = <64>; 1079 status = "disabled"; 1080 }; 1081 1082 spi_10: spi@10d30000 { 1083 compatible = "google,gs101-spi"; 1084 reg = <0x10d30000 0x30>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1088 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1089 clock-names = "spi", "spi_busclk0"; 1090 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1091 pinctrl-0 = <&spi10_bus>; 1092 pinctrl-names = "default"; 1093 status = "disabled"; 1094 }; 1095 }; 1096 1097 usi11: usi@10d400c0 { 1098 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1099 reg = <0x10d400c0 0x20>; 1100 ranges; 1101 #address-cells = <1>; 1102 #size-cells = <1>; 1103 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1104 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1105 clock-names = "pclk", "ipclk"; 1106 samsung,sysreg = <&sysreg_peric1 0x100c>; 1107 status = "disabled"; 1108 1109 hsi2c_11: i2c@10d40000 { 1110 compatible = "google,gs101-hsi2c", 1111 "samsung,exynosautov9-hsi2c"; 1112 reg = <0x10d40000 0xc0>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, 1116 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; 1117 clock-names = "hsi2c", "hsi2c_pclk"; 1118 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1119 pinctrl-0 = <&hsi2c11_bus>; 1120 pinctrl-names = "default"; 1121 status = "disabled"; 1122 }; 1123 1124 serial_11: serial@10d40000 { 1125 compatible = "google,gs101-uart"; 1126 reg = <0x10d40000 0xc0>; 1127 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1128 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1129 clock-names = "uart", "clk_uart_baud0"; 1130 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1131 pinctrl-0 = <&uart11_bus_single>; 1132 pinctrl-names = "default"; 1133 samsung,uart-fifosize = <64>; 1134 status = "disabled"; 1135 }; 1136 1137 spi_11: spi@10d40000 { 1138 compatible = "google,gs101-spi"; 1139 reg = <0x10d40000 0x30>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1143 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1144 clock-names = "spi", "spi_busclk0"; 1145 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1146 pinctrl-0 = <&spi11_bus>; 1147 pinctrl-names = "default"; 1148 status = "disabled"; 1149 }; 1150 }; 1151 1152 usi12: usi@10d500c0 { 1153 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1154 reg = <0x10d500c0 0x20>; 1155 ranges; 1156 #address-cells = <1>; 1157 #size-cells = <1>; 1158 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1159 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1160 clock-names = "pclk", "ipclk"; 1161 samsung,sysreg = <&sysreg_peric1 0x1010>; 1162 status = "disabled"; 1163 1164 hsi2c_12: i2c@10d50000 { 1165 compatible = "google,gs101-hsi2c", 1166 "samsung,exynosautov9-hsi2c"; 1167 reg = <0x10d50000 0xc0>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 1171 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 1172 clock-names = "hsi2c", "hsi2c_pclk"; 1173 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1174 pinctrl-0 = <&hsi2c12_bus>; 1175 pinctrl-names = "default"; 1176 status = "disabled"; 1177 }; 1178 1179 serial_12: serial@10d50000 { 1180 compatible = "google,gs101-uart"; 1181 reg = <0x10d50000 0xc0>; 1182 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1183 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1184 clock-names = "uart", "clk_uart_baud0"; 1185 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1186 pinctrl-0 = <&uart12_bus_single>; 1187 pinctrl-names = "default"; 1188 samsung,uart-fifosize = <64>; 1189 status = "disabled"; 1190 }; 1191 1192 spi_12: spi@10d50000 { 1193 compatible = "google,gs101-spi"; 1194 reg = <0x10d50000 0x30>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1198 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1199 clock-names = "spi", "spi_busclk0"; 1200 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1201 pinctrl-0 = <&spi12_bus>; 1202 pinctrl-names = "default"; 1203 status = "disabled"; 1204 }; 1205 }; 1206 1207 usi13: usi@10d600c0 { 1208 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1209 reg = <0x10d600c0 0x20>; 1210 ranges; 1211 #address-cells = <1>; 1212 #size-cells = <1>; 1213 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1214 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1215 clock-names = "pclk", "ipclk"; 1216 samsung,sysreg = <&sysreg_peric1 0x1014>; 1217 status = "disabled"; 1218 1219 hsi2c_13: i2c@10d60000 { 1220 compatible = "google,gs101-hsi2c", 1221 "samsung,exynosautov9-hsi2c"; 1222 reg = <0x10d60000 0xc0>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, 1226 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; 1227 clock-names = "hsi2c", "hsi2c_pclk"; 1228 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1229 pinctrl-0 = <&hsi2c13_bus>; 1230 pinctrl-names = "default"; 1231 status = "disabled"; 1232 }; 1233 1234 serial_13: serial@10d60000 { 1235 compatible = "google,gs101-uart"; 1236 reg = <0x10d60000 0xc0>; 1237 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1238 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1239 clock-names = "uart", "clk_uart_baud0"; 1240 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1241 pinctrl-0 = <&uart13_bus_single>; 1242 pinctrl-names = "default"; 1243 samsung,uart-fifosize = <64>; 1244 status = "disabled"; 1245 }; 1246 1247 spi_13: spi@10d60000 { 1248 compatible = "google,gs101-spi"; 1249 reg = <0x10d60000 0x30>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1253 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1254 clock-names = "spi", "spi_busclk0"; 1255 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1256 pinctrl-0 = <&spi13_bus>; 1257 pinctrl-names = "default"; 1258 status = "disabled"; 1259 }; 1260 }; 1261 1262 cmu_hsi0: clock-controller@11000000 { 1263 compatible = "google,gs101-cmu-hsi0"; 1264 reg = <0x11000000 0x4000>; 1265 #clock-cells = <1>; 1266 1267 clocks = <&ext_24_5m>, 1268 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 1269 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, 1270 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 1271 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; 1272 clock-names = "oscclk", "bus", "dpgtc", "usb31drd", 1273 "usbdpdbg"; 1274 }; 1275 1276 usbdrd31_phy: phy@11100000 { 1277 compatible = "google,gs101-usb31drd-phy"; 1278 reg = <0x11100000 0x0200>, 1279 <0x110f0000 0x0800>, 1280 <0x110e0000 0x2800>; 1281 reg-names = "phy", "pcs", "pma"; 1282 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 1283 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, 1284 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, 1285 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, 1286 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; 1287 clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; 1288 #phy-cells = <1>; 1289 samsung,pmu-syscon = <&pmu_system_controller>; 1290 status = "disabled"; 1291 }; 1292 1293 usbdrd31: usb@11110000 { 1294 compatible = "google,gs101-dwusb3"; 1295 ranges = <0x0 0x11110000 0x10000>; 1296 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 1297 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, 1298 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, 1299 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; 1300 clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; 1301 #address-cells = <1>; 1302 #size-cells = <1>; 1303 status = "disabled"; 1304 1305 usbdrd31_dwc3: usb@0 { 1306 compatible = "snps,dwc3"; 1307 reg = <0x0 0x10000>; 1308 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; 1309 clock-names = "ref"; 1310 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1311 phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; 1312 phy-names = "usb2-phy", "usb3-phy"; 1313 snps,has-lpm-erratum; 1314 snps,dis_u2_susphy_quirk; 1315 snps,dis_u3_susphy_quirk; 1316 status = "disabled"; 1317 }; 1318 }; 1319 1320 pinctrl_hsi1: pinctrl@11840000 { 1321 compatible = "google,gs101-pinctrl"; 1322 reg = <0x11840000 0x00001000>; 1323 /* TODO: update once support for this CMU exists */ 1324 clocks = <0>; 1325 clock-names = "pclk"; 1326 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1327 }; 1328 1329 cmu_hsi2: clock-controller@14400000 { 1330 compatible = "google,gs101-cmu-hsi2"; 1331 reg = <0x14400000 0x4000>; 1332 #clock-cells = <1>; 1333 clocks = <&ext_24_5m>, 1334 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, 1335 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, 1336 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, 1337 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; 1338 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1339 }; 1340 1341 sysreg_hsi2: syscon@14420000 { 1342 compatible = "google,gs101-hsi2-sysreg", "syscon"; 1343 reg = <0x14420000 0x10000>; 1344 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1345 }; 1346 1347 pinctrl_hsi2: pinctrl@14440000 { 1348 compatible = "google,gs101-pinctrl"; 1349 reg = <0x14440000 0x00001000>; 1350 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; 1351 clock-names = "pclk"; 1352 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 1353 }; 1354 1355 ufs_0: ufs@14700000 { 1356 compatible = "google,gs101-ufs"; 1357 reg = <0x14700000 0x200>, 1358 <0x14701100 0x200>, 1359 <0x14780000 0xa000>, 1360 <0x14600000 0x100>; 1361 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1362 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1363 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, 1364 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, 1365 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, 1366 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, 1367 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, 1368 <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1369 clock-names = "core_clk", "sclk_unipro_main", "fmp", 1370 "aclk", "pclk", "sysreg"; 1371 freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; 1372 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1373 pinctrl-names = "default"; 1374 phys = <&ufs_0_phy>; 1375 phy-names = "ufs-phy"; 1376 samsung,sysreg = <&sysreg_hsi2 0x710>; 1377 status = "disabled"; 1378 }; 1379 1380 ufs_0_phy: phy@14704000 { 1381 compatible = "google,gs101-ufs-phy"; 1382 reg = <0x14704000 0x3000>; 1383 reg-names = "phy-pma"; 1384 samsung,pmu-syscon = <&pmu_system_controller>; 1385 #phy-cells = <0>; 1386 clocks = <&ext_24_5m>; 1387 clock-names = "ref_clk"; 1388 status = "disabled"; 1389 }; 1390 1391 cmu_apm: clock-controller@17400000 { 1392 compatible = "google,gs101-cmu-apm"; 1393 reg = <0x17400000 0x8000>; 1394 #clock-cells = <1>; 1395 1396 clocks = <&ext_24_5m>; 1397 clock-names = "oscclk"; 1398 }; 1399 1400 sysreg_apm: syscon@174204e0 { 1401 compatible = "google,gs101-apm-sysreg", "syscon"; 1402 reg = <0x174204e0 0x1000>; 1403 }; 1404 1405 pmu_system_controller: system-controller@17460000 { 1406 compatible = "google,gs101-pmu", "syscon"; 1407 reg = <0x17460000 0x10000>; 1408 1409 poweroff: syscon-poweroff { 1410 compatible = "syscon-poweroff"; 1411 offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ 1412 mask = <0x00000100>; 1413 value = <0x0>; 1414 }; 1415 1416 reboot: syscon-reboot { 1417 compatible = "syscon-reboot"; 1418 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 1419 mask = <0x2>; /* SWRESET_SYSTEM */ 1420 value = <0x2>; /* reset value */ 1421 }; 1422 1423 reboot-mode { 1424 compatible = "syscon-reboot-mode"; 1425 offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ 1426 mode-bootloader = <0xfc>; 1427 mode-charge = <0x0a>; 1428 mode-fastboot = <0xfa>; 1429 mode-reboot-ab-update = <0x52>; 1430 mode-recovery = <0xff>; 1431 mode-rescue = <0xf9>; 1432 mode-shutdown-thermal = <0x51>; 1433 mode-shutdown-thermal-battery = <0x51>; 1434 }; 1435 }; 1436 1437 pinctrl_gpio_alive: pinctrl@174d0000 { 1438 compatible = "google,gs101-pinctrl"; 1439 reg = <0x174d0000 0x00001000>; 1440 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; 1441 clock-names = "pclk"; 1442 1443 wakeup-interrupt-controller { 1444 compatible = "google,gs101-wakeup-eint", 1445 "samsung,exynos850-wakeup-eint", 1446 "samsung,exynos7-wakeup-eint"; 1447 }; 1448 }; 1449 1450 pinctrl_far_alive: pinctrl@174e0000 { 1451 compatible = "google,gs101-pinctrl"; 1452 reg = <0x174e0000 0x00001000>; 1453 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; 1454 clock-names = "pclk"; 1455 1456 wakeup-interrupt-controller { 1457 compatible = "google,gs101-wakeup-eint", 1458 "samsung,exynos850-wakeup-eint", 1459 "samsung,exynos7-wakeup-eint"; 1460 }; 1461 }; 1462 1463 ap2apm_mailbox: mailbox@17610000 { 1464 compatible = "google,gs101-mbox"; 1465 reg = <0x17610000 0x1000>; 1466 clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; 1467 clock-names = "pclk"; 1468 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>; 1469 #mbox-cells = <0>; 1470 }; 1471 1472 pinctrl_gsactrl: pinctrl@17940000 { 1473 compatible = "google,gs101-pinctrl"; 1474 reg = <0x17940000 0x00001000>; 1475 /* TODO: update once support for this CMU exists */ 1476 clocks = <0>; 1477 clock-names = "pclk"; 1478 }; 1479 1480 pinctrl_gsacore: pinctrl@17a80000 { 1481 compatible = "google,gs101-pinctrl"; 1482 reg = <0x17a80000 0x00001000>; 1483 /* TODO: update once support for this CMU exists */ 1484 clocks = <0>; 1485 clock-names = "pclk"; 1486 status = "disabled"; 1487 }; 1488 1489 cmu_top: clock-controller@1e080000 { 1490 compatible = "google,gs101-cmu-top"; 1491 reg = <0x1e080000 0x8000>; 1492 #clock-cells = <1>; 1493 1494 clocks = <&ext_24_5m>; 1495 clock-names = "oscclk"; 1496 }; 1497 }; 1498 1499 apm_sram: sram@2039000 { 1500 compatible = "mmio-sram"; 1501 reg = <0x0 0x2039000 0x40000>; 1502 #address-cells = <1>; 1503 #size-cells = <1>; 1504 ranges = <0x0 0x0 0x2039000 0x40000>; 1505 }; 1506 1507 timer { 1508 compatible = "arm,armv8-timer"; 1509 interrupts = 1510 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1511 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1512 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1513 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 1514 }; 1515}; 1516 1517#include "gs101-pinctrl.dtsi" 1518