1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAutov920 SoC device tree source 4 * 5 * Copyright (c) 2023 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov920.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,exynos-usi.h> 12 13/ { 14 compatible = "samsung,exynosautov920"; 15 #address-cells = <2>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 pinctrl0 = &pinctrl_alive; 22 pinctrl1 = &pinctrl_aud; 23 pinctrl2 = &pinctrl_hsi0; 24 pinctrl3 = &pinctrl_hsi1; 25 pinctrl4 = &pinctrl_hsi2; 26 pinctrl5 = &pinctrl_hsi2ufs; 27 pinctrl6 = &pinctrl_peric0; 28 pinctrl7 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a78-pmu"; 33 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 34 }; 35 36 xtcxo: clock { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-output-names = "oscclk"; 40 }; 41 42 cpus: cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu0>; 50 }; 51 core1 { 52 cpu = <&cpu1>; 53 }; 54 core2 { 55 cpu = <&cpu2>; 56 }; 57 core3 { 58 cpu = <&cpu3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu4>; 65 }; 66 core1 { 67 cpu = <&cpu5>; 68 }; 69 core2 { 70 cpu = <&cpu6>; 71 }; 72 core3 { 73 cpu = <&cpu7>; 74 }; 75 }; 76 77 cluster2 { 78 core0 { 79 cpu = <&cpu8>; 80 }; 81 core1 { 82 cpu = <&cpu9>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a78ae"; 90 reg = <0x0 0x0>; 91 enable-method = "psci"; 92 i-cache-size = <0x10000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <256>; 95 d-cache-size = <0x10000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <256>; 98 next-level-cache = <&l2_cache_cl0>; 99 }; 100 101 cpu1: cpu@100 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a78ae"; 104 reg = <0x0 0x100>; 105 enable-method = "psci"; 106 i-cache-size = <0x10000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <0x10000>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <256>; 112 next-level-cache = <&l2_cache_cl0>; 113 }; 114 115 cpu2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a78ae"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 i-cache-size = <0x10000>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <256>; 123 d-cache-size = <0x10000>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <256>; 126 next-level-cache = <&l2_cache_cl0>; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78ae"; 132 reg = <0x0 0x300>; 133 enable-method = "psci"; 134 i-cache-size = <0x10000>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; 137 d-cache-size = <0x10000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <256>; 140 next-level-cache = <&l2_cache_cl0>; 141 }; 142 143 cpu4: cpu@10000 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a78ae"; 146 reg = <0x0 0x10000>; 147 enable-method = "psci"; 148 i-cache-size = <0x10000>; 149 i-cache-line-size = <64>; 150 i-cache-sets = <256>; 151 d-cache-size = <0x10000>; 152 d-cache-line-size = <64>; 153 d-cache-sets = <256>; 154 next-level-cache = <&l2_cache_cl1>; 155 }; 156 157 cpu5: cpu@10100 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a78ae"; 160 reg = <0x0 0x10100>; 161 enable-method = "psci"; 162 i-cache-size = <0x10000>; 163 i-cache-line-size = <64>; 164 i-cache-sets = <256>; 165 d-cache-size = <0x10000>; 166 d-cache-line-size = <64>; 167 d-cache-sets = <256>; 168 next-level-cache = <&l2_cache_cl1>; 169 }; 170 171 cpu6: cpu@10200 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a78ae"; 174 reg = <0x0 0x10200>; 175 enable-method = "psci"; 176 i-cache-size = <0x10000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x10000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_cache_cl1>; 183 }; 184 185 cpu7: cpu@10300 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a78ae"; 188 reg = <0x0 0x10300>; 189 enable-method = "psci"; 190 i-cache-size = <0x10000>; 191 i-cache-line-size = <64>; 192 i-cache-sets = <256>; 193 d-cache-size = <0x10000>; 194 d-cache-line-size = <64>; 195 d-cache-sets = <256>; 196 next-level-cache = <&l2_cache_cl1>; 197 }; 198 199 cpu8: cpu@20000 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a78ae"; 202 reg = <0x0 0x20000>; 203 enable-method = "psci"; 204 i-cache-size = <0x10000>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <0x10000>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_cache_cl2>; 211 }; 212 213 cpu9: cpu@20100 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-a78ae"; 216 reg = <0x0 0x20100>; 217 enable-method = "psci"; 218 i-cache-size = <0x10000>; 219 i-cache-line-size = <64>; 220 i-cache-sets = <256>; 221 d-cache-size = <0x10000>; 222 d-cache-line-size = <64>; 223 d-cache-sets = <256>; 224 next-level-cache = <&l2_cache_cl2>; 225 }; 226 227 l2_cache_cl0: l2-cache0 { 228 compatible = "cache"; 229 cache-level = <2>; 230 cache-unified; 231 cache-size = <0x40000>; 232 cache-line-size = <64>; 233 cache-sets = <512>; 234 next-level-cache = <&l3_cache_cl0>; 235 }; 236 237 l2_cache_cl1: l2-cache1 { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 cache-size = <0x40000>; 242 cache-line-size = <64>; 243 cache-sets = <512>; 244 next-level-cache = <&l3_cache_cl1>; 245 }; 246 247 l2_cache_cl2: l2-cache2 { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 cache-size = <0x40000>; 252 cache-line-size = <64>; 253 cache-sets = <512>; 254 next-level-cache = <&l3_cache_cl2>; 255 }; 256 257 l3_cache_cl0: l3-cache0 { 258 compatible = "cache"; 259 cache-level = <3>; 260 cache-unified; 261 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ 262 cache-line-size = <64>; 263 cache-sets = <2048>; 264 }; 265 266 l3_cache_cl1: l3-cache1 { 267 compatible = "cache"; 268 cache-level = <3>; 269 cache-unified; 270 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ 271 cache-line-size = <64>; 272 cache-sets = <2048>; 273 }; 274 275 l3_cache_cl2: l3-cache2 { 276 compatible = "cache"; 277 cache-level = <3>; 278 cache-unified; 279 cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ 280 cache-line-size = <64>; 281 cache-sets = <1365>; 282 }; 283 }; 284 285 psci { 286 compatible = "arm,psci-1.0"; 287 method = "smc"; 288 }; 289 290 soc: soc@0 { 291 compatible = "simple-bus"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges = <0x0 0x0 0x0 0x20000000>; 295 296 chipid@10000000 { 297 compatible = "samsung,exynosautov920-chipid", 298 "samsung,exynos850-chipid"; 299 reg = <0x10000000 0x24>; 300 }; 301 302 cmu_misc: clock-controller@10020000 { 303 compatible = "samsung,exynosautov920-cmu-misc"; 304 reg = <0x10020000 0x8000>; 305 #clock-cells = <1>; 306 307 clocks = <&xtcxo>, 308 <&cmu_top DOUT_CLKCMU_MISC_NOC>; 309 clock-names = "oscclk", 310 "noc"; 311 }; 312 313 watchdog_cl0: watchdog@10060000 { 314 compatible = "samsung,exynosautov920-wdt"; 315 reg = <0x10060000 0x100>; 316 interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&xtcxo>, <&xtcxo>; 318 clock-names = "watchdog", "watchdog_src"; 319 samsung,syscon-phandle = <&pmu_system_controller>; 320 samsung,cluster-index = <0>; 321 }; 322 323 watchdog_cl1: watchdog@10070000 { 324 compatible = "samsung,exynosautov920-wdt"; 325 reg = <0x10070000 0x100>; 326 interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&xtcxo>, <&xtcxo>; 328 clock-names = "watchdog", "watchdog_src"; 329 samsung,syscon-phandle = <&pmu_system_controller>; 330 samsung,cluster-index = <1>; 331 }; 332 333 gic: interrupt-controller@10400000 { 334 compatible = "arm,gic-v3"; 335 #interrupt-cells = <3>; 336 #address-cells = <0>; 337 interrupt-controller; 338 reg = <0x10400000 0x10000>, 339 <0x10460000 0x140000>; 340 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 341 }; 342 343 spdma0: dma-controller@10180000 { 344 compatible = "arm,pl330", "arm,primecell"; 345 reg = <0x10180000 0x1000>; 346 interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 348 clock-names = "apb_pclk"; 349 #dma-cells = <1>; 350 }; 351 352 spdma1: dma-controller@10190000 { 353 compatible = "arm,pl330", "arm,primecell"; 354 reg = <0x10190000 0x1000>; 355 interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 357 clock-names = "apb_pclk"; 358 #dma-cells = <1>; 359 }; 360 361 pdma0: dma-controller@101a0000 { 362 compatible = "arm,pl330", "arm,primecell"; 363 reg = <0x101a0000 0x1000>; 364 interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 366 clock-names = "apb_pclk"; 367 #dma-cells = <1>; 368 }; 369 370 pdma1: dma-controller@101b0000 { 371 compatible = "arm,pl330", "arm,primecell"; 372 reg = <0x101b0000 0x1000>; 373 interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 375 clock-names = "apb_pclk"; 376 #dma-cells = <1>; 377 }; 378 379 pdma2: dma-controller@101c0000 { 380 compatible = "arm,pl330", "arm,primecell"; 381 reg = <0x101c0000 0x1000>; 382 interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 384 clock-names = "apb_pclk"; 385 #dma-cells = <1>; 386 }; 387 388 pdma3: dma-controller@101d0000 { 389 compatible = "arm,pl330", "arm,primecell"; 390 reg = <0x101d0000 0x1000>; 391 interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 393 clock-names = "apb_pclk"; 394 #dma-cells = <1>; 395 }; 396 397 pdma4: dma-controller@101e0000 { 398 compatible = "arm,pl330", "arm,primecell"; 399 reg = <0x101e0000 0x1000>; 400 interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 402 clock-names = "apb_pclk"; 403 #dma-cells = <1>; 404 }; 405 406 cmu_peric0: clock-controller@10800000 { 407 compatible = "samsung,exynosautov920-cmu-peric0"; 408 reg = <0x10800000 0x8000>; 409 #clock-cells = <1>; 410 411 clocks = <&xtcxo>, 412 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, 413 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 414 clock-names = "oscclk", 415 "noc", 416 "ip"; 417 }; 418 419 syscon_peric0: syscon@10820000 { 420 compatible = "samsung,exynosautov920-peric0-sysreg", 421 "syscon"; 422 reg = <0x10820000 0x2000>; 423 }; 424 425 pinctrl_peric0: pinctrl@10830000 { 426 compatible = "samsung,exynosautov920-pinctrl"; 427 reg = <0x10830000 0x10000>; 428 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>; 429 }; 430 431 usi_0: usi@108800c0 { 432 compatible = "samsung,exynosautov920-usi", 433 "samsung,exynos850-usi"; 434 reg = <0x108800c0 0x20>; 435 samsung,sysreg = <&syscon_peric0 0x1000>; 436 samsung,mode = <USI_V2_UART>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges; 440 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 441 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 442 clock-names = "pclk", "ipclk"; 443 status = "disabled"; 444 445 serial_0: serial@10880000 { 446 compatible = "samsung,exynosautov920-uart", 447 "samsung,exynos850-uart"; 448 reg = <0x10880000 0xc0>; 449 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&uart0_bus>; 452 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 453 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 454 clock-names = "uart", "clk_uart_baud0"; 455 samsung,uart-fifosize = <256>; 456 status = "disabled"; 457 }; 458 }; 459 460 pwm: pwm@109b0000 { 461 compatible = "samsung,exynosautov920-pwm", 462 "samsung,exynos4210-pwm"; 463 reg = <0x109b0000 0x100>; 464 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 465 #pwm-cells = <3>; 466 clocks = <&xtcxo>; 467 clock-names = "timers"; 468 status = "disabled"; 469 }; 470 471 cmu_peric1: clock-controller@10c00000 { 472 compatible = "samsung,exynosautov920-cmu-peric1"; 473 reg = <0x10c00000 0x8000>; 474 #clock-cells = <1>; 475 476 clocks = <&xtcxo>, 477 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>, 478 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 479 clock-names = "oscclk", 480 "noc", 481 "ip"; 482 }; 483 484 syscon_peric1: syscon@10c20000 { 485 compatible = "samsung,exynosautov920-peric1-sysreg", 486 "syscon"; 487 reg = <0x10c20000 0x2000>; 488 }; 489 490 pinctrl_peric1: pinctrl@10c30000 { 491 compatible = "samsung,exynosautov920-pinctrl"; 492 reg = <0x10c30000 0x10000>; 493 interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 494 }; 495 496 cmu_top: clock-controller@11000000 { 497 compatible = "samsung,exynosautov920-cmu-top"; 498 reg = <0x11000000 0x8000>; 499 #clock-cells = <1>; 500 501 clocks = <&xtcxo>; 502 clock-names = "oscclk"; 503 }; 504 505 pinctrl_alive: pinctrl@11850000 { 506 compatible = "samsung,exynosautov920-pinctrl"; 507 reg = <0x11850000 0x10000>; 508 509 wakeup-interrupt-controller { 510 compatible = "samsung,exynosautov920-wakeup-eint"; 511 }; 512 }; 513 514 pmu_system_controller: system-controller@11860000 { 515 compatible = "samsung,exynosautov920-pmu", 516 "samsung,exynos7-pmu","syscon"; 517 reg = <0x11860000 0x10000>; 518 }; 519 520 cmu_hsi0: clock-controller@16000000 { 521 compatible = "samsung,exynosautov920-cmu-hsi0"; 522 reg = <0x16000000 0x8000>; 523 #clock-cells = <1>; 524 525 clocks = <&xtcxo>, 526 <&cmu_top DOUT_CLKCMU_HSI0_NOC>; 527 clock-names = "oscclk", 528 "noc"; 529 }; 530 531 pinctrl_hsi0: pinctrl@16040000 { 532 compatible = "samsung,exynosautov920-pinctrl"; 533 reg = <0x16040000 0x10000>; 534 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 535 }; 536 537 cmu_hsi1: clock-controller@16400000 { 538 compatible = "samsung,exynosautov920-cmu-hsi1"; 539 reg = <0x16400000 0x8000>; 540 #clock-cells = <1>; 541 542 clocks = <&xtcxo>, 543 <&cmu_top DOUT_CLKCMU_HSI1_NOC>, 544 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>, 545 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>; 546 clock-names = "oscclk", 547 "noc", 548 "usbdrd", 549 "mmc_card"; 550 }; 551 552 pinctrl_hsi1: pinctrl@16450000 { 553 compatible = "samsung,exynosautov920-pinctrl"; 554 reg = <0x16450000 0x10000>; 555 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 556 }; 557 558 pinctrl_hsi2: pinctrl@16c10000 { 559 compatible = "samsung,exynosautov920-pinctrl"; 560 reg = <0x16c10000 0x10000>; 561 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 562 }; 563 564 pinctrl_hsi2ufs: pinctrl@16d20000 { 565 compatible = "samsung,exynosautov920-pinctrl"; 566 reg = <0x16d20000 0x10000>; 567 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 568 }; 569 570 ufs_0_phy: phy@16e04000 { 571 compatible = "samsung,exynosautov920-ufs-phy"; 572 reg = <0x16e04000 0x4000>; 573 reg-names = "phy-pma"; 574 clocks = <&xtcxo>; 575 clock-names = "ref_clk"; 576 samsung,pmu-syscon = <&pmu_system_controller>; 577 #phy-cells = <0>; 578 status = "disabled"; 579 }; 580 581 pinctrl_aud: pinctrl@1a460000 { 582 compatible = "samsung,exynosautov920-pinctrl"; 583 reg = <0x1a460000 0x10000>; 584 }; 585 }; 586 587 timer { 588 compatible = "arm,armv8-timer"; 589 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 590 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 591 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 592 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 593 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 594 }; 595}; 596 597#include "exynosautov920-pinctrl.dtsi" 598