1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on
4 * Apple T6000 / T6001 "M1 Pro" / "M1 Max".
5 *
6 * Copyright The Asahi Linux Contributors
7 */
8
9
10	nco: clock-controller@28e03c000 {
11		compatible = "apple,t6000-nco", "apple,nco";
12		reg = <0x2 0x8e03c000 0x0 0x14000>;
13		clocks = <&nco_clkref>;
14		#clock-cells = <1>;
15	};
16
17	aic: interrupt-controller@28e100000 {
18		compatible = "apple,t6000-aic", "apple,aic2";
19		#interrupt-cells = <4>;
20		interrupt-controller;
21		reg = <0x2 0x8e100000 0x0 0xc000>,
22			<0x2 0x8e10c000 0x0 0x4>;
23		reg-names = "core", "event";
24		power-domains = <&ps_aic>;
25	};
26
27	pinctrl_smc: pinctrl@290820000 {
28		compatible = "apple,t6000-pinctrl", "apple,pinctrl";
29		reg = <0x2 0x90820000 0x0 0x4000>;
30
31		gpio-controller;
32		#gpio-cells = <2>;
33		gpio-ranges = <&pinctrl_smc 0 0 30>;
34		apple,npins = <30>;
35
36		interrupt-controller;
37		#interrupt-cells = <2>;
38		interrupt-parent = <&aic>;
39		interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>,
40				<AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>,
41				<AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>,
42				<AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>,
43				<AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH>,
44				<AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH>,
45				<AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>;
46	};
47
48	wdt: watchdog@2922b0000 {
49		compatible = "apple,t6000-wdt", "apple,wdt";
50		reg = <0x2 0x922b0000 0x0 0x4000>;
51		clocks = <&clkref>;
52		interrupt-parent = <&aic>;
53		interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>;
54	};
55
56	sio_dart_0: iommu@39b004000 {
57		compatible = "apple,t6000-dart";
58		reg = <0x3 0x9b004000 0x0 0x4000>;
59		interrupt-parent = <&aic>;
60		interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>;
61		#iommu-cells = <1>;
62		power-domains = <&ps_sio_cpu>;
63	};
64
65	sio_dart_1: iommu@39b008000 {
66		compatible = "apple,t6000-dart";
67		reg = <0x3 0x9b008000 0x0 0x8000>;
68		interrupt-parent = <&aic>;
69		interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>;
70		#iommu-cells = <1>;
71		power-domains = <&ps_sio_cpu>;
72	};
73
74	fpwm0: pwm@39b030000 {
75		compatible = "apple,t6000-fpwm", "apple,s5l-fpwm";
76		reg = <0x3 0x9b030000 0x0 0x4000>;
77		power-domains = <&ps_fpwm0>;
78		clocks = <&clkref>;
79		#pwm-cells = <2>;
80		status = "disabled";
81	};
82
83	i2c0: i2c@39b040000 {
84		compatible = "apple,t6000-i2c", "apple,i2c";
85		reg = <0x3 0x9b040000 0x0 0x4000>;
86		clocks = <&clkref>;
87		interrupt-parent = <&aic>;
88		interrupts = <AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH>;
89		pinctrl-0 = <&i2c0_pins>;
90		pinctrl-names = "default";
91		power-domains = <&ps_i2c0>;
92		#address-cells = <0x1>;
93		#size-cells = <0x0>;
94	};
95
96	i2c1: i2c@39b044000 {
97		compatible = "apple,t6000-i2c", "apple,i2c";
98		reg = <0x3 0x9b044000 0x0 0x4000>;
99		clocks = <&clkref>;
100		interrupt-parent = <&aic>;
101		interrupts = <AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH>;
102		pinctrl-0 = <&i2c1_pins>;
103		pinctrl-names = "default";
104		power-domains = <&ps_i2c1>;
105		#address-cells = <0x1>;
106		#size-cells = <0x0>;
107		status = "disabled";
108	};
109
110	i2c2: i2c@39b048000 {
111		compatible = "apple,t6000-i2c", "apple,i2c";
112		reg = <0x3 0x9b048000 0x0 0x4000>;
113		clocks = <&clkref>;
114		interrupt-parent = <&aic>;
115		interrupts = <AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH>;
116		pinctrl-0 = <&i2c2_pins>;
117		pinctrl-names = "default";
118		power-domains = <&ps_i2c2>;
119		#address-cells = <0x1>;
120		#size-cells = <0x0>;
121		status = "disabled";
122	};
123
124	i2c3: i2c@39b04c000 {
125		compatible = "apple,t6000-i2c", "apple,i2c";
126		reg = <0x3 0x9b04c000 0x0 0x4000>;
127		clocks = <&clkref>;
128		interrupt-parent = <&aic>;
129		interrupts = <AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH>;
130		pinctrl-0 = <&i2c3_pins>;
131		pinctrl-names = "default";
132		power-domains = <&ps_i2c3>;
133		#address-cells = <0x1>;
134		#size-cells = <0x0>;
135		status = "disabled";
136	};
137
138	i2c4: i2c@39b050000 {
139		compatible = "apple,t6000-i2c", "apple,i2c";
140		reg = <0x3 0x9b050000 0x0 0x4000>;
141		clocks = <&clkref>;
142		interrupt-parent = <&aic>;
143		interrupts = <AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH>;
144		pinctrl-0 = <&i2c4_pins>;
145		pinctrl-names = "default";
146		power-domains = <&ps_i2c4>;
147		#address-cells = <0x1>;
148		#size-cells = <0x0>;
149		status = "disabled";
150	};
151
152	i2c5: i2c@39b054000 {
153		compatible = "apple,t6000-i2c", "apple,i2c";
154		reg = <0x3 0x9b054000 0x0 0x4000>;
155		clocks = <&clkref>;
156		interrupt-parent = <&aic>;
157		interrupts = <AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH>;
158		pinctrl-0 = <&i2c5_pins>;
159		pinctrl-names = "default";
160		power-domains = <&ps_i2c5>;
161		#address-cells = <0x1>;
162		#size-cells = <0x0>;
163		status = "disabled";
164	};
165
166	spi1: spi@39b104000 {
167		compatible = "apple,t6000-spi", "apple,spi";
168		reg = <0x3 0x9b104000 0x0 0x4000>;
169		interrupt-parent = <&aic>;
170		interrupts = <AIC_IRQ 0 1107 IRQ_TYPE_LEVEL_HIGH>;
171		#address-cells = <1>;
172		#size-cells = <0>;
173		clocks = <&clk_200m>;
174		pinctrl-0 = <&spi1_pins>;
175		pinctrl-names = "default";
176		power-domains = <&ps_spi1>;
177		status = "disabled";
178	};
179
180	spi3: spi@39b10c000 {
181		compatible = "apple,t6000-spi", "apple,spi";
182		reg = <0x3 0x9b10c000 0x0 0x4000>;
183		interrupt-parent = <&aic>;
184		interrupts = <AIC_IRQ 0 1109 IRQ_TYPE_LEVEL_HIGH>;
185		#address-cells = <1>;
186		#size-cells = <0>;
187		clocks = <&clkref>;
188		pinctrl-0 = <&spi3_pins>;
189		pinctrl-names = "default";
190		power-domains = <&ps_spi3>;
191		status = "disabled";
192	};
193
194	serial0: serial@39b200000 {
195		compatible = "apple,s5l-uart";
196		reg = <0x3 0x9b200000 0x0 0x1000>;
197		reg-io-width = <4>;
198		interrupt-parent = <&aic>;
199		interrupts = <AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH>;
200		/*
201		 * TODO: figure out the clocking properly, there may
202		 * be a third selectable clock.
203		 */
204		clocks = <&clkref>, <&clkref>;
205		clock-names = "uart", "clk_uart_baud0";
206		power-domains = <&ps_uart0>;
207		status = "disabled";
208	};
209
210	admac: dma-controller@39b400000 {
211		compatible = "apple,t6000-admac", "apple,admac";
212		reg = <0x3 0x9b400000 0x0 0x34000>;
213		#dma-cells = <1>;
214		dma-channels = <16>;
215		interrupts-extended = <0>,
216				      <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>,
217				      <0>,
218				      <0>;
219		iommus = <&sio_dart_0 2>, <&sio_dart_1 2>;
220		power-domains = <&ps_sio_adma>;
221		resets = <&ps_audio_p>;
222	};
223
224	mca: mca@39b600000 {
225		compatible = "apple,t6000-mca", "apple,mca";
226		reg = <0x3 0x9b600000 0x0 0x10000>,
227		      <0x3 0x9b500000 0x0 0x20000>;
228		clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>;
229		dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
230		       <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
231		       <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
232		       <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>;
233		dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
234			    "tx1a", "rx1a", "tx1b", "rx1b",
235			    "tx2a", "rx2a", "tx2b", "rx2b",
236			    "tx3a", "rx3a", "tx3b", "rx3b";
237		interrupt-parent = <&aic>;
238		interrupts = <AIC_IRQ 0 1112 IRQ_TYPE_LEVEL_HIGH>,
239			     <AIC_IRQ 0 1113 IRQ_TYPE_LEVEL_HIGH>,
240			     <AIC_IRQ 0 1114 IRQ_TYPE_LEVEL_HIGH>,
241			     <AIC_IRQ 0 1115 IRQ_TYPE_LEVEL_HIGH>;
242		power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
243				<&ps_mca2>, <&ps_mca3>;
244		resets = <&ps_audio_p>;
245		#sound-dai-cells = <1>;
246	};
247
248	pcie0_dart_0: iommu@581008000 {
249		compatible = "apple,t6000-dart";
250		reg = <0x5 0x81008000 0x0 0x4000>;
251		#iommu-cells = <1>;
252		interrupt-parent = <&aic>;
253		interrupts = <AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH>;
254		power-domains = <&ps_apcie_gp_sys>;
255	};
256
257	pcie0_dart_1: iommu@582008000 {
258		compatible = "apple,t6000-dart";
259		reg = <0x5 0x82008000 0x0 0x4000>;
260		#iommu-cells = <1>;
261		interrupt-parent = <&aic>;
262		interrupts = <AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH>;
263		power-domains = <&ps_apcie_gp_sys>;
264	};
265
266	pcie0_dart_2: iommu@583008000 {
267		compatible = "apple,t6000-dart";
268		reg = <0x5 0x83008000 0x0 0x4000>;
269		#iommu-cells = <1>;
270		interrupt-parent = <&aic>;
271		interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>;
272		power-domains = <&ps_apcie_gp_sys>;
273		status = "disabled";
274	};
275
276	pcie0_dart_3: iommu@584008000 {
277		compatible = "apple,t6000-dart";
278		reg = <0x5 0x84008000 0x0 0x4000>;
279		#iommu-cells = <1>;
280		interrupt-parent = <&aic>;
281		interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>;
282		power-domains = <&ps_apcie_gp_sys>;
283		status = "disabled";
284	};
285
286	pcie0: pcie@590000000 {
287		compatible = "apple,t6000-pcie", "apple,pcie";
288		device_type = "pci";
289
290		reg = <0x5 0x90000000 0x0 0x1000000>,
291			<0x5 0x80000000 0x0 0x100000>,
292			<0x5 0x81000000 0x0 0x4000>,
293			<0x5 0x82000000 0x0 0x4000>,
294			<0x5 0x83000000 0x0 0x4000>,
295			<0x5 0x84000000 0x0 0x4000>;
296		reg-names = "config", "rc", "port0", "port1", "port2", "port3";
297
298		interrupt-parent = <&aic>;
299		interrupts = <AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH>,
300				<AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH>,
301				<AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH>,
302				<AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH>;
303
304		msi-controller;
305		msi-parent = <&pcie0>;
306		msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>;
307
308
309		iommu-map = <0x100 &pcie0_dart_0 1 1>,
310				<0x200 &pcie0_dart_1 1 1>,
311				<0x300 &pcie0_dart_2 1 1>,
312				<0x400 &pcie0_dart_3 1 1>;
313		iommu-map-mask = <0xff00>;
314
315		bus-range = <0 4>;
316		#address-cells = <3>;
317		#size-cells = <2>;
318		ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
319				<0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;
320
321		power-domains = <&ps_apcie_gp_sys>;
322		pinctrl-0 = <&pcie_pins>;
323		pinctrl-names = "default";
324
325		port00: pci@0,0 {
326			device_type = "pci";
327			reg = <0x0 0x0 0x0 0x0 0x0>;
328			reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;
329
330			#address-cells = <3>;
331			#size-cells = <2>;
332			ranges;
333
334			interrupt-controller;
335			#interrupt-cells = <1>;
336
337			interrupt-map-mask = <0 0 0 7>;
338			interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
339					<0 0 0 2 &port00 0 0 0 1>,
340					<0 0 0 3 &port00 0 0 0 2>,
341					<0 0 0 4 &port00 0 0 0 3>;
342		};
343
344		port01: pci@1,0 {
345			device_type = "pci";
346			reg = <0x800 0x0 0x0 0x0 0x0>;
347			reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;
348
349			#address-cells = <3>;
350			#size-cells = <2>;
351			ranges;
352
353			interrupt-controller;
354			#interrupt-cells = <1>;
355
356			interrupt-map-mask = <0 0 0 7>;
357			interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
358					<0 0 0 2 &port01 0 0 0 1>,
359					<0 0 0 3 &port01 0 0 0 2>,
360					<0 0 0 4 &port01 0 0 0 3>;
361		};
362
363		port02: pci@2,0 {
364			device_type = "pci";
365			reg = <0x1000 0x0 0x0 0x0 0x0>;
366			reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;
367
368			#address-cells = <3>;
369			#size-cells = <2>;
370			ranges;
371
372			interrupt-controller;
373			#interrupt-cells = <1>;
374
375			interrupt-map-mask = <0 0 0 7>;
376			interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
377					<0 0 0 2 &port02 0 0 0 1>,
378					<0 0 0 3 &port02 0 0 0 2>,
379					<0 0 0 4 &port02 0 0 0 3>;
380			status = "disabled";
381		};
382
383		port03: pci@3,0 {
384			device_type = "pci";
385			reg = <0x1800 0x0 0x0 0x0 0x0>;
386			reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;
387
388			#address-cells = <3>;
389			#size-cells = <2>;
390			ranges;
391
392			interrupt-controller;
393			#interrupt-cells = <1>;
394
395			interrupt-map-mask = <0 0 0 7>;
396			interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
397					<0 0 0 2 &port03 0 0 0 1>,
398					<0 0 0 3 &port03 0 0 0 2>,
399					<0 0 0 4 &port03 0 0 0 3>;
400			status = "disabled";
401		};
402	};
403