1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2014-2022 Toradex
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pwm/pwm.h>
10
11/ {
12	model = "Toradex Colibri iMX6DL/S Module";
13
14	aliases {
15		mmc0 = &usdhc3; /* eMMC */
16		mmc1 = &usdhc1; /* MMC/SD Slot */
17		/delete-property/ mmc2;
18		/delete-property/ mmc3;
19	};
20
21	backlight: backlight {
22		compatible = "pwm-backlight";
23		brightness-levels = <0 45 63 88 119 158 203 255>;
24		default-brightness-level = <4>;
25		enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_gpio_bl_on>;
28		power-supply = <&reg_module_3v3>;
29		pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>;
30		status = "disabled";
31	};
32
33	extcon_usbc_det: usbc-det {
34		compatible = "linux,extcon-usb-gpio";
35		id-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
36		pinctrl-names = "default";
37		pinctrl-0 = <&pinctrl_usbc_det>;
38	};
39
40	gpio-keys {
41		compatible = "gpio-keys";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_gpio_keys>;
44
45		key-wakeup {
46			debounce-interval = <10>;
47			gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
48			label = "Wake-Up";
49			linux,code = <KEY_WAKEUP>;
50			wakeup-source;
51		};
52	};
53
54	lcd_display: disp0 {
55		compatible = "fsl,imx-parallel-display";
56		interface-pix-fmt = "bgr666";
57		pinctrl-names = "default";
58		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
59		status = "disabled";
60
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		port@0 {
65			reg = <0>;
66
67			lcd_display_in: endpoint {
68				remote-endpoint = <&ipu1_di0_disp0>;
69			};
70		};
71
72		port@1 {
73			reg = <1>;
74
75			lcd_display_out: endpoint {
76				remote-endpoint = <&lcd_panel_in>;
77			};
78		};
79	};
80
81	/* Will be filled by the bootloader */
82	memory@10000000 {
83		device_type = "memory";
84		reg = <0x10000000 0>;
85	};
86
87	panel_dpi: panel-dpi {
88		/*
89		 * edt,et057090dhu: EDT 5.7" LCD TFT
90		 * edt,et070080dh6: EDT 7.0" LCD TFT
91		 */
92		compatible = "edt,et057090dhu";
93		backlight = <&backlight>;
94		status = "disabled";
95
96		port {
97			lcd_panel_in: endpoint {
98				remote-endpoint = <&lcd_display_out>;
99			};
100		};
101	};
102
103	reg_module_3v3: regulator-module-3v3 {
104		compatible = "regulator-fixed";
105		regulator-name = "+V3.3";
106		regulator-min-microvolt = <3300000>;
107		regulator-max-microvolt = <3300000>;
108		regulator-always-on;
109	};
110
111	reg_module_3v3_audio: regulator-module-3v3-audio {
112		compatible = "regulator-fixed";
113		regulator-name = "+V3.3_AUDIO";
114		regulator-min-microvolt = <3300000>;
115		regulator-max-microvolt = <3300000>;
116		regulator-always-on;
117	};
118
119	reg_usb_host_vbus: regulator-usb-host-vbus {
120		compatible = "regulator-fixed";
121		gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
122		pinctrl-names = "default";
123		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
124		regulator-max-microvolt = <5000000>;
125		regulator-min-microvolt = <5000000>;
126		regulator-name = "usb_host_vbus";
127		status = "disabled";
128	};
129
130	sound {
131		compatible = "fsl,imx-audio-sgtl5000";
132		audio-codec = <&codec>;
133		audio-routing =
134			"Headphone Jack", "HP_OUT",
135			"LINE_IN", "Line In Jack",
136			"MIC_IN", "Mic Jack",
137			"Mic Jack", "Mic Bias";
138		model = "colibri-imx6";
139		mux-int-port = <1>;
140		mux-ext-port = <5>;
141		ssi-controller = <&ssi1>;
142	};
143
144	spdif_out: spdif-out {
145		compatible = "linux,spdif-dit";
146		#sound-dai-cells = <0>;
147	};
148
149	spdif_in: spdif-in {
150		compatible = "linux,spdif-dir";
151		#sound-dai-cells = <0>;
152	};
153
154	/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
155	sound_spdif: sound-spdif {
156		compatible = "fsl,imx-audio-spdif";
157		audio-cpu = <&spdif>;
158		audio-codec = <&spdif_out>, <&spdif_in>;
159		model = "imx-spdif";
160		status = "disabled";
161	};
162};
163
164&audmux {
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
167	status = "okay";
168};
169
170/* Optional on SODIMM 55/63 */
171&can1 {
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_flexcan1>;
174	status = "disabled";
175};
176
177/* Optional on SODIMM 178/188 */
178&can2 {
179	pinctrl-names = "default";
180	pinctrl-0 = <&pinctrl_flexcan2>;
181	status = "disabled";
182};
183
184&clks {
185	fsl,pmic-stby-poweroff;
186};
187
188/* Colibri SSP */
189&ecspi4 {
190	cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_ecspi4>;
193	status = "disabled";
194};
195
196&fec {
197	phy-mode = "rmii";
198	phy-handle = <&ethphy>;
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_enet>;
201	status = "okay";
202
203	mdio {
204		#address-cells = <1>;
205		#size-cells = <0>;
206
207		ethphy: ethernet-phy@0 {
208			reg = <0>;
209			micrel,led-mode = <0>;
210		};
211	};
212};
213
214&gpio1 {
215	gpio-line-names = "",
216			  "SODIMM_67",
217			  "SODIMM_180",
218			  "SODIMM_196",
219			  "SODIMM_174",
220			  "SODIMM_176",
221			  "SODIMM_194",
222			  "SODIMM_55",
223			  "SODIMM_63",
224			  "SODIMM_28",
225			  "SODIMM_93",
226			  "SODIMM_69",
227			  "SODIMM_99",
228			  "SODIMM_130",
229			  "SODIMM_106",
230			  "SODIMM_98",
231			  "SODIMM_192",
232			  "SODIMM_49",
233			  "SODIMM_190",
234			  "SODIMM_51",
235			  "SODIMM_47",
236			  "SODIMM_53",
237			  "",
238			  "SODIMM_22";
239};
240
241&gpio2 {
242	gpio-line-names = "SODIMM_132",
243			  "SODIMM_134",
244			  "SODIMM_135",
245			  "SODIMM_133",
246			  "SODIMM_102",
247			  "SODIMM_43",
248			  "SODIMM_127",
249			  "SODIMM_37",
250			  "SODIMM_104",
251			  "SODIMM_59",
252			  "SODIMM_30",
253			  "SODIMM_100",
254			  "SODIMM_38",
255			  "SODIMM_34",
256			  "SODIMM_32",
257			  "SODIMM_36",
258			  "SODIMM_59",
259			  "SODIMM_67",
260			  "SODIMM_97",
261			  "SODIMM_79",
262			  "SODIMM_103",
263			  "SODIMM_101",
264			  "SODIMM_45",
265			  "SODIMM_105",
266			  "SODIMM_107",
267			  "SODIMM_91",
268			  "SODIMM_89",
269			  "SODIMM_150",
270			  "SODIMM_126",
271			  "SODIMM_128",
272			  "",
273			  "SODIMM_94";
274};
275
276&gpio3 {
277	gpio-line-names = "SODIMM_111",
278			  "SODIMM_113",
279			  "SODIMM_115",
280			  "SODIMM_117",
281			  "SODIMM_119",
282			  "SODIMM_121",
283			  "SODIMM_123",
284			  "SODIMM_125",
285			  "SODIMM_110",
286			  "SODIMM_112",
287			  "SODIMM_114",
288			  "SODIMM_116",
289			  "SODIMM_118",
290			  "SODIMM_120",
291			  "SODIMM_122",
292			  "SODIMM_124",
293			  "",
294			  "SODIMM_96",
295			  "SODIMM_77",
296			  "SODIMM_25",
297			  "SODIMM_27",
298			  "SODIMM_88",
299			  "SODIMM_90",
300			  "SODIMM_31",
301			  "SODIMM_23",
302			  "SODIMM_29",
303			  "SODIMM_71",
304			  "SODIMM_73",
305			  "SODIMM_92",
306			  "SODIMM_81",
307			  "SODIMM_131",
308			  "SODIMM_129";
309};
310
311&gpio4 {
312	gpio-line-names = "",
313			  "",
314			  "",
315			  "",
316			  "",
317			  "SODIMM_168",
318			  "",
319			  "",
320			  "",
321			  "",
322			  "SODIMM_184",
323			  "SODIMM_186",
324			  "HDMI_15",
325			  "HDMI_16",
326			  "SODIMM_178",
327			  "SODIMM_188",
328			  "SODIMM_56",
329			  "SODIMM_44",
330			  "SODIMM_68",
331			  "SODIMM_82",
332			  "SODIMM_24",
333			  "SODIMM_76",
334			  "SODIMM_70",
335			  "SODIMM_60",
336			  "SODIMM_58",
337			  "SODIMM_78",
338			  "SODIMM_72",
339			  "SODIMM_80",
340			  "SODIMM_46",
341			  "SODIMM_62",
342			  "SODIMM_48",
343			  "SODIMM_74";
344};
345
346&gpio5 {
347	gpio-line-names = "SODIMM_95",
348			  "",
349			  "SODIMM_86",
350			  "",
351			  "SODIMM_65",
352			  "SODIMM_50",
353			  "SODIMM_52",
354			  "SODIMM_54",
355			  "SODIMM_66",
356			  "SODIMM_64",
357			  "SODIMM_57",
358			  "SODIMM_61",
359			  "SODIMM_136",
360			  "SODIMM_138",
361			  "SODIMM_140",
362			  "SODIMM_142",
363			  "SODIMM_144",
364			  "SODIMM_146",
365			  "SODIMM_172",
366			  "SODIMM_170",
367			  "SODIMM_149",
368			  "SODIMM_151",
369			  "SODIMM_153",
370			  "SODIMM_155",
371			  "SODIMM_157",
372			  "SODIMM_159",
373			  "SODIMM_161",
374			  "SODIMM_163",
375			  "SODIMM_33",
376			  "SODIMM_35",
377			  "SODIMM_165",
378			  "SODIMM_167";
379};
380
381&gpio6 {
382	gpio-line-names = "SODIMM_169",
383			  "SODIMM_171",
384			  "SODIMM_173",
385			  "SODIMM_175",
386			  "SODIMM_177",
387			  "SODIMM_179",
388			  "SODIMM_85",
389			  "SODIMM_166",
390			  "SODIMM_160",
391			  "SODIMM_162",
392			  "SODIMM_158",
393			  "SODIMM_164",
394			  "",
395			  "",
396			  "SODIMM_156",
397			  "SODIMM_75",
398			  "SODIMM_154",
399			  "",
400			  "",
401			  "",
402			  "",
403			  "",
404			  "",
405			  "",
406			  "",
407			  "",
408			  "",
409			  "",
410			  "",
411			  "",
412			  "",
413			  "SODIMM_152";
414};
415
416&gpio7 {
417	gpio-line-names = "",
418			  "",
419			  "",
420			  "",
421			  "",
422			  "",
423			  "",
424			  "",
425			  "",
426			  "SODIMM_19",
427			  "SODIMM_21",
428			  "",
429			  "SODIMM_137";
430};
431
432&hdmi {
433	pinctrl-names = "default";
434	pinctrl-0 = <&pinctrl_hdmi_ddc>;
435	status = "disabled";
436};
437
438/*
439 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
440 * touch screen controller
441 */
442&i2c2 {
443	clock-frequency = <100000>;
444	pinctrl-names = "default", "gpio";
445	pinctrl-0 = <&pinctrl_i2c2>;
446	pinctrl-1 = <&pinctrl_i2c2_gpio>;
447	scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
448	sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
449	status = "okay";
450
451	pmic: pmic@8 {
452		compatible = "fsl,pfuze100";
453		fsl,pmic-stby-poweroff;
454		reg = <0x08>;
455
456		regulators {
457			sw1a_reg: sw1ab {
458				regulator-always-on;
459				regulator-boot-on;
460				regulator-max-microvolt = <1875000>;
461				regulator-min-microvolt = <300000>;
462				regulator-ramp-delay = <6250>;
463			};
464
465			sw1c_reg: sw1c {
466				regulator-always-on;
467				regulator-boot-on;
468				regulator-max-microvolt = <1875000>;
469				regulator-min-microvolt = <300000>;
470				regulator-ramp-delay = <6250>;
471			};
472
473			sw3a_reg: sw3a {
474				regulator-always-on;
475				regulator-boot-on;
476				regulator-max-microvolt = <1975000>;
477				regulator-min-microvolt = <400000>;
478			};
479
480			swbst_reg: swbst {
481				regulator-always-on;
482				regulator-boot-on;
483				regulator-max-microvolt = <5150000>;
484				regulator-min-microvolt = <5000000>;
485			};
486
487			snvs_reg: vsnvs {
488				regulator-always-on;
489				regulator-boot-on;
490				regulator-max-microvolt = <3000000>;
491				regulator-min-microvolt = <1000000>;
492			};
493
494			vref_reg: vrefddr {
495				regulator-always-on;
496				regulator-boot-on;
497			};
498
499			/* vgen1: unused */
500
501			vgen2_reg: vgen2 {
502				regulator-always-on;
503				regulator-boot-on;
504				regulator-max-microvolt = <1550000>;
505				regulator-min-microvolt = <800000>;
506			};
507
508			/*
509			 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
510			 * the i.MX 6 NVCC_SD1.
511			 */
512			vgen3_reg: vgen3 {
513				regulator-always-on;
514				regulator-boot-on;
515				regulator-max-microvolt = <3300000>;
516				regulator-min-microvolt = <1800000>;
517			};
518
519			vgen4_reg: vgen4 {
520				regulator-always-on;
521				regulator-boot-on;
522				regulator-max-microvolt = <1800000>;
523				regulator-min-microvolt = <1800000>;
524			};
525
526			vgen5_reg: vgen5 {
527				regulator-always-on;
528				regulator-boot-on;
529				regulator-max-microvolt = <3300000>;
530				regulator-min-microvolt = <1800000>;
531			};
532
533			vgen6_reg: vgen6 {
534				regulator-always-on;
535				regulator-boot-on;
536				regulator-max-microvolt = <3300000>;
537				regulator-min-microvolt = <1800000>;
538			};
539		};
540	};
541
542	codec: sgtl5000@a {
543		compatible = "fsl,sgtl5000";
544		clocks = <&clks IMX6QDL_CLK_CKO>;
545		lrclk-strength = <3>;
546		pinctrl-names = "default";
547		pinctrl-0 = <&pinctrl_sgtl5000>;
548		reg = <0x0a>;
549		#sound-dai-cells = <0>;
550		VDDA-supply = <&reg_module_3v3_audio>;
551		VDDIO-supply = <&reg_module_3v3>;
552		VDDD-supply = <&vgen4_reg>;
553	};
554
555	/* STMPE811 touch screen controller */
556	stmpe811@41 {
557		compatible = "st,stmpe811";
558		blocks = <0x5>;
559		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
560		interrupt-parent = <&gpio6>;
561		id = <0>;
562		irq-trigger = <0x1>;
563		pinctrl-names = "default";
564		pinctrl-0 = <&pinctrl_touch_int>;
565		reg = <0x41>;
566		/* 3.25 MHz ADC clock speed */
567		st,adc-freq = <1>;
568		/* 12-bit ADC */
569		st,mod-12b = <1>;
570		/* internal ADC reference */
571		st,ref-sel = <0>;
572		/* ADC converstion time: 80 clocks */
573		st,sample-time = <4>;
574
575		stmpe_ts: stmpe_touchscreen {
576			compatible = "st,stmpe-ts";
577			/* 8 sample average control */
578			st,ave-ctrl = <3>;
579			/* 7 length fractional part in z */
580			st,fraction-z = <7>;
581			/*
582			 * 50 mA typical 80 mA max touchscreen drivers
583			 * current limit value
584			 */
585			st,i-drive = <1>;
586			/* 1 ms panel driver settling time */
587			st,settling = <3>;
588			/* 5 ms touch detect interrupt delay */
589			st,touch-det-delay = <5>;
590		};
591
592		stmpe_adc: stmpe_adc {
593			compatible = "st,stmpe-adc";
594			/* forbid to use ADC channels 3-0 (touch) */
595			st,norequest-mask = <0x0F>;
596		};
597	};
598};
599
600/*
601 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
602 */
603&i2c3 {
604	clock-frequency = <100000>;
605	pinctrl-names = "default", "gpio";
606	pinctrl-0 = <&pinctrl_i2c3>;
607	pinctrl-1 = <&pinctrl_i2c3_gpio>;
608	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
609	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
610	status = "disabled";
611
612	atmel_mxt_ts: touchscreen@4a {
613		compatible = "atmel,maxtouch";
614		interrupt-parent = <&gpio2>;
615		interrupts = <24 IRQ_TYPE_EDGE_FALLING>;	/* SODIMM 107 */
616		pinctrl-names = "default";
617		pinctrl-0 = <&pinctrl_atmel_conn>;
618		reg = <0x4a>;
619		reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;	/* SODIMM 106 */
620		status = "disabled";
621	};
622};
623
624&ipu1_di0_disp0 {
625	remote-endpoint = <&lcd_display_in>;
626};
627
628/* Colibri PWM<B> */
629&pwm1 {
630	pinctrl-names = "default";
631	pinctrl-0 = <&pinctrl_pwm1>;
632	status = "disabled";
633};
634
635/* Colibri PWM<D> */
636&pwm2 {
637	pinctrl-names = "default";
638	pinctrl-0 = <&pinctrl_pwm2>;
639	status = "disabled";
640};
641
642/* Colibri PWM<A> */
643&pwm3 {
644	pinctrl-names = "default";
645	pinctrl-0 = <&pinctrl_pwm3>;
646	status = "disabled";
647};
648
649/* Colibri PWM<C> */
650&pwm4 {
651	pinctrl-names = "default";
652	pinctrl-0 = <&pinctrl_pwm4>;
653	status = "disabled";
654};
655
656/* Optional S/PDIF out on SODIMM 137 */
657&spdif {
658	pinctrl-names = "default";
659	pinctrl-0 = <&pinctrl_spdif>;
660	status = "disabled";
661};
662
663&ssi1 {
664	status = "okay";
665};
666
667/* Colibri UART_A */
668&uart1 {
669	fsl,dte-mode;
670	pinctrl-names = "default";
671	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
672	uart-has-rtscts;
673	status = "disabled";
674};
675
676/* Colibri UART_B */
677&uart2 {
678	fsl,dte-mode;
679	pinctrl-names = "default";
680	pinctrl-0 = <&pinctrl_uart2_dte>;
681	uart-has-rtscts;
682	status = "disabled";
683};
684
685/* Colibri UART_C */
686&uart3 {
687	fsl,dte-mode;
688	pinctrl-names = "default";
689	pinctrl-0 = <&pinctrl_uart3_dte>;
690	status = "disabled";
691};
692
693/* Colibri USBH */
694&usbh1 {
695	vbus-supply = <&reg_usb_host_vbus>;
696};
697
698/* Colibri USBC */
699&usbotg {
700	dr_mode = "otg";
701	extcon = <0>, <&extcon_usbc_det>;
702	status = "disabled";
703};
704
705/* Colibri MMC */
706&usdhc1 {
707	cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
708	bus-width = <4>;
709	no-1-8-v;
710	disable-wp;
711	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
712	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
713	pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
714	pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
715	pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>;
716	vmmc-supply = <&reg_module_3v3>;
717	vqmmc-supply = <&vgen3_reg>;
718	status = "disabled";
719};
720
721/* eMMC */
722&usdhc3 {
723	bus-width = <8>;
724	no-1-8-v;
725	non-removable;
726	pinctrl-names = "default";
727	pinctrl-0 = <&pinctrl_usdhc3>;
728	vqmmc-supply = <&reg_module_3v3>;
729	status = "okay";
730};
731
732&weim {
733	pinctrl-names = "default";
734	pinctrl-0 = <&pinctrl_weim_sram  &pinctrl_weim_cs0
735		     &pinctrl_weim_cs1   &pinctrl_weim_cs2
736		     &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
737	#address-cells = <2>;
738	#size-cells = <1>;
739	status = "disabled";
740};
741
742&iomuxc {
743	pinctrl-names = "default";
744	pinctrl-0 = <&pinctrl_usbh_oc_1>;
745
746	/* Atmel MXT touchsceen + Capacitive Touch Adapter */
747	/* NOTE: This pin group conflicts with pin groups
748	 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously.
749	 */
750	pinctrl_atmel_adap: atmeladaptergrp {
751		fsl,pins = <
752			MX6QDL_PAD_GPIO_9__GPIO1_IO09   0xb0b1  /* SODIMM  28 */
753			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1  /* SODIMM  30 */
754		>;
755	};
756
757	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
758	/* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and
759	 * pinctrl_weim_cs2. Don't use them simultaneously.
760	 */
761	pinctrl_atmel_conn: atmelconnectorgrp {
762		fsl,pins = <
763			MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0xb0b1  /* SODIMM_107 */
764			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1  /* SODIMM_106 */
765		>;
766	};
767
768	pinctrl_audmux: audmuxgrp {
769		fsl,pins = <
770			MX6QDL_PAD_KEY_COL0__AUD5_TXC	0x130b0
771			MX6QDL_PAD_KEY_ROW0__AUD5_TXD	0x130b0
772			MX6QDL_PAD_KEY_COL1__AUD5_TXFS	0x130b0
773			MX6QDL_PAD_KEY_ROW1__AUD5_RXD	0x130b0
774		>;
775	};
776
777	pinctrl_cam_mclk: cammclkgrp {
778		fsl,pins = <
779			/* Parallel Camera CAM sys_mclk */
780			MX6QDL_PAD_NANDF_CS2__CCM_CLKO2	0x00b0
781		>;
782	};
783
784	/* CSI pins used as GPIOs */
785	pinctrl_csi_gpio_1: csigpio1grp {
786		fsl,pins = <
787			MX6QDL_PAD_EIM_D18__GPIO3_IO18   0x1b0b0
788			MX6QDL_PAD_EIM_A19__GPIO2_IO19   0x1b0b0
789			MX6QDL_PAD_EIM_D29__GPIO3_IO29   0x130b0
790			MX6QDL_PAD_EIM_A23__GPIO6_IO06   0x1b0b0
791			MX6QDL_PAD_EIM_A20__GPIO2_IO18   0x1b0b0
792			MX6QDL_PAD_EIM_A17__GPIO2_IO21   0x1b0b0
793			MX6QDL_PAD_EIM_A18__GPIO2_IO20   0x1b0b0
794			MX6QDL_PAD_EIM_EB3__GPIO2_IO31   0x1b0b0
795			MX6QDL_PAD_EIM_D17__GPIO3_IO17   0x1b0b0
796			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
797			MX6QDL_PAD_SD2_CMD__GPIO1_IO11   0x1b0b0
798			MX6QDL_PAD_SD2_DAT0__GPIO1_IO15  0x1b0b0
799		>;
800	};
801
802	pinctrl_csi_gpio_2: csigpio2grp {
803		fsl,pins = <
804			MX6QDL_PAD_EIM_A24__GPIO5_IO04   0x1b0b0
805		>;
806	};
807
808	pinctrl_ecspi4: ecspi4grp {
809		fsl,pins = <
810			/* SPI CS */
811			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x000b1
812			MX6QDL_PAD_EIM_D22__ECSPI4_MISO	0x100b1
813			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI	0x100b1
814			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
815		>;
816	};
817
818	pinctrl_enet: enetgrp {
819		fsl,pins = <
820			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
821			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
822			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
823			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
824			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
825			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
826			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
827			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
828			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
829			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	((1<<30) | 0x1b0b0)
830		>;
831	};
832
833	pinctrl_flexcan1: flexcan1grp {
834		fsl,pins = <
835			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
836			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
837		>;
838	};
839
840	pinctrl_flexcan2: flexcan2grp {
841		fsl,pins = <
842			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
843			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
844		>;
845	};
846
847	pinctrl_gpio_1: gpio1grp {
848		fsl,pins = <
849			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20     0x1b0b0
850			MX6QDL_PAD_EIM_D27__GPIO3_IO27      0x1b0b0
851			MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
852			MX6QDL_PAD_NANDF_D3__GPIO2_IO03     0x1b0b0
853			MX6QDL_PAD_NANDF_D4__GPIO2_IO04     0x1b0b0
854			MX6QDL_PAD_NANDF_D6__GPIO2_IO06     0x1b0b0
855			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08     0x1b0b0
856			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11     0x1b0b0
857		>;
858	};
859	pinctrl_gpio_2: gpio2grp {
860		fsl,pins = <
861			MX6QDL_PAD_GPIO_7__GPIO1_IO07       0x1b0b0
862			MX6QDL_PAD_GPIO_8__GPIO1_IO08       0x1b0b0
863		>;
864	};
865
866	pinctrl_gpio_bl_on: gpioblongrp {
867		fsl,pins = <
868			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x1b0b0
869		>;
870	};
871
872	pinctrl_gpio_keys: gpiokeysgrp {
873		fsl,pins = <
874			MX6QDL_PAD_EIM_A16__GPIO2_IO22		0x130b0
875		>;
876	};
877
878	pinctrl_hdmi_ddc: hdmiddcgrp {
879		fsl,pins = <
880			MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
881			MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
882		>;
883	};
884
885	pinctrl_i2c2: i2c2grp {
886		fsl,pins = <
887			MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
888			MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
889		>;
890	};
891
892	pinctrl_i2c2_gpio: i2c2gpiogrp {
893		fsl,pins = <
894			MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
895			MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
896		>;
897	};
898
899	pinctrl_i2c3: i2c3grp {
900		fsl,pins = <
901			MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
902			MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
903		>;
904	};
905
906	pinctrl_i2c3_gpio: i2c3gpiogrp {
907		fsl,pins = <
908			MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
909			MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
910		>;
911	};
912
913	pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
914		fsl,pins = <
915			MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12	0xb0b1
916			MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13	0xb0b1
917			MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14	0xb0b1
918			MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15	0xb0b1
919			MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16	0xb0b1
920			MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17	0xb0b1
921			MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18	0xb0b1
922			MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19	0xb0b1
923			MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK	0xb0b1
924			MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC	0xb0b1
925			MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC	0xb0b1
926			/* Disable PWM pins on camera interface */
927			MX6QDL_PAD_GPIO_1__GPIO1_IO01		0x40
928			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09		0x40
929		>;
930	};
931
932	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
933		fsl,pins = <
934			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0xa1
935			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0xa1
936			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0xa1
937			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0xa1
938			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0xa1
939			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0xa1
940			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0xa1
941			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0xa1
942			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0xa1
943			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0xa1
944			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0xa1
945			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0xa1
946			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0xa1
947			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0xa1
948			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0xa1
949			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0xa1
950			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0xa1
951			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0xa1
952			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0xa1
953			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0xa1
954			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0xa1
955			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0xa1
956		>;
957	};
958
959	pinctrl_lvds_transceiver: lvdstxgrp {
960		fsl,pins = <
961			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM  95 */
962			MX6QDL_PAD_GPIO_7__GPIO1_IO07   0x0b030 /* SODIMM  55 */
963			MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x03030 /* SODIMM  63 */
964			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM  99 */
965		>;
966	};
967
968	pinctrl_mic_gnd: micgndgrp {
969		fsl,pins = <
970			/* Controls Mic GND, PU or '1' pull Mic GND to GND */
971			MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
972		>;
973	};
974
975	pinctrl_mmc_cd: mmccdgrp {
976		fsl,pins = <
977			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x1b0b1
978		>;
979	};
980
981	pinctrl_mmc_cd_sleep: mmccdslpgrp {
982		fsl,pins = <
983			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x0
984		>;
985	};
986
987	pinctrl_pwm1: pwm1grp {
988		fsl,pins = <
989			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b1
990		>;
991	};
992
993	pinctrl_pwm2: pwm2grp {
994		fsl,pins = <
995			MX6QDL_PAD_EIM_A21__GPIO2_IO17	0x00040
996			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
997		>;
998	};
999
1000	pinctrl_pwm3: pwm3grp {
1001		fsl,pins = <
1002			MX6QDL_PAD_EIM_A22__GPIO2_IO16	0x00040
1003			MX6QDL_PAD_SD4_DAT1__PWM3_OUT	0x1b0b1
1004		>;
1005	};
1006
1007	pinctrl_pwm4: pwm4grp {
1008		fsl,pins = <
1009			MX6QDL_PAD_SD4_DAT2__PWM4_OUT	0x1b0b1
1010		>;
1011	};
1012
1013	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
1014		fsl,pins = <
1015			/* SODIMM 129 / USBH_PEN */
1016			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x0f058
1017		>;
1018	};
1019
1020	pinctrl_sgtl5000: sgtl5000grp {
1021		fsl,pins = <
1022			/* SGTL5000 sys_mclk */
1023			MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x000b0
1024		>;
1025	};
1026
1027	pinctrl_spdif: spdifgrp {
1028		fsl,pins = <
1029			MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1030		>;
1031	};
1032
1033	pinctrl_touch_int: gpiotouchintgrp {
1034		fsl,pins = <
1035			/* STMPE811 interrupt */
1036			MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
1037		>;
1038	};
1039
1040	pinctrl_uart1_dce: uart1dcegrp {
1041		fsl,pins = <
1042			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1043			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1044		>;
1045	};
1046
1047	/* DTE mode */
1048	pinctrl_uart1_dte: uart1dtegrp {
1049		fsl,pins = <
1050			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
1051			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
1052			MX6QDL_PAD_EIM_D19__UART1_RTS_B	0x1b0b1
1053			MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
1054		>;
1055	};
1056
1057	/* Additional DTR, DSR, DCD */
1058	pinctrl_uart1_ctrl: uart1ctrlgrp {
1059		fsl,pins = <
1060			MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
1061			MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
1062			MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
1063		>;
1064	};
1065
1066	pinctrl_uart2_dte: uart2dtegrp {
1067		fsl,pins = <
1068			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
1069			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
1070			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
1071			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
1072		>;
1073	};
1074
1075	pinctrl_uart3_dte: uart3dtegrp {
1076		fsl,pins = <
1077			MX6QDL_PAD_SD4_CLK__UART3_TX_DATA	0x1b0b1
1078			MX6QDL_PAD_SD4_CMD__UART3_RX_DATA	0x1b0b1
1079		>;
1080	};
1081
1082	pinctrl_usbc_det: usbcdetgrp {
1083		fsl,pins = <
1084			/* SODIMM 137 / USBC_DET */
1085			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
1086			/* USBC_DET_OVERWRITE */
1087			MX6QDL_PAD_RGMII_RXC__GPIO6_IO30	0x0f058
1088			/* USBC_DET_EN */
1089			MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26	0x0f058
1090		>;
1091	};
1092
1093	pinctrl_usbc_id_1: usbcid1grp {
1094		fsl,pins = <
1095			/* USBC_ID */
1096			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
1097		>;
1098	};
1099
1100	pinctrl_usbh_oc_1: usbhoc1grp {
1101		fsl,pins = <
1102			/* USBH_OC */
1103			MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
1104		>;
1105	};
1106
1107	pinctrl_usdhc1: usdhc1grp {
1108		fsl,pins = <
1109			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
1110			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
1111			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
1112			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
1113			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
1114			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
1115		>;
1116	};
1117
1118	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1119		fsl,pins = <
1120			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x170b1
1121			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x100b1
1122			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
1123			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
1124			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
1125			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
1126		>;
1127	};
1128
1129	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1130		fsl,pins = <
1131			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x170f1
1132			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x100f1
1133			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
1134			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
1135			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
1136			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
1137		>;
1138	};
1139
1140	/* avoid backfeeding with removed card power */
1141	pinctrl_usdhc1_sleep: usdhc1sleepgrp {
1142		fsl,pins = <
1143			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x3000
1144			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x3000
1145			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x3000
1146			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x3000
1147			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x3000
1148			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x3000
1149		>;
1150	};
1151
1152	pinctrl_usdhc3: usdhc3grp {
1153		fsl,pins = <
1154			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
1155			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
1156			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
1157			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
1158			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
1159			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
1160			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
1161			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
1162			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
1163			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
1164			/* eMMC reset */
1165			MX6QDL_PAD_SD3_RST__SD3_RESET	0x17059
1166		>;
1167	};
1168
1169	pinctrl_weim_cs0: weimcs0grp {
1170		fsl,pins = <
1171			/* nEXT_CS0 */
1172			MX6QDL_PAD_EIM_CS0__EIM_CS0_B	0xb0b1
1173		>;
1174	};
1175
1176	pinctrl_weim_cs1: weimcs1grp {
1177		fsl,pins = <
1178			/* nEXT_CS1 */
1179			MX6QDL_PAD_EIM_CS1__EIM_CS1_B	0xb0b1
1180		>;
1181	};
1182
1183	pinctrl_weim_cs2: weimcs2grp {
1184		fsl,pins = <
1185			/* nEXT_CS2 */
1186			MX6QDL_PAD_SD2_DAT1__EIM_CS2_B	0xb0b1
1187		>;
1188	};
1189
1190	/* ADDRESS[16:18] [25] used as GPIO */
1191	pinctrl_weim_gpio_1: weimgpio1grp {
1192		fsl,pins = <
1193			MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x1b0b0
1194			MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16	0x1b0b0
1195			MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x1b0b0
1196			MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
1197			MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13	0x1b0b0
1198			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x1b0b0
1199			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x1b0b0
1200			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
1201			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
1202			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
1203		>;
1204	};
1205
1206	/* ADDRESS[19:24] used as GPIO */
1207	pinctrl_weim_gpio_2: weimgpio2grp {
1208		fsl,pins = <
1209			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x1b0b0
1210			MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13	0x1b0b0
1211			MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
1212			MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x1b0b0
1213			MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16	0x1b0b0
1214			MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x1b0b0
1215			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x1b0b0
1216			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
1217			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
1218		>;
1219	};
1220
1221	/* DATA[16:31] used as GPIO */
1222	pinctrl_weim_gpio_3: weimgpio3grp {
1223		fsl,pins = <
1224			MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x1b0b0
1225			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x1b0b0
1226			MX6QDL_PAD_EIM_LBA__GPIO2_IO27		0x1b0b0
1227			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0x1b0b0
1228			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
1229			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0
1230			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x1b0b0
1231			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
1232			MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x1b0b0
1233			MX6QDL_PAD_NANDF_CS0__GPIO6_IO11	0x1b0b0
1234			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x1b0b0
1235			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x1b0b0
1236			MX6QDL_PAD_NANDF_CLE__GPIO6_IO07	0x1b0b0
1237			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10	0x1b0b0
1238			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x1b0b0
1239		>;
1240	};
1241
1242	/* DQM[0:3] used as GPIO */
1243	pinctrl_weim_gpio_4: weimgpio4grp {
1244		fsl,pins = <
1245			MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0x1b0b0
1246			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x1b0b0
1247			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
1248			MX6QDL_PAD_SD2_DAT2__GPIO1_IO13		0x1b0b0
1249		>;
1250	};
1251
1252	/* RDY used as GPIO */
1253	pinctrl_weim_gpio_5: weimgpio5grp {
1254		fsl,pins = <
1255			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0x1b0b0
1256		>;
1257	};
1258
1259	/* ADDRESS[16] DATA[30] used as GPIO */
1260	pinctrl_weim_gpio_6: weimgpio6grp {
1261		fsl,pins = <
1262			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0
1263			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
1264		>;
1265	};
1266
1267	pinctrl_weim_npwe: weimnpwegrp {
1268		fsl,pins = <
1269			MX6QDL_PAD_RGMII_TD2__GPIO6_IO22	0x130b0
1270			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x0040
1271		>;
1272	};
1273
1274	pinctrl_weim_sram: weimsramgrp {
1275		fsl,pins = <
1276			/* Data */
1277			MX6QDL_PAD_CSI0_DAT4__EIM_DATA02	0x1b0b0
1278			MX6QDL_PAD_CSI0_DAT5__EIM_DATA03	0x1b0b0
1279			MX6QDL_PAD_CSI0_DAT6__EIM_DATA04	0x1b0b0
1280			MX6QDL_PAD_CSI0_DAT7__EIM_DATA05	0x1b0b0
1281			MX6QDL_PAD_CSI0_DAT8__EIM_DATA06	0x1b0b0
1282			MX6QDL_PAD_CSI0_DAT9__EIM_DATA07	0x1b0b0
1283			MX6QDL_PAD_CSI0_DAT12__EIM_DATA08	0x1b0b0
1284			MX6QDL_PAD_CSI0_DAT13__EIM_DATA09	0x1b0b0
1285			MX6QDL_PAD_CSI0_DAT14__EIM_DATA10	0x1b0b0
1286			MX6QDL_PAD_CSI0_DAT15__EIM_DATA11	0x1b0b0
1287			MX6QDL_PAD_CSI0_DAT16__EIM_DATA12	0x1b0b0
1288			MX6QDL_PAD_CSI0_DAT17__EIM_DATA13	0x1b0b0
1289			MX6QDL_PAD_CSI0_DAT18__EIM_DATA14	0x1b0b0
1290			MX6QDL_PAD_CSI0_DAT19__EIM_DATA15	0x1b0b0
1291			MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00	0x1b0b0
1292			MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01	0x1b0b0
1293			/* Address */
1294			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
1295			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
1296			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
1297			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
1298			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
1299			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
1300			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
1301			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
1302			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
1303			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
1304			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
1305			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
1306			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
1307			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
1308			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
1309			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
1310			/* Ctrl */
1311			MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
1312			MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
1313		>;
1314	};
1315
1316	pinctrl_weim_rdnwr: weimrdnwrgrp {
1317		fsl,pins = <
1318			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23	0x130b0
1319			MX6QDL_PAD_SD2_CLK__GPIO1_IO10		0x0040
1320		>;
1321	};
1322};
1323