1/* 2 * Copyright 2015 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26 27/ { 28 #address-cells = <1>; 29 #size-cells = <1>; 30 model = "ARM RealView PB11MPcore"; 31 compatible = "arm,realview-pb11mp"; 32 33 chosen { }; 34 35 aliases { 36 serial0 = &pb11mp_serial0; 37 serial1 = &pb11mp_serial1; 38 serial2 = &pb11mp_serial2; 39 serial3 = &pb11mp_serial3; 40 }; 41 42 memory { 43 device_type = "memory"; 44 /* 45 * The PB11MPCore has 512 MiB memory @ 0x70000000 46 * and the first 256 are also remapped @ 0x00000000 47 */ 48 reg = <0x70000000 0x20000000>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "arm,realview-smp"; 55 56 MP11_0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,arm11mpcore"; 59 reg = <0>; 60 next-level-cache = <&L2>; 61 }; 62 63 MP11_1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,arm11mpcore"; 66 reg = <1>; 67 next-level-cache = <&L2>; 68 }; 69 70 MP11_2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,arm11mpcore"; 73 reg = <2>; 74 next-level-cache = <&L2>; 75 }; 76 77 MP11_3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,arm11mpcore"; 80 reg = <3>; 81 next-level-cache = <&L2>; 82 }; 83 }; 84 85 /* Primary TestChip GIC synthesized with the CPU */ 86 intc_tc11mp: interrupt-controller@1f000100 { 87 compatible = "arm,tc11mp-gic"; 88 #interrupt-cells = <3>; 89 #address-cells = <1>; 90 interrupt-controller; 91 reg = <0x1f001000 0x1000>, 92 <0x1f000100 0x100>; 93 }; 94 95 L2: cache-controller@1f002000 { 96 compatible = "arm,l220-cache"; 97 reg = <0x1f002000 0x1000>; 98 interrupt-parent = <&intc_tc11mp>; 99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, 100 <0 30 IRQ_TYPE_LEVEL_HIGH>, 101 <0 31 IRQ_TYPE_LEVEL_HIGH>; 102 cache-unified; 103 cache-level = <2>; 104 /* 105 * Override default cache size, sets and 106 * associativity as these may be erroneously set 107 * up by boot loader(s), probably for safety 108 * since th outer sync operation can cause the 109 * cache to hang unless disabled. 110 */ 111 cache-size = <1048576>; // 1MB 112 cache-sets = <4096>; 113 cache-line-size = <32>; 114 arm,shared-override; 115 arm,parity-enable; 116 arm,outer-sync-disable; 117 }; 118 119 scu@1f000000 { 120 compatible = "arm,arm11mp-scu"; 121 reg = <0x1f000000 0x100>; 122 }; 123 124 timer@1f000600 { 125 compatible = "arm,arm11mp-twd-timer"; 126 reg = <0x1f000600 0x20>; 127 interrupt-parent = <&intc_tc11mp>; 128 interrupts = <1 13 0xf04>; 129 }; 130 131 watchdog@1f000620 { 132 compatible = "arm,arm11mp-twd-wdt"; 133 reg = <0x1f000620 0x20>; 134 interrupt-parent = <&intc_tc11mp>; 135 interrupts = <1 14 0xf04>; 136 }; 137 138 /* PMU with one IRQ line per core */ 139 pmu { 140 compatible = "arm,arm11mpcore-pmu"; 141 interrupt-parent = <&intc_tc11mp>; 142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 143 <0 18 IRQ_TYPE_LEVEL_HIGH>, 144 <0 19 IRQ_TYPE_LEVEL_HIGH>, 145 <0 20 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; 147 }; 148 149 /* The voltage to the MMC card is hardwired at 3.3V */ 150 vmmc: regulator-vmmc { 151 compatible = "regulator-fixed"; 152 regulator-name = "vmmc"; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 regulator-boot-on; 156 }; 157 158 veth: regulator-veth { 159 compatible = "regulator-fixed"; 160 regulator-name = "veth"; 161 regulator-min-microvolt = <3300000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 }; 165 166 xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { 167 #clock-cells = <0>; 168 compatible = "fixed-clock"; 169 clock-frequency = <24000000>; 170 }; 171 172 refclk32khz: clock-32768 { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <32768>; 176 }; 177 178 timclk: clock-1000000 { 179 #clock-cells = <0>; 180 compatible = "fixed-factor-clock"; 181 clock-div = <24>; 182 clock-mult = <1>; 183 clocks = <&xtal24mhz>; 184 }; 185 186 /* FIXME: this actually hangs off the PLL clocks */ 187 pclk: clock-pclk { 188 #clock-cells = <0>; 189 compatible = "fixed-clock"; 190 clock-frequency = <0>; 191 }; 192 193 flash0@40000000 { 194 /* 2 * 32MiB NOR Flash memory */ 195 compatible = "arm,versatile-flash", "cfi-flash"; 196 reg = <0x40000000 0x04000000>; 197 bank-width = <4>; 198 partitions { 199 compatible = "arm,arm-firmware-suite"; 200 }; 201 }; 202 203 flash1@44000000 { 204 // 2 * 32MiB NOR Flash memory 205 compatible = "arm,versatile-flash", "cfi-flash"; 206 reg = <0x44000000 0x04000000>; 207 bank-width = <4>; 208 partitions { 209 compatible = "arm,arm-firmware-suite"; 210 }; 211 }; 212 213 bridge { 214 compatible = "ti,ths8134a", "ti,ths8134"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 ports { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 222 port@0 { 223 reg = <0>; 224 225 vga_bridge_in: endpoint { 226 remote-endpoint = <&clcd_pads>; 227 }; 228 }; 229 230 port@1 { 231 reg = <1>; 232 233 vga_bridge_out: endpoint { 234 remote-endpoint = <&vga_con_in>; 235 }; 236 }; 237 }; 238 }; 239 240 vga { 241 /* 242 * This DDC I2C is connected directly to the DVI portions 243 * of the connector, so it's not really working when the 244 * monitor is connected to the VGA connector. 245 */ 246 compatible = "vga-connector"; 247 ddc-i2c-bus = <&i2c1>; 248 249 port { 250 vga_con_in: endpoint { 251 remote-endpoint = <&vga_bridge_out>; 252 }; 253 }; 254 }; 255 256 soc { 257 #address-cells = <1>; 258 #size-cells = <1>; 259 compatible = "arm,realview-pb11mp-soc", "simple-bus"; 260 regmap = <&pb11mp_syscon>; 261 ranges; 262 263 pb11mp_syscon: syscon@10000000 { 264 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; 265 reg = <0x10000000 0x1000>; 266 ranges = <0x0 0x10000000 0x1000>; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 270 led@8,0 { 271 compatible = "register-bit-led"; 272 reg = <0x08 0x04>; 273 offset = <0x08>; 274 mask = <0x01>; 275 label = "versatile:0"; 276 linux,default-trigger = "heartbeat"; 277 default-state = "on"; 278 }; 279 led@8,1 { 280 compatible = "register-bit-led"; 281 reg = <0x08 0x04>; 282 offset = <0x08>; 283 mask = <0x02>; 284 label = "versatile:1"; 285 linux,default-trigger = "mmc0"; 286 default-state = "off"; 287 }; 288 led@8,2 { 289 compatible = "register-bit-led"; 290 reg = <0x08 0x04>; 291 offset = <0x08>; 292 mask = <0x04>; 293 label = "versatile:2"; 294 linux,default-trigger = "cpu0"; 295 default-state = "off"; 296 }; 297 led@8,3 { 298 compatible = "register-bit-led"; 299 reg = <0x08 0x04>; 300 offset = <0x08>; 301 mask = <0x08>; 302 label = "versatile:3"; 303 linux,default-trigger = "cpu1"; 304 default-state = "off"; 305 }; 306 led@8,4 { 307 compatible = "register-bit-led"; 308 reg = <0x08 0x04>; 309 offset = <0x08>; 310 mask = <0x10>; 311 label = "versatile:4"; 312 linux,default-trigger = "cpu2"; 313 default-state = "off"; 314 }; 315 led@8,5 { 316 compatible = "register-bit-led"; 317 reg = <0x08 0x04>; 318 offset = <0x08>; 319 mask = <0x20>; 320 label = "versatile:5"; 321 linux,default-trigger = "cpu3"; 322 default-state = "off"; 323 }; 324 led@8,6 { 325 compatible = "register-bit-led"; 326 reg = <0x08 0x04>; 327 offset = <0x08>; 328 mask = <0x40>; 329 label = "versatile:6"; 330 default-state = "off"; 331 }; 332 led@8,7 { 333 compatible = "register-bit-led"; 334 reg = <0x08 0x04>; 335 offset = <0x08>; 336 mask = <0x80>; 337 label = "versatile:7"; 338 default-state = "off"; 339 }; 340 341 oscclk0: clock-controller@c { 342 compatible = "arm,syscon-icst307"; 343 reg = <0x0c 0x04>; 344 #clock-cells = <0>; 345 lock-offset = <0x20>; 346 vco-offset = <0x0C>; 347 clocks = <&xtal24mhz>; 348 }; 349 oscclk1: clock-controller@10 { 350 compatible = "arm,syscon-icst307"; 351 reg = <0x10 0x04>; 352 #clock-cells = <0>; 353 lock-offset = <0x20>; 354 vco-offset = <0x10>; 355 clocks = <&xtal24mhz>; 356 }; 357 oscclk2: clock-controller@14 { 358 compatible = "arm,syscon-icst307"; 359 reg = <0x14 0x04>; 360 #clock-cells = <0>; 361 lock-offset = <0x20>; 362 vco-offset = <0x14>; 363 clocks = <&xtal24mhz>; 364 }; 365 oscclk3: clock-controller@18 { 366 compatible = "arm,syscon-icst307"; 367 reg = <0x18 0x04>; 368 #clock-cells = <0>; 369 lock-offset = <0x20>; 370 vco-offset = <0x18>; 371 clocks = <&xtal24mhz>; 372 }; 373 oscclk4: clock-controller@1c { 374 compatible = "arm,syscon-icst307"; 375 reg = <0x1c 0x04>; 376 #clock-cells = <0>; 377 lock-offset = <0x20>; 378 vco-offset = <0x1c>; 379 clocks = <&xtal24mhz>; 380 }; 381 oscclk5: clock-controller@d4 { 382 compatible = "arm,syscon-icst307"; 383 reg = <0xd4 0x04>; 384 #clock-cells = <0>; 385 lock-offset = <0x20>; 386 vco-offset = <0xd4>; 387 clocks = <&xtal24mhz>; 388 }; 389 oscclk6: clock-controller@d8 { 390 compatible = "arm,syscon-icst307"; 391 reg = <0xd8 0x04>; 392 #clock-cells = <0>; 393 lock-offset = <0x20>; 394 vco-offset = <0xd8>; 395 clocks = <&xtal24mhz>; 396 }; 397 }; 398 399 sp810_syscon: sysctl@10001000 { 400 compatible = "arm,sp810", "arm,primecell"; 401 reg = <0x10001000 0x1000>; 402 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 403 clock-names = "refclk", "timclk", "apb_pclk"; 404 #clock-cells = <1>; 405 clock-output-names = "timerclk0", 406 "timerclk1", 407 "timerclk2", 408 "timerclk3"; 409 assigned-clocks = <&sp810_syscon 0>, 410 <&sp810_syscon 1>, 411 <&sp810_syscon 2>, 412 <&sp810_syscon 3>; 413 assigned-clock-parents = <&timclk>, 414 <&timclk>, 415 <&timclk>, 416 <&timclk>; 417 }; 418 419 i2c0: i2c@10002000 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 compatible = "arm,versatile-i2c"; 423 reg = <0x10002000 0x1000>; 424 425 rtc@68 { 426 compatible = "dallas,ds1338"; 427 reg = <0x68>; 428 }; 429 }; 430 431 aaci: aaci@10004000 { 432 compatible = "arm,pl041", "arm,primecell"; 433 reg = <0x10004000 0x1000>; 434 interrupt-parent = <&intc_tc11mp>; 435 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&pclk>; 437 clock-names = "apb_pclk"; 438 }; 439 440 mci: mmcsd@10005000 { 441 compatible = "arm,pl18x", "arm,primecell"; 442 reg = <0x10005000 0x1000>; 443 interrupt-parent = <&intc_tc11mp>; 444 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, 445 <0 15 IRQ_TYPE_LEVEL_HIGH>; 446 /* Due to frequent FIFO overruns, use just 500 kHz */ 447 max-frequency = <500000>; 448 bus-width = <4>; 449 cap-sd-highspeed; 450 cap-mmc-highspeed; 451 clocks = <&mclk>, <&pclk>; 452 clock-names = "mclk", "apb_pclk"; 453 vmmc-supply = <&vmmc>; 454 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 455 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 456 }; 457 458 kmi0: kmi@10006000 { 459 compatible = "arm,pl050", "arm,primecell"; 460 reg = <0x10006000 0x1000>; 461 interrupt-parent = <&intc_tc11mp>; 462 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&kmiclk>, <&pclk>; 464 clock-names = "KMIREFCLK", "apb_pclk"; 465 }; 466 467 kmi1: kmi@10007000 { 468 compatible = "arm,pl050", "arm,primecell"; 469 reg = <0x10007000 0x1000>; 470 interrupt-parent = <&intc_tc11mp>; 471 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&kmiclk>, <&pclk>; 473 clock-names = "KMIREFCLK", "apb_pclk"; 474 }; 475 476 pb11mp_serial0: serial@10009000 { 477 compatible = "arm,pl011", "arm,primecell"; 478 reg = <0x10009000 0x1000>; 479 interrupt-parent = <&intc_tc11mp>; 480 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&uartclk>, <&pclk>; 482 clock-names = "uartclk", "apb_pclk"; 483 }; 484 485 pb11mp_serial1: serial@1000a000 { 486 compatible = "arm,pl011", "arm,primecell"; 487 reg = <0x1000a000 0x1000>; 488 interrupt-parent = <&intc_tc11mp>; 489 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&uartclk>, <&pclk>; 491 clock-names = "uartclk", "apb_pclk"; 492 }; 493 494 pb11mp_serial2: serial@1000b000 { 495 compatible = "arm,pl011", "arm,primecell"; 496 reg = <0x1000b000 0x1000>; 497 interrupt-parent = <&intc_pb11mp>; 498 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&uartclk>, <&pclk>; 500 clock-names = "uartclk", "apb_pclk"; 501 }; 502 503 pb11mp_serial3: serial@1000c000 { 504 compatible = "arm,pl011", "arm,primecell"; 505 reg = <0x1000c000 0x1000>; 506 interrupt-parent = <&intc_pb11mp>; 507 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&uartclk>, <&pclk>; 509 clock-names = "uartclk", "apb_pclk"; 510 }; 511 512 spi@1000d000 { 513 compatible = "arm,pl022", "arm,primecell"; 514 reg = <0x1000d000 0x1000>; 515 interrupt-parent = <&intc_pb11mp>; 516 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&sspclk>, <&pclk>; 518 clock-names = "sspclk", "apb_pclk"; 519 }; 520 521 watchdog@1000f000 { 522 compatible = "arm,sp805", "arm,primecell"; 523 reg = <0x1000f000 0x1000>; 524 interrupt-parent = <&intc_pb11mp>; 525 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&wdogclk>, <&pclk>; 527 clock-names = "wdog_clk", "apb_pclk"; 528 status = "disabled"; 529 }; 530 531 watchdog@10010000 { 532 compatible = "arm,sp805", "arm,primecell"; 533 reg = <0x10010000 0x1000>; 534 interrupt-parent = <&intc_pb11mp>; 535 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&wdogclk>, <&pclk>; 537 clock-names = "wdog_clk", "apb_pclk"; 538 }; 539 540 timer01: timer@10011000 { 541 compatible = "arm,sp804", "arm,primecell"; 542 reg = <0x10011000 0x1000>; 543 interrupt-parent = <&intc_tc11mp>; 544 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 545 arm,sp804-has-irq = <1>; 546 clocks = <&sp810_syscon 0>, 547 <&sp810_syscon 1>, 548 <&pclk>; 549 clock-names = "timer0clk", 550 "timer1clk", 551 "apb_pclk"; 552 }; 553 554 timer23: timer@10012000 { 555 compatible = "arm,sp804", "arm,primecell"; 556 reg = <0x10012000 0x1000>; 557 interrupt-parent = <&intc_tc11mp>; 558 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 559 arm,sp804-has-irq = <1>; 560 clocks = <&sp810_syscon 2>, 561 <&sp810_syscon 3>, 562 <&pclk>; 563 clock-names = "timer0clk", 564 "timer1clk", 565 "apb_pclk"; 566 }; 567 568 gpio0: gpio@10013000 { 569 compatible = "arm,pl061", "arm,primecell"; 570 reg = <0x10013000 0x1000>; 571 gpio-controller; 572 interrupt-parent = <&intc_pb11mp>; 573 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 clocks = <&pclk>; 578 clock-names = "apb_pclk"; 579 }; 580 581 gpio1: gpio@10014000 { 582 compatible = "arm,pl061", "arm,primecell"; 583 reg = <0x10014000 0x1000>; 584 gpio-controller; 585 interrupt-parent = <&intc_pb11mp>; 586 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 587 #gpio-cells = <2>; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 clocks = <&pclk>; 591 clock-names = "apb_pclk"; 592 }; 593 594 gpio2: gpio@10015000 { 595 compatible = "arm,pl061", "arm,primecell"; 596 reg = <0x10015000 0x1000>; 597 gpio-controller; 598 interrupt-parent = <&intc_pb11mp>; 599 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 600 #gpio-cells = <2>; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 clocks = <&pclk>; 604 clock-names = "apb_pclk"; 605 }; 606 607 i2c1: i2c@10016000 { 608 #address-cells = <1>; 609 #size-cells = <0>; 610 compatible = "arm,versatile-i2c"; 611 reg = <0x10016000 0x1000>; 612 }; 613 614 rtc: rtc@10017000 { 615 compatible = "arm,pl031", "arm,primecell"; 616 reg = <0x10017000 0x1000>; 617 interrupt-parent = <&intc_tc11mp>; 618 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&pclk>; 620 clock-names = "apb_pclk"; 621 }; 622 623 timer45: timer@10018000 { 624 compatible = "arm,sp804", "arm,primecell"; 625 reg = <0x10018000 0x1000>; 626 clocks = <&timclk>, <&timclk>, <&pclk>; 627 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 628 status = "disabled"; 629 }; 630 631 timer67: timer@10019000 { 632 compatible = "arm,sp804", "arm,primecell"; 633 reg = <0x10019000 0x1000>; 634 clocks = <&timclk>, <&timclk>, <&pclk>; 635 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 636 status = "disabled"; 637 }; 638 639 640 clcd@10020000 { 641 compatible = "arm,pl111", "arm,primecell"; 642 reg = <0x10020000 0x1000>; 643 interrupt-parent = <&intc_pb11mp>; 644 interrupt-names = "combined"; 645 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&oscclk4>, <&pclk>; 647 clock-names = "clcdclk", "apb_pclk"; 648 /* 1024x768 16bpp @65MHz works fine */ 649 max-memory-bandwidth = <95000000>; 650 651 port { 652 clcd_pads: endpoint { 653 remote-endpoint = <&vga_bridge_in>; 654 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 655 }; 656 }; 657 }; 658 659 /* 660 * This GIC on the Platform Baseboard is cascaded off the 661 * TestChip GIC 662 */ 663 intc_pb11mp: interrupt-controller@1e000000 { 664 compatible = "arm,arm11mp-gic"; 665 #interrupt-cells = <3>; 666 #address-cells = <1>; 667 interrupt-controller; 668 reg = <0x1e001000 0x1000>, 669 <0x1e000000 0x100>; 670 interrupt-parent = <&intc_tc11mp>; 671 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 672 }; 673 674 /* SMSC 9118 ethernet with PHY and EEPROM */ 675 ethernet@4e000000 { 676 compatible = "smsc,lan9118", "smsc,lan9115"; 677 reg = <0x4e000000 0x10000>; 678 interrupt-parent = <&intc_tc11mp>; 679 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 680 phy-mode = "mii"; 681 reg-io-width = <4>; 682 smsc,irq-active-high; 683 smsc,irq-push-pull; 684 vdd33a-supply = <&veth>; 685 vddvario-supply = <&veth>; 686 }; 687 688 usb@4f000000 { 689 compatible = "nxp,usb-isp1761"; 690 reg = <0x4f000000 0x20000>; 691 interrupt-parent = <&intc_tc11mp>; 692 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 693 dr_mode = "peripheral"; 694 }; 695 }; 696}; 697