1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq5018-dwc3 18 - qcom,ipq5332-dwc3 19 - qcom,ipq5424-dwc3 20 - qcom,ipq6018-dwc3 21 - qcom,ipq8064-dwc3 22 - qcom,ipq8074-dwc3 23 - qcom,ipq9574-dwc3 24 - qcom,msm8953-dwc3 25 - qcom,msm8994-dwc3 26 - qcom,msm8996-dwc3 27 - qcom,msm8998-dwc3 28 - qcom,qcm2290-dwc3 29 - qcom,qcs404-dwc3 30 - qcom,qcs615-dwc3 31 - qcom,qcs8300-dwc3 32 - qcom,qdu1000-dwc3 33 - qcom,sa8775p-dwc3 34 - qcom,sar2130p-dwc3 35 - qcom,sc7180-dwc3 36 - qcom,sc7280-dwc3 37 - qcom,sc8180x-dwc3 38 - qcom,sc8180x-dwc3-mp 39 - qcom,sc8280xp-dwc3 40 - qcom,sc8280xp-dwc3-mp 41 - qcom,sdm660-dwc3 42 - qcom,sdm670-dwc3 43 - qcom,sdm845-dwc3 44 - qcom,sdx55-dwc3 45 - qcom,sdx65-dwc3 46 - qcom,sdx75-dwc3 47 - qcom,sm4250-dwc3 48 - qcom,sm6115-dwc3 49 - qcom,sm6125-dwc3 50 - qcom,sm6350-dwc3 51 - qcom,sm6375-dwc3 52 - qcom,sm8150-dwc3 53 - qcom,sm8250-dwc3 54 - qcom,sm8350-dwc3 55 - qcom,sm8450-dwc3 56 - qcom,sm8550-dwc3 57 - qcom,sm8650-dwc3 58 - qcom,x1e80100-dwc3 59 - qcom,x1e80100-dwc3-mp 60 - const: qcom,dwc3 61 62 reg: 63 description: Offset and length of register set for QSCRATCH wrapper 64 maxItems: 1 65 66 "#address-cells": 67 enum: [ 1, 2 ] 68 69 "#size-cells": 70 enum: [ 1, 2 ] 71 72 ranges: true 73 74 power-domains: 75 description: specifies a phandle to PM domain provider node 76 maxItems: 1 77 78 required-opps: 79 maxItems: 1 80 81 clocks: 82 description: | 83 Several clocks are used, depending on the variant. Typical ones are:: 84 - cfg_noc:: System Config NOC clock. 85 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 86 60MHz for HS operation. 87 - iface:: System bus AXI clock. 88 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 89 power mode (U3). 90 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 91 mode. Its frequency should be 19.2MHz. 92 minItems: 1 93 maxItems: 9 94 95 clock-names: 96 minItems: 1 97 maxItems: 9 98 99 resets: 100 maxItems: 1 101 102 interconnects: 103 maxItems: 2 104 105 interconnect-names: 106 items: 107 - const: usb-ddr 108 - const: apps-usb 109 110 interrupts: 111 description: | 112 Different types of interrupts are used based on HS PHY used on target: 113 - pwr_event: Used for wakeup based on other power events. 114 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 115 hs_phy_irq which is not triggered by default and its 116 functionality is mutually exclusive to that of 117 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 118 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 119 expose only a single IRQ whose behavior can be modified 120 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 121 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 122 of PHY address space. 123 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 124 DM pads of the SoC. These are used for wakeup 125 only on SoCs with non-QUSB2 targets with 126 exception of SDM670/SDM845/SM6350. 127 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 128 minItems: 2 129 maxItems: 18 130 131 interrupt-names: 132 minItems: 2 133 maxItems: 18 134 135 qcom,select-utmi-as-pipe-clk: 136 description: 137 If present, disable USB3 pipe_clk requirement. 138 Used when dwc3 operates without SSPHY and only 139 HS/FS/LS modes are supported. 140 type: boolean 141 142 wakeup-source: true 143 144# Required child node: 145 146patternProperties: 147 "^usb@[0-9a-f]+$": 148 $ref: snps,dwc3.yaml# 149 unevaluatedProperties: false 150 151 properties: 152 wakeup-source: false 153 154required: 155 - compatible 156 - reg 157 - "#address-cells" 158 - "#size-cells" 159 - ranges 160 - clocks 161 - clock-names 162 - interrupts 163 - interrupt-names 164 165allOf: 166 - if: 167 properties: 168 compatible: 169 contains: 170 enum: 171 - qcom,ipq4019-dwc3 172 - qcom,ipq5332-dwc3 173 then: 174 properties: 175 clocks: 176 maxItems: 3 177 clock-names: 178 items: 179 - const: core 180 - const: sleep 181 - const: mock_utmi 182 183 - if: 184 properties: 185 compatible: 186 contains: 187 enum: 188 - qcom,ipq8064-dwc3 189 then: 190 properties: 191 clocks: 192 items: 193 - description: Master/Core clock, has to be >= 125 MHz 194 for SS operation and >= 60MHz for HS operation. 195 clock-names: 196 items: 197 - const: core 198 199 - if: 200 properties: 201 compatible: 202 contains: 203 enum: 204 - qcom,ipq9574-dwc3 205 - qcom,msm8953-dwc3 206 - qcom,msm8996-dwc3 207 - qcom,msm8998-dwc3 208 - qcom,qcs8300-dwc3 209 - qcom,sa8775p-dwc3 210 - qcom,sc7180-dwc3 211 - qcom,sc7280-dwc3 212 - qcom,sdm670-dwc3 213 - qcom,sdm845-dwc3 214 - qcom,sdx55-dwc3 215 - qcom,sdx65-dwc3 216 - qcom,sdx75-dwc3 217 - qcom,sm6350-dwc3 218 then: 219 properties: 220 clocks: 221 maxItems: 5 222 clock-names: 223 items: 224 - const: cfg_noc 225 - const: core 226 - const: iface 227 - const: sleep 228 - const: mock_utmi 229 230 - if: 231 properties: 232 compatible: 233 contains: 234 enum: 235 - qcom,ipq6018-dwc3 236 then: 237 properties: 238 clocks: 239 minItems: 3 240 maxItems: 4 241 clock-names: 242 oneOf: 243 - items: 244 - const: core 245 - const: sleep 246 - const: mock_utmi 247 - items: 248 - const: cfg_noc 249 - const: core 250 - const: sleep 251 - const: mock_utmi 252 253 - if: 254 properties: 255 compatible: 256 contains: 257 enum: 258 - qcom,ipq8074-dwc3 259 - qcom,qdu1000-dwc3 260 then: 261 properties: 262 clocks: 263 maxItems: 4 264 clock-names: 265 items: 266 - const: cfg_noc 267 - const: core 268 - const: sleep 269 - const: mock_utmi 270 271 - if: 272 properties: 273 compatible: 274 contains: 275 enum: 276 - qcom,ipq5018-dwc3 277 - qcom,msm8994-dwc3 278 - qcom,qcs404-dwc3 279 then: 280 properties: 281 clocks: 282 maxItems: 4 283 clock-names: 284 items: 285 - const: core 286 - const: iface 287 - const: sleep 288 - const: mock_utmi 289 290 - if: 291 properties: 292 compatible: 293 contains: 294 enum: 295 - qcom,sc8280xp-dwc3 296 - qcom,sc8280xp-dwc3-mp 297 - qcom,x1e80100-dwc3 298 - qcom,x1e80100-dwc3-mp 299 then: 300 properties: 301 clocks: 302 maxItems: 9 303 clock-names: 304 items: 305 - const: cfg_noc 306 - const: core 307 - const: iface 308 - const: sleep 309 - const: mock_utmi 310 - const: noc_aggr 311 - const: noc_aggr_north 312 - const: noc_aggr_south 313 - const: noc_sys 314 315 - if: 316 properties: 317 compatible: 318 contains: 319 enum: 320 - qcom,sdm660-dwc3 321 then: 322 properties: 323 clocks: 324 minItems: 4 325 maxItems: 5 326 clock-names: 327 oneOf: 328 - items: 329 - const: cfg_noc 330 - const: core 331 - const: iface 332 - const: sleep 333 - const: mock_utmi 334 - items: 335 - const: cfg_noc 336 - const: core 337 - const: sleep 338 - const: mock_utmi 339 340 - if: 341 properties: 342 compatible: 343 contains: 344 enum: 345 - qcom,qcm2290-dwc3 346 - qcom,qcs615-dwc3 347 - qcom,sar2130p-dwc3 348 - qcom,sc8180x-dwc3 349 - qcom,sc8180x-dwc3-mp 350 - qcom,sm6115-dwc3 351 - qcom,sm6125-dwc3 352 - qcom,sm8150-dwc3 353 - qcom,sm8250-dwc3 354 - qcom,sm8450-dwc3 355 - qcom,sm8550-dwc3 356 - qcom,sm8650-dwc3 357 then: 358 properties: 359 clocks: 360 minItems: 6 361 clock-names: 362 items: 363 - const: cfg_noc 364 - const: core 365 - const: iface 366 - const: sleep 367 - const: mock_utmi 368 - const: xo 369 370 - if: 371 properties: 372 compatible: 373 contains: 374 enum: 375 - qcom,sm8350-dwc3 376 then: 377 properties: 378 clocks: 379 minItems: 5 380 maxItems: 6 381 clock-names: 382 minItems: 5 383 items: 384 - const: cfg_noc 385 - const: core 386 - const: iface 387 - const: sleep 388 - const: mock_utmi 389 - const: xo 390 391 - if: 392 properties: 393 compatible: 394 contains: 395 enum: 396 - qcom,ipq5018-dwc3 397 - qcom,ipq6018-dwc3 398 - qcom,ipq8074-dwc3 399 - qcom,msm8953-dwc3 400 - qcom,msm8998-dwc3 401 then: 402 properties: 403 interrupts: 404 minItems: 2 405 maxItems: 3 406 interrupt-names: 407 minItems: 2 408 items: 409 - const: pwr_event 410 - const: qusb2_phy 411 - const: ss_phy_irq 412 413 - if: 414 properties: 415 compatible: 416 contains: 417 enum: 418 - qcom,msm8996-dwc3 419 - qcom,qcs404-dwc3 420 - qcom,sdm660-dwc3 421 - qcom,sm6115-dwc3 422 - qcom,sm6125-dwc3 423 then: 424 properties: 425 interrupts: 426 minItems: 3 427 maxItems: 4 428 interrupt-names: 429 minItems: 3 430 items: 431 - const: pwr_event 432 - const: qusb2_phy 433 - const: hs_phy_irq 434 - const: ss_phy_irq 435 436 - if: 437 properties: 438 compatible: 439 contains: 440 enum: 441 - qcom,ipq5332-dwc3 442 then: 443 properties: 444 interrupts: 445 maxItems: 3 446 interrupt-names: 447 items: 448 - const: pwr_event 449 - const: dp_hs_phy_irq 450 - const: dm_hs_phy_irq 451 452 - if: 453 properties: 454 compatible: 455 contains: 456 enum: 457 - qcom,x1e80100-dwc3 458 then: 459 properties: 460 interrupts: 461 minItems: 3 462 maxItems: 4 463 interrupt-names: 464 minItems: 3 465 items: 466 - const: pwr_event 467 - const: dp_hs_phy_irq 468 - const: dm_hs_phy_irq 469 - const: ss_phy_irq 470 471 - if: 472 properties: 473 compatible: 474 contains: 475 enum: 476 - qcom,ipq4019-dwc3 477 - qcom,ipq8064-dwc3 478 - qcom,msm8994-dwc3 479 - qcom,qcs615-dwc3 480 - qcom,qcs8300-dwc3 481 - qcom,qdu1000-dwc3 482 - qcom,sa8775p-dwc3 483 - qcom,sc7180-dwc3 484 - qcom,sc7280-dwc3 485 - qcom,sc8180x-dwc3 486 - qcom,sc8280xp-dwc3 487 - qcom,sdm670-dwc3 488 - qcom,sdm845-dwc3 489 - qcom,sdx55-dwc3 490 - qcom,sdx65-dwc3 491 - qcom,sdx75-dwc3 492 - qcom,sm4250-dwc3 493 - qcom,sm6350-dwc3 494 - qcom,sm8150-dwc3 495 - qcom,sm8250-dwc3 496 - qcom,sm8350-dwc3 497 - qcom,sm8450-dwc3 498 - qcom,sm8550-dwc3 499 - qcom,sm8650-dwc3 500 then: 501 properties: 502 interrupts: 503 minItems: 4 504 maxItems: 5 505 interrupt-names: 506 minItems: 4 507 items: 508 - const: pwr_event 509 - const: hs_phy_irq 510 - const: dp_hs_phy_irq 511 - const: dm_hs_phy_irq 512 - const: ss_phy_irq 513 514 - if: 515 properties: 516 compatible: 517 contains: 518 enum: 519 - qcom,sc8180x-dwc3-mp 520 - qcom,x1e80100-dwc3-mp 521 then: 522 properties: 523 interrupts: 524 minItems: 10 525 maxItems: 10 526 interrupt-names: 527 items: 528 - const: pwr_event_1 529 - const: pwr_event_2 530 - const: hs_phy_1 531 - const: hs_phy_2 532 - const: dp_hs_phy_1 533 - const: dm_hs_phy_1 534 - const: dp_hs_phy_2 535 - const: dm_hs_phy_2 536 - const: ss_phy_1 537 - const: ss_phy_2 538 539 - if: 540 properties: 541 compatible: 542 contains: 543 enum: 544 - qcom,sc8280xp-dwc3-mp 545 then: 546 properties: 547 interrupts: 548 minItems: 18 549 maxItems: 18 550 interrupt-names: 551 items: 552 - const: pwr_event_1 553 - const: pwr_event_2 554 - const: pwr_event_3 555 - const: pwr_event_4 556 - const: hs_phy_1 557 - const: hs_phy_2 558 - const: hs_phy_3 559 - const: hs_phy_4 560 - const: dp_hs_phy_1 561 - const: dm_hs_phy_1 562 - const: dp_hs_phy_2 563 - const: dm_hs_phy_2 564 - const: dp_hs_phy_3 565 - const: dm_hs_phy_3 566 - const: dp_hs_phy_4 567 - const: dm_hs_phy_4 568 - const: ss_phy_1 569 - const: ss_phy_2 570 571additionalProperties: false 572 573examples: 574 - | 575 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 576 #include <dt-bindings/interrupt-controller/arm-gic.h> 577 #include <dt-bindings/interrupt-controller/irq.h> 578 soc { 579 #address-cells = <2>; 580 #size-cells = <2>; 581 582 usb@a6f8800 { 583 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 584 reg = <0 0x0a6f8800 0 0x400>; 585 586 #address-cells = <2>; 587 #size-cells = <2>; 588 ranges; 589 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 590 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 591 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 592 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 593 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 594 clock-names = "cfg_noc", 595 "core", 596 "iface", 597 "sleep", 598 "mock_utmi"; 599 600 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 601 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 602 assigned-clock-rates = <19200000>, <150000000>; 603 604 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 607 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 608 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 609 interrupt-names = "pwr_event", "hs_phy_irq", 610 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 611 612 power-domains = <&gcc USB30_PRIM_GDSC>; 613 614 resets = <&gcc GCC_USB30_PRIM_BCR>; 615 616 usb@a600000 { 617 compatible = "snps,dwc3"; 618 reg = <0 0x0a600000 0 0xcd00>; 619 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 620 iommus = <&apps_smmu 0x740 0>; 621 snps,dis_u2_susphy_quirk; 622 snps,dis_enblslpm_quirk; 623 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 624 phy-names = "usb2-phy", "usb3-phy"; 625 }; 626 }; 627 }; 628