1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QPIC NAND controller
8
9maintainers:
10  - Md sadre Alam <quic_mdalam@quicinc.com>
11
12description:
13  The QCOM QPIC-SPI-NAND flash controller is an extended version of
14  the QCOM QPIC NAND flash controller. It can work both in serial
15  and parallel mode. It supports typical SPI-NAND page cache
16  operations in single, dual or quad IO mode with pipelined ECC
17  encoding/decoding using the QPIC ECC HW engine.
18
19allOf:
20  - $ref: /schemas/spi/spi-controller.yaml#
21
22properties:
23  compatible:
24    enum:
25      - qcom,ipq9574-snand
26
27  reg:
28    maxItems: 1
29
30  clocks:
31    maxItems: 3
32
33  clock-names:
34    items:
35      - const: core
36      - const: aon
37      - const: iom
38
39  dmas:
40    items:
41      - description: tx DMA channel
42      - description: rx DMA channel
43      - description: cmd DMA channel
44
45  dma-names:
46    items:
47      - const: tx
48      - const: rx
49      - const: cmd
50
51required:
52  - compatible
53  - reg
54  - clocks
55  - clock-names
56
57unevaluatedProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
62    spi@79b0000 {
63        compatible = "qcom,ipq9574-snand";
64        reg = <0x1ac00000 0x800>;
65
66        clocks = <&gcc GCC_QPIC_CLK>,
67                 <&gcc GCC_QPIC_AHB_CLK>,
68                 <&gcc GCC_QPIC_IO_MACRO_CLK>;
69        clock-names = "core", "aon", "iom";
70
71        #address-cells = <1>;
72        #size-cells = <0>;
73
74        flash@0 {
75            compatible = "spi-nand";
76            reg = <0>;
77            #address-cells = <1>;
78            #size-cells = <1>;
79            nand-ecc-engine = <&qpic_nand>;
80            nand-ecc-strength = <4>;
81            nand-ecc-step-size = <512>;
82        };
83    };
84