1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale SPI (Serial Peripheral Interface) controller
8
9maintainers:
10  - J. Neuschäfer <j.ne@posteo.net>
11
12properties:
13  compatible:
14    enum:
15      - fsl,spi
16      - aeroflexgaisler,spictrl
17
18  reg:
19    maxItems: 1
20
21  cell-index:
22    $ref: /schemas/types.yaml#/definitions/uint32
23    description: |
24      QE SPI subblock index.
25      0: QE subblock SPI1
26      1: QE subblock SPI2
27
28  mode:
29    description: SPI operation mode
30    enum:
31      - cpu
32      - cpu-qe
33
34  interrupts:
35    maxItems: 1
36
37  clock-frequency:
38    description: input clock frequency to non FSL_SOC cores
39
40  cs-gpios: true
41
42  fsl,spisel_boot:
43    $ref: /schemas/types.yaml#/definitions/flag
44    description:
45      For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used
46      as chip select for a slave device. Use reg = <number of gpios> in the
47      corresponding child node, i.e. 0 if the cs-gpios property is not present.
48
49required:
50  - compatible
51  - reg
52  - mode
53  - interrupts
54
55allOf:
56  - $ref: spi-controller.yaml#
57
58unevaluatedProperties: false
59
60examples:
61  - |
62    #include <dt-bindings/interrupt-controller/irq.h>
63
64    spi@4c0 {
65        compatible = "fsl,spi";
66        reg = <0x4c0 0x40>;
67        cell-index = <0>;
68        interrupts = <82 0>;
69        mode = "cpu";
70        cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING          // device reg=<0>
71                    &gpio 19 IRQ_TYPE_EDGE_RISING>;        // device reg=<1>
72    };
73
74...
75