1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Synchronous Audio Interface (SAI).
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  The SAI is based on I2S module that used communicating with audio codecs,
14  which provides a synchronous audio interface that supports fullduplex
15  serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16  codec/DSP interfaces.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - fsl,imx6ul-sai
24              - fsl,imx7d-sai
25          - const: fsl,imx6sx-sai
26
27      - items:
28          - enum:
29              - fsl,imx8mm-sai
30              - fsl,imx8mn-sai
31              - fsl,imx8mp-sai
32          - const: fsl,imx8mq-sai
33
34      - items:
35          - enum:
36              - fsl,imx6sx-sai
37              - fsl,imx7ulp-sai
38              - fsl,imx8mq-sai
39              - fsl,imx8qm-sai
40              - fsl,imx8ulp-sai
41              - fsl,imx93-sai
42              - fsl,imx95-sai
43              - fsl,vf610-sai
44      - items:
45          - enum:
46              - fsl,imx94-sai
47          - const: fsl,imx95-sai
48
49  reg:
50    maxItems: 1
51
52  clocks:
53    items:
54      - description: The ipg clock for register access
55      - description: master clock source 0 (obsoleted)
56      - description: master clock source 1
57      - description: master clock source 2
58      - description: master clock source 3
59      - description: PLL clock source for 8kHz series
60      - description: PLL clock source for 11kHz series
61    minItems: 4
62
63  clock-names:
64    oneOf:
65      - items:
66          - const: bus
67          - const: mclk0
68          - const: mclk1
69          - const: mclk2
70          - const: mclk3
71          - const: pll8k
72          - const: pll11k
73        minItems: 5
74      - items:
75          - const: bus
76          - const: mclk1
77          - const: mclk2
78          - const: mclk3
79          - const: pll8k
80          - const: pll11k
81        minItems: 4
82
83  power-domains:
84    maxItems: 1
85
86  dmas:
87    minItems: 1
88    maxItems: 2
89
90  dma-names:
91    minItems: 1
92    items:
93      - enum: [ rx, tx ]
94      - const: tx
95
96  interrupts:
97    items:
98      - description: receive and transmit interrupt
99
100  ports:
101    $ref: /schemas/graph.yaml#/properties/ports
102    properties:
103      port@0:
104        $ref: audio-graph-port.yaml#
105        unevaluatedProperties: false
106        description: port for TX and RX
107
108      port@1:
109        $ref: audio-graph-port.yaml#
110        unevaluatedProperties: false
111        description: port for TX only
112
113      port@2:
114        $ref: audio-graph-port.yaml#
115        unevaluatedProperties: false
116        description: port for RX only
117
118  big-endian:
119    description: |
120      required if all the SAI registers are big-endian rather than little-endian.
121    type: boolean
122
123  fsl,dataline:
124    $ref: /schemas/types.yaml#/definitions/uint32-matrix
125    description: |
126      Configure the dataline. It has 3 value for each configuration
127    maxItems: 16
128    items:
129      items:
130        - description: format Default(0), I2S(1) or PDM(2)
131          enum: [0, 1, 2]
132        - description: dataline mask for 'rx'
133        - description: dataline mask for 'tx'
134
135  fsl,sai-mclk-direction-output:
136    description: SAI will output the SAI MCLK clock.
137    type: boolean
138
139  fsl,sai-synchronous-rx:
140    description: |
141      SAI will work in the synchronous mode (sync Tx with Rx) which means
142      both the transmitter and the receiver will send and receive data by
143      following receiver's bit clocks and frame sync clocks.
144    type: boolean
145
146  fsl,sai-asynchronous:
147    description: |
148      SAI will work in the asynchronous mode, which means both transmitter
149      and receiver will send and receive data by following their own bit clocks
150      and frame sync clocks separately.
151      If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
152      default synchronous mode (sync Rx with Tx) will be used, which means both
153      transmitter and receiver will send and receive data by following clocks
154      of transmitter.
155    type: boolean
156
157  fsl,shared-interrupt:
158    description: Interrupt is shared with other modules.
159    type: boolean
160
161  lsb-first:
162    description: |
163      Configures whether the LSB or the MSB is transmitted
164      first for the fifo data. If this property is absent,
165      the MSB is transmitted first as default, or the LSB
166      is transmitted first.
167    type: boolean
168
169  "#sound-dai-cells":
170    const: 0
171    description: optional, some dts node didn't add it.
172
173allOf:
174  - $ref: dai-common.yaml#
175  - if:
176      required:
177        - fsl,sai-asynchronous
178    then:
179      properties:
180        fsl,sai-synchronous-rx: false
181
182required:
183  - compatible
184  - reg
185  - clocks
186  - clock-names
187  - dmas
188  - dma-names
189  - interrupts
190
191unevaluatedProperties: false
192
193examples:
194  - |
195    #include <dt-bindings/interrupt-controller/arm-gic.h>
196    #include <dt-bindings/clock/vf610-clock.h>
197    sai2: sai@40031000 {
198        compatible = "fsl,vf610-sai";
199        reg = <0x40031000 0x1000>;
200        interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
201        pinctrl-names = "default";
202        pinctrl-0 = <&pinctrl_sai2_1>;
203        clocks = <&clks VF610_CLK_PLATFORM_BUS>,
204                 <&clks VF610_CLK_SAI2>,
205                 <&clks 0>, <&clks 0>;
206        clock-names = "bus", "mclk1", "mclk2", "mclk3";
207        dma-names = "rx", "tx";
208        dmas = <&edma0 0 20>, <&edma0 0 21>;
209        big-endian;
210        lsb-first;
211    };
212
213  - |
214    #include <dt-bindings/interrupt-controller/arm-gic.h>
215    #include <dt-bindings/clock/imx8mm-clock.h>
216    sai1: sai@30010000 {
217        compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
218        reg = <0x30010000 0x10000>;
219        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
220        clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
221                 <&clk IMX8MM_CLK_DUMMY>,
222                 <&clk IMX8MM_CLK_SAI1_ROOT>,
223                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
224        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
225        dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
226        dma-names = "rx", "tx";
227        fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
228        #sound-dai-cells = <0>;
229
230        ports {
231            #address-cells = <1>;
232            #size-cells = <0>;
233
234            port@1 {
235                reg = <1>;
236                playback-only;
237
238                sai1_endpoint0: endpoint {
239                   dai-tdm-slot-num = <8>;
240                   dai-tdm-slot-width = <32>;
241                   dai-tdm-slot-width-map = <32 8 32>;
242                   dai-format = "dsp_a";
243                   bitclock-master;
244                   frame-master;
245                   remote-endpoint = <&mcodec01_ep>;
246                };
247            };
248
249            port@2 {
250                reg = <2>;
251                capture-only;
252
253                sai1_endpoint1: endpoint {
254                    dai-tdm-slot-num = <8>;
255                    dai-tdm-slot-width = <32>;
256                    dai-tdm-slot-width-map = <32 8 32>;
257                    dai-format = "dsp_a";
258                    remote-endpoint = <&fe02_ep>;
259                };
260            };
261        };
262    };
263