1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX TPM PWM controller
8
9maintainers:
10  - Shawn Guo <shawnguo@kernel.org>
11  - Sascha Hauer <s.hauer@pengutronix.de>
12  - Fabio Estevam <festevam@gmail.com>
13
14description: |
15  The TPM counter and period counter are shared between multiple
16  channels, so all channels should use same period setting.
17
18allOf:
19  - $ref: pwm.yaml#
20
21properties:
22  "#pwm-cells":
23    const: 3
24
25  compatible:
26    oneOf:
27      - enum:
28          - fsl,imx7ulp-pwm
29      - items:
30          - enum:
31              - fsl,imx93-pwm
32              - fsl,imx94-pwm
33              - fsl,imx95-pwm
34          - const: fsl,imx7ulp-pwm
35
36  reg:
37    maxItems: 1
38
39  assigned-clocks:
40    maxItems: 1
41
42  assigned-clock-parents:
43    maxItems: 1
44
45  clocks:
46    maxItems: 1
47
48required:
49  - compatible
50  - reg
51  - clocks
52
53additionalProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/imx7ulp-clock.h>
58
59    pwm@40250000 {
60        compatible = "fsl,imx7ulp-pwm";
61        reg = <0x40250000 0x1000>;
62        assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
63        assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
64        clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
65        #pwm-cells = <3>;
66    };
67