1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Naneng Combo Phy
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3562-naneng-combphy
16      - rockchip,rk3568-naneng-combphy
17      - rockchip,rk3576-naneng-combphy
18      - rockchip,rk3588-naneng-combphy
19
20  reg:
21    maxItems: 1
22
23  clocks:
24    items:
25      - description: reference clock
26      - description: apb clock
27      - description: pipe clock
28
29  clock-names:
30    items:
31      - const: ref
32      - const: apb
33      - const: pipe
34
35  resets:
36    minItems: 1
37    maxItems: 2
38
39  reset-names:
40    minItems: 1
41    items:
42      - const: phy
43      - const: apb
44
45  rockchip,enable-ssc:
46    type: boolean
47    description:
48      The option SSC can be enabled for U3, SATA and PCIE.
49      Most commercially available platforms use SSC to reduce EMI.
50
51  rockchip,ext-refclk:
52    type: boolean
53    description:
54      Many PCIe connections, especially backplane connections,
55      require a synchronous reference clock between the two link partners.
56      To achieve this a common clock source, referred to as REFCLK in
57      the PCI Express Card Electromechanical Specification,
58      should be used by both ends of the PCIe link.
59      In PCIe mode one can choose to use an internal or an external reference
60      clock.
61      By default the internal clock is selected. The PCIe PHY provides a 100MHz
62      differential clock output(optional with SSC) for system applications.
63      When selecting this option an externally 100MHz differential
64      reference clock needs to be provided to the PCIe PHY.
65
66  rockchip,pipe-grf:
67    $ref: /schemas/types.yaml#/definitions/phandle
68    description:
69      Some additional phy settings are accessed through GRF regs.
70
71  rockchip,pipe-phy-grf:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description:
74      Some additional pipe settings are accessed through GRF regs.
75
76  "#phy-cells":
77    const: 1
78
79required:
80  - compatible
81  - reg
82  - clocks
83  - clock-names
84  - resets
85  - rockchip,pipe-grf
86  - rockchip,pipe-phy-grf
87  - "#phy-cells"
88
89allOf:
90  - if:
91      properties:
92        compatible:
93          contains:
94            const: rockchip,rk3568-naneng-combphy
95    then:
96      properties:
97        resets:
98          maxItems: 1
99        reset-names:
100          maxItems: 1
101  - if:
102      properties:
103        compatible:
104          contains:
105            const: rockchip,rk3588-naneng-combphy
106    then:
107      properties:
108        resets:
109          minItems: 2
110        reset-names:
111          minItems: 2
112      required:
113        - reset-names
114
115additionalProperties: false
116
117examples:
118  - |
119    #include <dt-bindings/clock/rk3568-cru.h>
120
121    pipegrf: syscon@fdc50000 {
122      compatible = "rockchip,rk3568-pipe-grf", "syscon";
123      reg = <0xfdc50000 0x1000>;
124    };
125
126    pipe_phy_grf0: syscon@fdc70000 {
127      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
128      reg = <0xfdc70000 0x1000>;
129    };
130
131    combphy0: phy@fe820000 {
132      compatible = "rockchip,rk3568-naneng-combphy";
133      reg = <0xfe820000 0x100>;
134      clocks = <&pmucru CLK_PCIEPHY0_REF>,
135               <&cru PCLK_PIPEPHY0>,
136               <&cru PCLK_PIPE>;
137      clock-names = "ref", "apb", "pipe";
138      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
139      assigned-clock-rates = <100000000>;
140      resets = <&cru SRST_PIPEPHY0>;
141      rockchip,pipe-grf = <&pipegrf>;
142      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
143      #phy-cells = <1>;
144    };
145