1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm PCIe Endpoint Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    oneOf:
15      - enum:
16          - qcom,sa8775p-pcie-ep
17          - qcom,sar2130p-pcie-ep
18          - qcom,sdx55-pcie-ep
19          - qcom,sm8450-pcie-ep
20      - items:
21          - const: qcom,sdx65-pcie-ep
22          - const: qcom,sdx55-pcie-ep
23
24  reg:
25    minItems: 6
26    items:
27      - description: Qualcomm-specific PARF configuration registers
28      - description: DesignWare PCIe registers
29      - description: External local bus interface registers
30      - description: Address Translation Unit (ATU) registers
31      - description: Memory region used to map remote RC address space
32      - description: BAR memory region
33      - description: DMA register space
34
35  reg-names:
36    minItems: 6
37    items:
38      - const: parf
39      - const: dbi
40      - const: elbi
41      - const: atu
42      - const: addr_space
43      - const: mmio
44      - const: dma
45
46  clocks:
47    minItems: 5
48    maxItems: 9
49
50  clock-names:
51    minItems: 5
52    maxItems: 9
53
54  qcom,perst-regs:
55    description: Reference to a syscon representing TCSR followed by the two
56                 offsets within syscon for Perst enable and Perst separation
57                 enable registers
58    $ref: /schemas/types.yaml#/definitions/phandle-array
59    items:
60      - items:
61          - description: Syscon to TCSR system registers
62          - description: Perst enable offset
63          - description: Perst separation enable offset
64
65  interrupts:
66    minItems: 2
67    items:
68      - description: PCIe Global interrupt
69      - description: PCIe Doorbell interrupt
70      - description: DMA interrupt
71
72  interrupt-names:
73    minItems: 2
74    items:
75      - const: global
76      - const: doorbell
77      - const: dma
78
79  iommus:
80    maxItems: 1
81
82  reset-gpios:
83    description: GPIO used as PERST# input signal
84    maxItems: 1
85
86  wake-gpios:
87    description: GPIO used as WAKE# output signal
88    maxItems: 1
89
90  interconnects:
91    maxItems: 2
92
93  interconnect-names:
94    items:
95      - const: pcie-mem
96      - const: cpu-pcie
97
98  dma-coherent: true
99
100  resets:
101    maxItems: 1
102
103  reset-names:
104    const: core
105
106  power-domains:
107    maxItems: 1
108
109  phys:
110    maxItems: 1
111
112  phy-names:
113    const: pciephy
114
115  num-lanes:
116    default: 2
117
118required:
119  - compatible
120  - reg
121  - reg-names
122  - clocks
123  - clock-names
124  - interrupts
125  - interrupt-names
126  - reset-gpios
127  - interconnects
128  - interconnect-names
129  - resets
130  - reset-names
131  - power-domains
132
133allOf:
134  - $ref: pci-ep.yaml#
135
136  - if:
137      properties:
138        compatible:
139          contains:
140            enum:
141              - qcom,sar2130p-pcie-ep
142    then:
143      properties:
144        clocks:
145          items:
146            - description: PCIe Auxiliary clock
147            - description: PCIe CFG AHB clock
148            - description: PCIe Master AXI clock
149            - description: PCIe Slave AXI clock
150            - description: PCIe Slave Q2A AXI clock
151            - description: PCIe DDRSS SF TBU clock
152            - description: PCIe AGGRE NOC AXI clock
153            - description: PCIe CFG NOC AXI clock
154            - description: PCIe QMIP AHB clock
155        clock-names:
156          items:
157            - const: aux
158            - const: cfg
159            - const: bus_master
160            - const: bus_slave
161            - const: slave_q2a
162            - const: ddrss_sf_tbu
163            - const: aggre_noc_axi
164            - const: cnoc_sf_axi
165            - const: qmip_pcie_ahb
166
167  - if:
168      properties:
169        compatible:
170          contains:
171            enum:
172              - qcom,sdx55-pcie-ep
173    then:
174      properties:
175        reg:
176          minItems: 6
177          maxItems: 6
178        reg-names:
179          minItems: 6
180          maxItems: 6
181        interrupts:
182          minItems: 2
183          maxItems: 2
184        interrupt-names:
185          minItems: 2
186          maxItems: 2
187        iommus: false
188    else:
189      properties:
190        reg:
191          minItems: 7
192          maxItems: 7
193        reg-names:
194          minItems: 7
195          maxItems: 7
196        interrupts:
197          minItems: 3
198          maxItems: 3
199        interrupt-names:
200          minItems: 3
201          maxItems: 3
202      required:
203        - iommus
204
205  - if:
206      properties:
207        compatible:
208          contains:
209            enum:
210              - qcom,sdx55-pcie-ep
211    then:
212      properties:
213        clocks:
214          items:
215            - description: PCIe Auxiliary clock
216            - description: PCIe CFG AHB clock
217            - description: PCIe Master AXI clock
218            - description: PCIe Slave AXI clock
219            - description: PCIe Slave Q2A AXI clock
220            - description: PCIe Sleep clock
221            - description: PCIe Reference clock
222        clock-names:
223          items:
224            - const: aux
225            - const: cfg
226            - const: bus_master
227            - const: bus_slave
228            - const: slave_q2a
229            - const: sleep
230            - const: ref
231
232  - if:
233      properties:
234        compatible:
235          contains:
236            enum:
237              - qcom,sm8450-pcie-ep
238    then:
239      properties:
240        clocks:
241          items:
242            - description: PCIe Auxiliary clock
243            - description: PCIe CFG AHB clock
244            - description: PCIe Master AXI clock
245            - description: PCIe Slave AXI clock
246            - description: PCIe Slave Q2A AXI clock
247            - description: PCIe Reference clock
248            - description: PCIe DDRSS SF TBU clock
249            - description: PCIe AGGRE NOC AXI clock
250        clock-names:
251          items:
252            - const: aux
253            - const: cfg
254            - const: bus_master
255            - const: bus_slave
256            - const: slave_q2a
257            - const: ref
258            - const: ddrss_sf_tbu
259            - const: aggre_noc_axi
260
261  - if:
262      properties:
263        compatible:
264          contains:
265            enum:
266              - qcom,sa8775p-pcie-ep
267    then:
268      properties:
269        clocks:
270          items:
271            - description: PCIe Auxiliary clock
272            - description: PCIe CFG AHB clock
273            - description: PCIe Master AXI clock
274            - description: PCIe Slave AXI clock
275            - description: PCIe Slave Q2A AXI clock
276        clock-names:
277          items:
278            - const: aux
279            - const: cfg
280            - const: bus_master
281            - const: bus_slave
282            - const: slave_q2a
283
284unevaluatedProperties: false
285
286examples:
287  - |
288    #include <dt-bindings/clock/qcom,gcc-sdx55.h>
289    #include <dt-bindings/gpio/gpio.h>
290    #include <dt-bindings/interconnect/qcom,sdx55.h>
291    #include <dt-bindings/interrupt-controller/arm-gic.h>
292
293    pcie_ep: pcie-ep@1c00000 {
294        compatible = "qcom,sdx55-pcie-ep";
295        reg = <0x01c00000 0x3000>,
296              <0x40000000 0xf1d>,
297              <0x40000f20 0xc8>,
298              <0x40001000 0x1000>,
299              <0x40002000 0x1000>,
300              <0x01c03000 0x3000>;
301        reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
302                    "mmio";
303
304        clocks = <&gcc GCC_PCIE_AUX_CLK>,
305             <&gcc GCC_PCIE_CFG_AHB_CLK>,
306             <&gcc GCC_PCIE_MSTR_AXI_CLK>,
307             <&gcc GCC_PCIE_SLV_AXI_CLK>,
308             <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
309             <&gcc GCC_PCIE_SLEEP_CLK>,
310             <&gcc GCC_PCIE_0_CLKREF_CLK>;
311        clock-names = "aux", "cfg", "bus_master", "bus_slave",
312                      "slave_q2a", "sleep", "ref";
313
314        qcom,perst-regs = <&tcsr 0xb258 0xb270>;
315
316        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
317                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
318        interrupt-names = "global", "doorbell";
319        interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
320                        <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
321        interconnect-names = "pcie-mem", "cpu-pcie";
322        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
323        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
324        resets = <&gcc GCC_PCIE_BCR>;
325        reset-names = "core";
326        power-domains = <&gcc PCIE_GDSC>;
327        phys = <&pcie0_lane>;
328        phy-names = "pciephy";
329        max-link-speed = <3>;
330        num-lanes = <2>;
331        linux,pci-domain = <0>;
332    };
333